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前往新版Gitcode,体验更适合开发者的 AI 搜索 >>
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47863f7e
编写于
7月 16, 2021
作者:
Z
zoujr
浏览文件
操作
浏览文件
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电子邮件补丁
差异文件
[WIP] BPU: Fix numBr width not match bugs
上级
dec9f595
变更
4
显示空白变更内容
内联
并排
Showing
4 changed file
with
48 addition
and
39 deletion
+48
-39
src/main/scala/xiangshan/decoupled-frontend/BPU.scala
src/main/scala/xiangshan/decoupled-frontend/BPU.scala
+6
-5
src/main/scala/xiangshan/decoupled-frontend/Bim.scala
src/main/scala/xiangshan/decoupled-frontend/Bim.scala
+24
-19
src/main/scala/xiangshan/decoupled-frontend/FTB.scala
src/main/scala/xiangshan/decoupled-frontend/FTB.scala
+3
-3
src/main/scala/xiangshan/decoupled-frontend/uBTB.scala
src/main/scala/xiangshan/decoupled-frontend/uBTB.scala
+15
-12
未找到文件。
src/main/scala/xiangshan/decoupled-frontend/BPU.scala
浏览文件 @
47863f7e
...
...
@@ -174,7 +174,7 @@ abstract class BasePredictor(implicit p: Parameters) extends XSModule with HasBP
io
.
s2_ready
:=
true
.
B
io
.
s3_ready
:=
true
.
B
val
s0_pc
=
Mux
(
io
.
flush
.
valid
,
io
.
flush
.
bits
,
io
.
in
.
bits
.
s0_pc
)
// fetchIdx(io.f0_pc)
val
s0_pc
=
WireInit
(
Mux
(
io
.
flush
.
valid
,
io
.
flush
.
bits
,
io
.
in
.
bits
.
s0_pc
)
)
// fetchIdx(io.f0_pc)
val
s1_pc
=
RegEnable
(
s0_pc
,
io
.
s0_fire
)
val
s2_pc
=
RegEnable
(
s1_pc
,
io
.
s1_fire
)
val
s3_pc
=
RegEnable
(
s2_pc
,
io
.
s2_fire
)
...
...
@@ -278,13 +278,14 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst {
predictors
.
io
.
in
.
valid
:=
!
reset
.
asBool
&&
toFtq_fire
predictors
.
io
.
in
.
bits
.
s0_pc
:=
s0_pc
predictors
.
io
.
in
.
bits
.
ghist
:=
final_gh
predictors
.
io
.
in
.
bits
.
ghist
:=
final_gh
.
predHist
predictors
.
io
.
in
.
bits
.
resp_in
(
0
)
:=
(
0.
U
).
asTypeOf
(
new
BranchPredictionResp
)
io
.
bpu_to_ftq
.
resp
.
bits
.
hit
:=
predictors
.
io
.
out
.
bits
.
resp
.
s3
.
hit
io
.
bpu_to_ftq
.
resp
.
bits
.
preds
:=
predictors
.
io
.
out
.
bits
.
resp
.
s3
io
.
bpu_to_ftq
.
resp
.
bits
.
meta
:=
predictors
.
io
.
out
.
bits
.
resp
.
s3
.
meta
// io.bpu_to_ftq.resp.bits.hit := predictors.io.out.bits.resp.s3.hit
// io.bpu_to_ftq.resp.bits.preds := predictors.io.out.bits.resp.s3.preds
// io.bpu_to_ftq.resp.bits.meta := predictors.io.out.bits.resp.s3.meta
io
.
bpu_to_ftq
.
resp
.
bits
:=
predictors
.
io
.
out
.
bits
.
resp
.
s3
predictors
.
io
.
in
.
bits
.
toFtq_fire
:=
toFtq_fire
...
...
src/main/scala/xiangshan/decoupled-frontend/Bim.scala
浏览文件 @
47863f7e
...
...
@@ -49,14 +49,15 @@ class BIM(implicit p: Parameters) extends BasePredictor with BimParams with BPUU
val
s1_read
=
bim
.
io
.
r
.
resp
.
data
io
.
out
.
bits
.
resp
.
s1
.
preds
.
taken_mask
:=
Cat
(
0.
U
(
1.
W
),
s1_read
(
1
)(
1
),
s1_read
(
0
)(
1
))
io
.
out
.
bits
.
resp
.
s1
.
meta
:=
s1_read
// io.out.bits.resp.s1.preds.taken_mask := Cat(0.U(1.W), s1_read(1)(1), s1_read(0)(1))
io
.
out
.
bits
.
resp
.
s1
.
preds
.
taken_mask
:=
VecInit
(
Cat
(
0.
U
(
1.
W
),
s1_read
(
0
)(
1
)).
asBools
())
io
.
out
.
bits
.
resp
.
s1
.
meta
:=
s1_read
.
asUInt
()
// TODO: Replace RegNext by RegEnable
io
.
out
.
bits
.
resp
.
s2
.
preds
.
taken
:=
RegEnable
(
io
.
out
.
bits
.
resp
.
s1
.
preds
.
taken
,
io
.
s1_fire
)
io
.
out
.
bits
.
resp
.
s2
.
preds
.
taken
_mask
:=
RegEnable
(
io
.
out
.
bits
.
resp
.
s1
.
preds
.
taken_mask
,
io
.
s1_fire
)
io
.
out
.
bits
.
resp
.
s2
.
meta
:=
RegEnable
(
io
.
out
.
bits
.
resp
.
s1
.
meta
,
io
.
s1_fire
)
io
.
out
.
bits
.
resp
.
s3
.
preds
.
taken
:=
RegEnable
(
io
.
out
.
bits
.
resp
.
s2
.
preds
.
taken
,
io
.
s2_fire
)
io
.
out
.
bits
.
resp
.
s3
.
preds
.
taken
_mask
:=
RegEnable
(
io
.
out
.
bits
.
resp
.
s2
.
preds
.
taken_mask
,
io
.
s2_fire
)
io
.
out
.
bits
.
resp
.
s3
.
meta
:=
RegEnable
(
io
.
out
.
bits
.
resp
.
s2
.
meta
,
io
.
s2_fire
)
// Update logic
...
...
@@ -85,24 +86,28 @@ class BIM(implicit p: Parameters) extends BasePredictor with BimParams with BPUU
satUpdate
(
oldCtrs
(
i
),
2
,
newTakens
(
i
))
))
val
need_to_update
=
u_valid
&&
update
.
preds
.
is_br
.
reduce
(
_
||
_
)
val
need_to_update
=
VecInit
((
0
until
numBr
).
map
(
i
=>
u_valid
&&
update
.
preds
.
is_br
(
i
))
)
when
(
reset
.
asBool
)
{
wrbypass_ctr_valids
.
foreach
(
_
:=
false
.
B
)}
when
(
reset
.
asBool
)
{
wrbypass_ctr_valids
.
foreach
(
_
:=
VecInit
(
Seq
.
fill
(
numBr
)(
false
.
B
))
)}
when
(
need_to_update
)
{
when
(
wrbypass_hit
)
{
wrbypass_ctrs
(
wrbypass_hit_idx
)
:=
newCtrs
wrbypass_ctr_valids
(
wrbypass_hit_idx
)
:=
true
.
B
for
(
i
<-
0
until
numBr
)
{
when
(
need_to_update
.
reduce
(
_
||
_
))
{
when
(
wrbypass_hit
)
{
when
(
need_to_update
(
i
))
{
wrbypass_ctrs
(
wrbypass_hit_idx
)(
i
)
:=
newCtrs
(
i
)
wrbypass_ctr_valids
(
wrbypass_hit_idx
)(
i
)
:=
true
.
B
}
}.
otherwise
{
wrbypass_ctr_valids
(
wrbypass_enq_ptr
)
:=
false
.
B
when
(
need_to_update
)
{
wrbypass_ctrs
(
wrbypass_enq_ptr
)
:=
newCtrs
wrbypass_ctr_valids
(
wrbypass_enq_ptr
)
:=
true
.
B
wrbypass_ctr_valids
(
wrbypass_enq_ptr
)(
i
)
:=
false
.
B
when
(
need_to_update
(
i
))
{
wrbypass_ctrs
(
wrbypass_enq_ptr
)(
i
)
:=
newCtrs
(
i
)
wrbypass_ctr_valids
(
wrbypass_enq_ptr
)(
i
)
:=
true
.
B
}
}
}
}
when
(
need_to_update
&&
!
wrbypass_hit
)
{
when
(
need_to_update
.
reduce
(
_
||
_
)
&&
!
wrbypass_hit
)
{
wrbypass_idx
(
wrbypass_enq_ptr
)
:=
u_idx
wrbypass_enq_ptr
:=
(
wrbypass_enq_ptr
+
1.
U
)(
log2Up
(
bypassEntries
)-
1
,
0
)
}
...
...
@@ -111,6 +116,6 @@ class BIM(implicit p: Parameters) extends BasePredictor with BimParams with BPUU
valid
=
need_to_update
.
asUInt
.
orR
||
doing_reset
,
data
=
Mux
(
doing_reset
,
VecInit
(
Seq
.
fill
(
numBr
)(
2.
U
(
2.
W
))),
newCtrs
),
setIdx
=
Mux
(
doing_reset
,
resetRow
,
u_idx
),
waymask
=
Mux
(
doing_reset
,
1.
U
(
1.
W
),
need_to_update
)
waymask
=
Mux
(
doing_reset
,
Fill
(
numBr
,
1.
U
(
1.
W
)).
asUInt
(),
need_to_update
.
asUInt
()
)
)
}
src/main/scala/xiangshan/decoupled-frontend/FTB.scala
浏览文件 @
47863f7e
...
...
@@ -129,7 +129,7 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams {
VecInit
(
s1_read
.
map
(
w
=>
w
.
tag
)).
asUInt
,
s1_tag
)))
val
writeWay
=
Mux
(
s1_hit
,
s1_hit_way
,
allocWays
)
val
writeWay
=
Mux
(
s1_hit
,
s1_hit_way
,
allocWays
(
0
))
// TODO: allocWays is Vec
val
ftb_entry
=
s1_read
(
s1_hit_way
)
...
...
@@ -146,7 +146,7 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams {
io
.
out
.
bits
.
resp
.
s1
.
preds
.
taken_mask
:=
io
.
in
.
bits
.
resp_in
(
0
).
s1
.
preds
.
taken_mask
io
.
out
.
bits
.
resp
.
s1
.
preds
.
taken_mask
(
0
)
:=
ftb_entry
.
jmpValid
io
.
out
.
bits
.
resp
.
s1
.
preds
.
is_br
:=
ftb_entry
.
brValids
.
reduce
(
_
||
_
)
io
.
out
.
bits
.
resp
.
s1
.
preds
.
is_br
:=
ftb_entry
.
brValids
io
.
out
.
bits
.
resp
.
s1
.
preds
.
is_jal
:=
ftb_entry
.
jmpValid
&&
!(
ftb_entry
.
isJalr
||
ftb_entry
.
isCall
||
ftb_entry
.
isRet
)
io
.
out
.
bits
.
resp
.
s1
.
preds
.
is_jalr
:=
ftb_entry
.
isJalr
io
.
out
.
bits
.
resp
.
s1
.
preds
.
is_call
:=
ftb_entry
.
isCall
...
...
@@ -185,7 +185,7 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams {
val
u_valid
=
RegNext
(
io
.
update
.
valid
)
val
u_way_mask
=
UIntToOH
(
u_way
)
val
ftb_write
=
update
.
ftb_entry
val
ftb_write
=
WireInit
(
update
.
ftb_entry
)
ftb_write
.
valid
:=
true
.
B
ftb_write
.
tag
:=
ftbAddr
.
getTag
(
u_pc
)
...
...
src/main/scala/xiangshan/decoupled-frontend/uBTB.scala
浏览文件 @
47863f7e
...
...
@@ -62,7 +62,8 @@ class MicroBTB(implicit p: Parameters) extends BasePredictor
val
pred
=
Vec
(
numBr
,
UInt
(
2.
W
))
def
taken
=
pred
.
map
(
_
(
1
)).
reduce
(
_
||
_
)
def
taken_mask
=
{
Cat
(
jmpValid
,
brValids
(
1
)
&&
pred
(
1
)(
1
),
brValids
(
0
)
&&
pred
(
0
)(
1
))
}
// def taken_mask = { Cat(jmpValid, brValids(1) && pred(1)(1), brValids(0) && pred(0)(1)) }
def
taken_mask
=
{
Cat
(
jmpValid
,
brValids
(
0
)
&&
pred
(
0
)(
1
))
}
}
class
MicroBTBData
extends
XSBundle
...
...
@@ -131,7 +132,8 @@ class MicroBTB(implicit p: Parameters) extends BasePredictor
val
hit_and_taken_mask
=
ParallelMux
(
hits
zip
taken_masks
)
val
target
=
Mux
(
hit_and_taken_mask
=/=
0.
U
,
PriorityMux
(
hit_and_taken_mask
,
Seq
(
hit_data
.
jmpTarget
,
hit_data
.
brTargets
(
1
),
hit_data
.
brTargets
(
0
))),
// PriorityMux(hit_and_taken_mask, Seq(hit_data.jmpTarget, hit_data.brTargets(1), hit_data.brTargets(0))),
PriorityMux
(
hit_and_taken_mask
,
Seq
(
hit_data
.
jmpTarget
,
9528.
U
(
VAddrBits
.
W
),
hit_data
.
brTargets
(
0
))),
read_pc
+
(
FetchWidth
*
4
).
U
)
val
ren
=
io
.
read_pc
.
valid
...
...
@@ -141,7 +143,8 @@ class MicroBTB(implicit p: Parameters) extends BasePredictor
// }.otherwise {
// io.read_resp.brValids := 0.U(numBr.W)
// }
io
.
read_resp
.
taken_mask
:=
Mux
(
ren
,
hit_and_taken_mask
,
0.
U
((
numBr
+
1
).
W
))
// io.read_resp.taken_mask := Mux(ren, hit_and_taken_mask, 0.U((numBr+1).W))
io
.
read_resp
.
taken_mask
:=
Mux
(
ren
,
VecInit
(
hit_and_taken_mask
.
asBools
()),
VecInit
(
Seq
.
fill
(
numBr
+
1
)(
false
.
B
)))
io
.
read_resp
.
target
:=
target
io
.
read_resp
.
pred
:=
hit_meta
.
pred
io
.
read_hit
:=
hit_oh
.
orR
...
...
@@ -190,18 +193,18 @@ class MicroBTB(implicit p: Parameters) extends BasePredictor
meta
.
io
.
wdata
(
0
)
:=
Mux
(
do_reset
,
0.
U
.
asTypeOf
(
new
MicroBTBMeta
),
RegNext
(
io
.
update_write_meta
.
bits
))
meta
.
io
.
wdata
(
0
).
pred
:=
Mux
(
do_reset
,
Vec
(
numBr
,
0.
U
(
2.
W
)),
RegNext
(
update_new_pred
))
meta
.
io
.
wdata
(
0
).
pred
:=
Mux
(
do_reset
,
Vec
Init
(
Seq
.
fill
(
numBr
)(
0.
U
(
2.
W
)
)),
RegNext
(
update_new_pred
))
data
.
io
.
waddr
(
0
)
:=
Mux
(
do_reset
,
reset_way
,
RegNext
(
update_way
))
data
.
io
.
wen
(
0
)
:=
do_reset
||
RegNext
(
io
.
update_write_data
.
valid
)
data
.
io
.
wdata
(
0
)
:=
Mux
(
do_reset
,
0.
U
.
asTypeOf
(
new
MicroBTBData
),
RegNext
(
io
.
update_write_data
.
bits
))
debug_io
.
update_hit
:=
update_hit
debug_io
.
update_hit_way
:=
update_hit_way
debug_io
.
update_write_way
:=
update_way
debug_io
.
update_old_pred
:=
update_old_pred
debug_io
.
update_new_pred
:=
update_new_pred
//
debug_io.update_hit := update_hit
//
debug_io.update_hit_way := update_hit_way
//
debug_io.update_write_way := update_way
//
debug_io.update_old_pred := update_old_pred
//
debug_io.update_new_pred := update_new_pred
}
val
ubtbBanks
=
Module
(
new
UBTBBank
(
numWays
))
...
...
@@ -214,7 +217,7 @@ class MicroBTB(implicit p: Parameters) extends BasePredictor
banks
.
read_pc
.
bits
:=
s1_pc
io
.
out
.
valid
:=
io
.
s1_fire
&&
!
io
.
flush
.
valid
io
.
out
.
bits
.
resp
.
s1
.
meta
:=
read_resps
.
pred
io
.
out
.
bits
.
resp
.
s1
.
meta
:=
read_resps
.
pred
.
asUInt
()
// TODO: What ubtb meta need
io
.
out
.
bits
.
resp
.
s1
.
preds
.
target
:=
Mux
(
banks
.
read_hit
,
read_resps
.
target
,
io
.
in
.
bits
.
s0_pc
+
(
FetchWidth
*
4
).
U
)
io
.
out
.
bits
.
resp
.
s1
.
preds
.
taken_mask
:=
read_resps
.
taken_mask
// io.out.bits.resp.s1.preds.is_br := read_resps.brValids
...
...
@@ -238,8 +241,8 @@ class MicroBTB(implicit p: Parameters) extends BasePredictor
val
data_write_valid
=
u_valid
&&
u_taken
val
meta_write_valid
=
u_valid
&&
(
u_taken
||
update
.
preds
.
is_br
.
reduce
(
_
||
_
))
val
update_write_datas
=
new
MicroBTBData
val
update_write_metas
=
new
MicroBTBMeta
val
update_write_datas
=
Wire
(
new
MicroBTBData
)
val
update_write_metas
=
Wire
(
new
MicroBTBMeta
)
update_write_metas
.
valid
:=
true
.
B
update_write_metas
.
tag
:=
u_tag
...
...
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