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体验新版 GitCode,发现更多精彩内容 >>
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450e05f5
编写于
1月 19, 2021
作者:
Y
Yinan Xu
提交者:
GitHub
1月 19, 2021
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差异文件
Merge pull request #454 from RISCVERS/trace-debug
bug fixes in TLB, PTW and sbuffer
上级
d8459212
f165b11a
变更
4
显示空白变更内容
内联
并排
Showing
4 changed file
with
12 addition
and
10 deletion
+12
-10
src/main/scala/xiangshan/cache/dtlb.scala
src/main/scala/xiangshan/cache/dtlb.scala
+1
-1
src/main/scala/xiangshan/cache/icache.scala
src/main/scala/xiangshan/cache/icache.scala
+1
-1
src/main/scala/xiangshan/cache/ptw.scala
src/main/scala/xiangshan/cache/ptw.scala
+8
-6
src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala
src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala
+2
-2
未找到文件。
src/main/scala/xiangshan/cache/dtlb.scala
浏览文件 @
450e05f5
...
...
@@ -406,7 +406,7 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
waiting
:=
false
.
B
}
// ptw <> DontCare // TODO: need check it
ptw
.
req
.
valid
:=
hasMissReq
&&
!
sfence
.
valid
&&
!
waiting
ptw
.
req
.
valid
:=
hasMissReq
&&
!
sfence
.
valid
&&
!
waiting
&&
!
RegNext
(
refill
)
ptw
.
resp
.
ready
:=
waiting
// val ptwReqSeq = Wire(Seq.fill(Width)(new comBundle()))
...
...
src/main/scala/xiangshan/cache/icache.scala
浏览文件 @
450e05f5
...
...
@@ -378,7 +378,7 @@ class ICache extends ICacheModule
(
0
until
blockWords
).
map
{
r
=>
val
row
=
dataHitWay
.
asTypeOf
(
Vec
(
blockWords
,
UInt
(
encRowBits
.
W
)))(
r
)
val
decodedRow
=
cacheParams
.
dataCode
.
decode
(
row
)
assert
(!(
s3_valid
&&
s3_hit
&&
decodedRow
.
uncorrectable
))
//
assert(!(s3_valid && s3_hit && decodedRow.uncorrectable))
decodedRow
.
corrected
}
)
...
...
src/main/scala/xiangshan/cache/ptw.scala
浏览文件 @
450e05f5
...
...
@@ -326,7 +326,8 @@ class PTWImp(outer: PTW) extends PtwModule(outer){
val
tlbl2
=
Module
(
new
SRAMWrapper
(
"L2TLB"
,
new
L2TlbEntires
(
num
=
TlbL2LineSize
,
tagLen
=
TlbL2TagLen
),
set
=
TlbL2LineNum
set
=
TlbL2LineNum
,
singlePort
=
true
))
// (total 256, one line is 4 => 64 lines)
val
tlbv
=
RegInit
(
0.
U
(
TlbL2LineNum
.
W
))
// valid
val
tlbg
=
Reg
(
UInt
(
TlbL2LineNum
.
W
))
// global
...
...
@@ -341,7 +342,8 @@ class PTWImp(outer: PTW) extends PtwModule(outer){
val
ptwl2
=
Module
(
new
SRAMWrapper
(
"L2PTW"
,
new
PtwEntries
(
num
=
PtwL2LineSize
,
tagLen
=
PtwL2TagLen
),
set
=
PtwL2LineNum
set
=
PtwL2LineNum
,
singlePort
=
true
))
// (total 256, one line is 4 => 64 lines)
val
l2v
=
RegInit
(
0.
U
(
PtwL2LineNum
.
W
))
// valid
val
l2g
=
Reg
(
UInt
(
PtwL2LineNum
.
W
))
// global
...
...
@@ -369,7 +371,6 @@ class PTWImp(outer: PTW) extends PtwModule(outer){
* tlbl2
*/
val
(
tlbHit
,
tlbHitData
)
=
{
assert
(
tlbl2
.
io
.
r
.
req
.
ready
)
val
ridx
=
genTlbL2Idx
(
req
.
vpn
)
val
vidx
=
RegEnable
(
tlbv
(
ridx
),
validOneCycle
)
...
...
@@ -377,19 +378,20 @@ class PTWImp(outer: PTW) extends PtwModule(outer){
tlbl2
.
io
.
r
.
req
.
bits
.
apply
(
setIdx
=
ridx
)
val
ramData
=
tlbl2
.
io
.
r
.
resp
.
data
(
0
)
assert
(
tlbl2
.
io
.
r
.
req
.
ready
||
!
tlbl2
.
io
.
r
.
req
.
valid
)
XSDebug
(
tlbl2
.
io
.
r
.
req
.
valid
,
p
"tlbl2 Read rIdx:${Hexadecimal(ridx)}\n"
)
XSDebug
(
RegNext
(
tlbl2
.
io
.
r
.
req
.
valid
),
p
"tlbl2 RamData:${ramData}\n"
)
XSDebug
(
RegNext
(
tlbl2
.
io
.
r
.
req
.
valid
),
p
"tlbl2 v:${vidx} hit:${ramData.hit(req.vpn)} tlbPte:${ramData.get(req.vpn)}\n"
)
val
spHitVec
=
sp
.
zipWithIndex
.
map
{
case
(
a
,
i
)
=>
Reg
Next
(
a
.
hit
(
req
.
vpn
)
&&
spv
(
i
),
validOneCycle
)
Reg
Enable
(
a
.
hit
(
req
.
vpn
)
&&
spv
(
i
),
validOneCycle
)
}
val
spHitData
=
ParallelMux
(
spHitVec
zip
sp
)
val
spHit
=
Cat
(
spHitVec
).
orR
XSDebug
(
RegNext
(
validOneCycle
),
p
"tlbl2 sp: spHit:${spHit} spPte:${spHitData}\n"
)
assert
(
RegNext
(!(
ramData
.
hit
(
req
.
vpn
)
&&
spHit
)),
"pages should not be normal page and super page as well"
)
assert
(
RegNext
(!(
ramData
.
hit
(
req
.
vpn
)
&&
vidx
&&
spHit
&&
RegNext
(
validOneCycle
)
)),
"pages should not be normal page and super page as well"
)
(
ramData
.
hit
(
req
.
vpn
)
&&
vidx
||
spHit
,
Mux
(
spHit
,
spHitData
,
ramData
.
get
(
req
.
vpn
)))
}
...
...
@@ -418,7 +420,7 @@ class PTWImp(outer: PTW) extends PtwModule(outer){
val
idx
=
RegEnable
(
l2addr
(
log2Up
(
PtwL2LineSize
)+
log2Up
(
XLEN
/
8
)-
1
,
log2Up
(
XLEN
/
8
)),
readRam
)
val
vidx
=
RegEnable
(
l2v
(
ridx
),
readRam
)
assert
(
ptwl2
.
io
.
r
.
req
.
ready
)
assert
(
ptwl2
.
io
.
r
.
req
.
ready
||
!
readRam
)
ptwl2
.
io
.
r
.
req
.
valid
:=
readRam
ptwl2
.
io
.
r
.
req
.
bits
.
apply
(
setIdx
=
ridx
)
val
ramData
=
ptwl2
.
io
.
r
.
resp
.
data
(
0
)
...
...
src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala
浏览文件 @
450e05f5
...
...
@@ -13,9 +13,9 @@ trait HasSbufferCst extends HasXSParameter {
def
s_prepare
=
2.
U
(
2.
W
)
def
s_inflight
=
3.
U
(
2.
W
)
val
evictCycle
=
8192
val
evictCycle
=
1
<<
20
require
(
isPow2
(
evictCycle
))
val
countBits
=
1
+
log2Up
(
evictCycle
)
val
countBits
=
log2Up
(
evictCycle
+
1
)
val
SbufferIndexWidth
:
Int
=
log2Up
(
StoreBufferSize
)
// paddr = tag + offset
...
...
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