Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
OpenXiangShan
XiangShan
提交
0b829d90
X
XiangShan
项目概览
OpenXiangShan
/
XiangShan
大约 1 年 前同步成功
通知
1183
Star
3914
Fork
526
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
0
列表
看板
标记
里程碑
合并请求
0
DevOps
流水线
流水线任务
计划
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
X
XiangShan
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
0
Issue
0
列表
看板
标记
里程碑
合并请求
0
合并请求
0
Pages
DevOps
DevOps
流水线
流水线任务
计划
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
流水线任务
提交
Issue看板
体验新版 GitCode,发现更多精彩内容 >>
提交
0b829d90
编写于
7月 26, 2020
作者:
A
Allen
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
Added various debug logs.
上级
00f48c43
变更
6
显示空白变更内容
内联
并排
Showing
6 changed file
with
131 addition
and
6 deletion
+131
-6
src/main/scala/bus/tilelink/TileLink.scala
src/main/scala/bus/tilelink/TileLink.scala
+34
-0
src/main/scala/xiangshan/mem/cache/L1Cache.scala
src/main/scala/xiangshan/mem/cache/L1Cache.scala
+3
-3
src/main/scala/xiangshan/mem/cache/dcache.scala
src/main/scala/xiangshan/mem/cache/dcache.scala
+28
-2
src/main/scala/xiangshan/mem/cache/mshrs.scala
src/main/scala/xiangshan/mem/cache/mshrs.scala
+46
-0
src/main/scala/xiangshan/utils/LogUtils.scala
src/main/scala/xiangshan/utils/LogUtils.scala
+6
-0
src/test/scala/xiangshan/backend/exu/DCacheTest.scala
src/test/scala/xiangshan/backend/exu/DCacheTest.scala
+14
-1
未找到文件。
src/main/scala/bus/tilelink/TileLink.scala
浏览文件 @
0b829d90
...
...
@@ -188,6 +188,9 @@ class TLBundleA(override val params: TLParameters) extends TLAddrChannel
val
mask
=
UInt
((
params
.
dataBits
/
8
).
W
)
val
data
=
UInt
(
params
.
dataBits
.
W
)
val
corrupt
=
Bool
()
def
dump
=
printf
(
s
"$channelName opcode: %x param: %x size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n"
,
opcode
,
param
,
size
,
source
,
address
,
mask
,
data
,
corrupt
)
}
class
TLBundleB
(
override
val
params
:
TLParameters
)
extends
TLAddrChannel
...
...
@@ -201,6 +204,8 @@ class TLBundleB(override val params: TLParameters) extends TLAddrChannel
val
mask
=
UInt
((
params
.
dataBits
/
8
).
W
)
val
data
=
UInt
(
params
.
dataBits
.
W
)
val
corrupt
=
Bool
()
def
dump
=
printf
(
s
"$channelName opcode: %x param: %x size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n"
,
opcode
,
param
,
size
,
source
,
address
,
mask
,
data
,
corrupt
)
}
class
TLBundleC
(
override
val
params
:
TLParameters
)
extends
TLAddrChannel
...
...
@@ -213,6 +218,8 @@ class TLBundleC(override val params: TLParameters) extends TLAddrChannel
val
address
=
UInt
(
params
.
addressBits
.
W
)
val
data
=
UInt
(
params
.
dataBits
.
W
)
val
corrupt
=
Bool
()
def
dump
=
printf
(
s
"$channelName opcode: %x param: %x size: %x source: %d address: %x data: %x corrupt: %b\n"
,
opcode
,
param
,
size
,
source
,
address
,
data
,
corrupt
)
}
class
TLBundleD
(
override
val
params
:
TLParameters
)
extends
TLDataChannel
...
...
@@ -226,18 +233,31 @@ class TLBundleD(override val params: TLParameters) extends TLDataChannel
val
denied
=
Bool
()
val
data
=
UInt
(
params
.
dataBits
.
W
)
val
corrupt
=
Bool
()
def
dump
=
printf
(
s
"$channelName opcode: %x param: %x size: %x source: %d sink: %d denied: %b data: %x corrupt: %b\n"
,
opcode
,
param
,
size
,
source
,
sink
,
denied
,
data
,
corrupt
)
}
class
TLBundleE
(
override
val
params
:
TLParameters
)
extends
TLChannel
{
val
channelName
=
"'E' channel"
val
sink
=
UInt
(
params
.
sinkBits
.
W
)
def
dump
=
printf
(
s
"$channelName sink: %d\n"
,
sink
)
}
// TL-UL and TL-UC
class
TLUnCached
(
val
params
:
TLParameters
)
extends
Bundle
{
val
a
=
Decoupled
(
new
TLBundleA
(
params
))
val
d
=
Flipped
(
Decoupled
(
new
TLBundleD
(
params
)))
def
dump
(
cond
:
Bool
)
=
{
when
(
cond
)
{
when
(
a
.
fire
())
{
a
.
bits
.
dump
}
when
(
d
.
fire
())
{
d
.
bits
.
dump
}
}
}
}
// TL-C
...
...
@@ -245,6 +265,20 @@ class TLCached(override val params: TLParameters) extends TLUnCached(params) {
val
b
=
Flipped
(
Decoupled
(
new
TLBundleB
(
params
)))
val
c
=
Decoupled
(
new
TLBundleC
(
params
))
val
e
=
Decoupled
(
new
TLBundleE
(
params
))
override
def
dump
(
cond
:
Bool
)
=
{
super
.
dump
(
cond
)
when
(
cond
)
{
when
(
b
.
fire
())
{
b
.
bits
.
dump
}
when
(
c
.
fire
())
{
c
.
bits
.
dump
}
when
(
e
.
fire
())
{
e
.
bits
.
dump
}
}
}
}
object
TLUnCached
...
...
src/main/scala/xiangshan/mem/cache/L1Cache.scala
浏览文件 @
0b829d90
...
...
@@ -5,7 +5,7 @@ package xiangshan.mem.cache
import
chisel3._
import
chisel3.util._
import
xiangshan.
HasXSParameter
import
xiangshan.
{
HasXSParameter
,
XSModule
,
XSBundle
}
import
xiangshan.mem.MemoryOpConstants
// this file contains common building blocks that can be shared by ICache and DCache
...
...
@@ -45,8 +45,8 @@ trait HasL1CacheParameters extends HasXSParameter
def
refillCycles
=
cacheDataBeats
}
abstract
class
L1CacheModule
extends
Module
abstract
class
L1CacheModule
extends
XS
Module
with
HasL1CacheParameters
abstract
class
L1CacheBundle
extends
Bundle
abstract
class
L1CacheBundle
extends
XS
Bundle
with
HasL1CacheParameters
src/main/scala/xiangshan/mem/cache/dcache.scala
浏览文件 @
0b829d90
...
...
@@ -5,6 +5,7 @@ import chisel3.util._
import
chisel3.util.experimental.BoringUtils
import
xiangshan.mem.
{
DCacheReq
,
DCacheResp
,
LSUDMemIO
}
import
xiangshan.utils.XSDebug
import
bus.tilelink._
import
_root_.utils.
{
Code
,
RandomReplacement
,
Transpose
}
...
...
@@ -72,10 +73,10 @@ trait HasDCacheParameters extends HasL1CacheParameters {
require
(
pgIdxBits
>=
untagBits
,
s
"page aliasing problem: pgIdxBits($pgIdxBits) < untagBits($untagBits)"
)
}
abstract
class
DCacheModule
extends
Module
abstract
class
DCacheModule
extends
L1Cache
Module
with
HasDCacheParameters
abstract
class
DCacheBundle
extends
Bundle
abstract
class
DCacheBundle
extends
L1Cache
Bundle
with
HasDCacheParameters
// basic building blocks for L1 DCache
...
...
@@ -407,6 +408,24 @@ class DCache extends DCacheModule
// -------
// Pipeline
def
dump_pipeline_reqs
(
pipeline_stage_name
:
String
,
valid
:
Vec
[
Bool
],
reqs
:
Vec
[
DCacheReq
],
s0_type
:
UInt
)
=
{
(
0
until
memWidth
)
map
{
w
=>
XSDebug
(
s
"$pipeline_stage_name"
)
XSDebug
(
"channel %d: valid: %b "
,
w
.
U
,
valid
(
w
))
when
(
valid
(
w
))
{
when
(
s0_type
===
t_replay
)
{
XSDebug
(
"type: reply "
)
}
.
elsewhen
(
s0_type
===
t_lsu
)
{
XSDebug
(
"type: reply "
)
}
.
otherwise
{
XSDebug
(
"type: unknown "
)
}
XSDebug
(
"cmd: %x addr: %x data: %x mask: %x meta: %x\n"
,
reqs
(
w
).
cmd
,
reqs
(
w
).
addr
,
reqs
(
w
).
data
,
reqs
(
w
).
mask
,
reqs
(
w
).
meta
)
}
}
}
// stage 0
val
s0_valid
=
Mux
(
io
.
lsu
.
req
.
fire
(),
VecInit
(
io
.
lsu
.
req
.
bits
.
map
(
_
.
valid
)),
...
...
@@ -416,6 +435,9 @@ class DCache extends DCacheModule
replay_req
)
val
s0_type
=
Mux
(
io
.
lsu
.
req
.
fire
(),
t_lsu
,
t_replay
)
dump_pipeline_reqs
(
"DCache s0"
,
s0_valid
,
s0_req
,
s0_type
)
// Does this request need to send a response or nack
// for successfully executed load/stores, we send a resp
// for all other failures(bank conflict, blocked by mshr, in write back)
...
...
@@ -437,6 +459,8 @@ class DCache extends DCacheModule
// For replays, the metadata isn't written yet
val
s1_replay_way_en
=
RegNext
(
mshrs
.
io
.
replay
.
bits
.
way_en
)
dump_pipeline_reqs
(
"DCache s1"
,
s1_valid
,
s1_req
,
s1_type
)
// tag check
def
wayMap
[
T
<:
Data
](
f
:
Int
=>
T
)
=
VecInit
((
0
until
nWays
).
map
(
f
))
val
s1_tag_eq_way
=
widthMap
(
i
=>
wayMap
((
w
:
Int
)
=>
meta
(
i
).
io
.
resp
(
w
).
tag
===
(
s1_addr
(
i
)
>>
untagBits
)).
asUInt
)
...
...
@@ -451,6 +475,8 @@ class DCache extends DCacheModule
val
s2_valid
=
widthMap
(
w
=>
RegNext
(
s1_valid
(
w
),
init
=
false
.
B
))
dump_pipeline_reqs
(
"DCache s2"
,
s2_valid
,
s2_req
,
s2_type
)
val
s2_tag_match_way
=
RegNext
(
s1_tag_match_way
)
val
s2_tag_match
=
s2_tag_match_way
.
map
(
_
.
orR
)
val
s2_hit_state
=
widthMap
(
i
=>
Mux1H
(
s2_tag_match_way
(
i
),
wayMap
((
w
:
Int
)
=>
RegNext
(
meta
(
i
).
io
.
resp
(
w
).
coh
))))
...
...
src/main/scala/xiangshan/mem/cache/mshrs.scala
浏览文件 @
0b829d90
...
...
@@ -10,6 +10,7 @@ import chisel3._
import
chisel3.util._
import
xiangshan.mem.DCacheReq
import
xiangshan.utils.XSDebug
import
bus.tilelink._
class
DCacheReqInternal
extends
DCacheReq
...
...
@@ -380,4 +381,49 @@ class MSHRFile extends DCacheModule
sdq_val
:=
sdq_val
&
~(
UIntToOH
(
replay_arb
.
io
.
out
.
bits
.
sdq_id
)
&
Fill
(
cfg
.
nSDQ
,
free_sdq
))
|
PriorityEncoderOH
(~
sdq_val
(
cfg
.
nSDQ
-
1
,
0
))
&
Fill
(
cfg
.
nSDQ
,
sdq_enq
)
}
// print all input/output requests for debug purpose
// print req
XSDebug
(
req
.
fire
(),
"cmd: %x addr: %x data: %x mask: %x meta: %x tag_match: %b old_coh: %d old_tag: %x way_en: %x\n"
,
req
.
bits
.
cmd
,
req
.
bits
.
addr
,
req
.
bits
.
data
,
req
.
bits
.
mask
,
req
.
bits
.
meta
,
req
.
bits
.
tag_match
,
req
.
bits
.
old_meta
.
coh
.
state
,
req
.
bits
.
old_meta
.
tag
,
req
.
bits
.
way_en
)
// block hit
(
0
until
memWidth
)
map
{
w
=>
XSDebug
(
io
.
req
(
w
).
valid
&&
io
.
block_hit
(
w
),
"channel %d req block hit\n"
,
w
.
U
)
}
// print refill
XSDebug
(
io
.
refill
.
fire
(),
"addr %x data: %x wmask: %x way_en: %x\n"
,
io
.
refill
.
bits
.
addr
,
io
.
refill
.
bits
.
data
,
io
.
refill
.
bits
.
wmask
,
io
.
refill
.
bits
.
way_en
)
// print meta_write
XSDebug
(
io
.
meta_write
.
fire
(),
"idx %x way_en: %x old_tag: %x new_coh: %d new_tag: %x\n"
,
io
.
meta_write
.
bits
.
idx
,
io
.
meta_write
.
bits
.
way_en
,
io
.
meta_write
.
bits
.
data
.
coh
.
state
,
io
.
meta_write
.
bits
.
data
.
tag
,
io
.
meta_write
.
bits
.
tag
)
// print replay
XSDebug
(
io
.
replay
.
fire
(),
"cmd: %x addr: %x data: %x mask: %x meta: %x tag_match: %b old_coh: %d old_tag: %x way_en: %x\n"
,
io
.
replay
.
bits
.
cmd
,
io
.
replay
.
bits
.
addr
,
io
.
replay
.
bits
.
data
,
io
.
replay
.
bits
.
mask
,
io
.
replay
.
bits
.
meta
,
io
.
replay
.
bits
.
tag_match
,
io
.
replay
.
bits
.
old_meta
.
coh
.
state
,
io
.
replay
.
bits
.
old_meta
.
tag
,
io
.
replay
.
bits
.
way_en
)
// print wb_req
XSDebug
(
io
.
wb_req
.
fire
(),
"idx %x tag: %x source: %d param: %x way_en: %x voluntary: %b\n"
,
io
.
wb_req
.
bits
.
idx
,
io
.
wb_req
.
bits
.
tag
,
io
.
wb_req
.
bits
.
source
,
io
.
wb_req
.
bits
.
param
,
io
.
wb_req
.
bits
.
way_en
,
io
.
wb_req
.
bits
.
voluntary
)
// print tilelink messages
when
(
XSDebug
.
trigger
&&
io
.
mem_acquire
.
fire
())
{
io
.
mem_acquire
.
bits
.
dump
}
when
(
XSDebug
.
trigger
&&
io
.
mem_grant
.
fire
())
{
io
.
mem_grant
.
bits
.
dump
}
when
(
XSDebug
.
trigger
&&
io
.
mem_finish
.
fire
())
{
io
.
mem_finish
.
bits
.
dump
}
}
src/main/scala/xiangshan/utils/LogUtils.scala
浏览文件 @
0b829d90
...
...
@@ -55,6 +55,12 @@ sealed abstract class LogHelper(val logLevel: XSLogLevel) extends HasXSParameter
apply
(
prefix
,
cond
,
Printable
.
pack
(
fmt
,
data
:_
*
))
def
apply
(
prefix
:
Boolean
,
cond
:
Bool
,
pable
:
Printable
)(
implicit
name
:
String
)
:
Any
=
XSLog
(
logLevel
)(
prefix
,
cond
,
pable
)
// trigger log or not
// used when user what to fine-control their printf output
def
trigger
:
Bool
=
{
logLevel
.
id
.
U
>=
XSLog
.
xsLogLevel
&&
XSLog
.
displayLog
}
}
object
XSDebug
extends
LogHelper
(
XSLogLevel
.
DEBUG
)
...
...
src/test/scala/xiangshan/backend/exu/DCacheTest.scala
浏览文件 @
0b829d90
...
...
@@ -4,10 +4,12 @@ import org.scalatest._
import
scala.collection.mutable.
{
Map
,
Queue
}
import
chisel3._
import
chisel3.util.experimental.BoringUtils
import
chisel3.experimental.BundleLiterals._
import
chiseltest._
import
xiangshan.XSModule
import
xiangshan.utils.XSLogLevel
import
xiangshan.mem.
{
LSUDMemIO
,
MemoryOpConstants
}
import
xiangshan.mem.cache.DCache
import
bus.tilelink.NaiveTLToAXI4
...
...
@@ -19,12 +21,23 @@ class DCacheDut extends XSModule {
})
val
dcache
=
Module
(
new
DCache
)
val
mem
=
Module
(
new
AXI4RAM
(
memByte
=
128
*
1024
*
1024
,
useBlackBox
=
tru
e
))
val
mem
=
Module
(
new
AXI4RAM
(
memByte
=
128
*
1024
*
1024
,
useBlackBox
=
fals
e
))
val
tlToAXI
=
Module
(
new
NaiveTLToAXI4
(
l1BusParams
))
dcache
.
io
.
lsu
<>
io
.
in
dcache
.
io
.
bus
<>
tlToAXI
.
io
.
in
tlToAXI
.
io
.
out
<>
mem
.
in
// log control
val
log_begin
,
log_end
,
log_level
=
Wire
(
UInt
(
64.
W
))
log_begin
:=
0.
U
log_end
:=
0xfffffff
.
U
log_level
:=
XSLogLevel
.
DEBUG
.
id
.
U
BoringUtils
.
addSource
(
log_begin
,
"DISPLAY_LOG_START"
)
BoringUtils
.
addSource
(
log_end
,
"DISPLAY_LOG_END"
)
BoringUtils
.
addSource
(
log_level
,
"DISPLAY_LOG_LEVEL"
)
}
...
...
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录