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0a6d33c1
编写于
2月 23, 2021
作者:
Y
Yinan Xu
提交者:
GitHub
2月 23, 2021
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差异文件
Merge pull request #571 from RISCVERS/opt-commit-type
dispatch1: compute lsqNeedAlloc in rename for better timing
上级
70051210
049559e7
变更
5
显示空白变更内容
内联
并排
Showing
5 changed file
with
24 addition
and
9 deletion
+24
-9
src/main/scala/xiangshan/backend/CtrlBlock.scala
src/main/scala/xiangshan/backend/CtrlBlock.scala
+1
-0
src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
+2
-0
src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala
src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala
+7
-1
src/main/scala/xiangshan/backend/rename/Rename.scala
src/main/scala/xiangshan/backend/rename/Rename.scala
+8
-0
src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
+6
-8
未找到文件。
src/main/scala/xiangshan/backend/CtrlBlock.scala
浏览文件 @
0a6d33c1
...
...
@@ -292,6 +292,7 @@ class CtrlBlock extends XSModule with HasCircularQueuePtrHelper {
rename
.
io
.
roqCommits
<>
roq
.
io
.
commits
rename
.
io
.
out
<>
dispatch
.
io
.
fromRename
rename
.
io
.
renameBypass
<>
dispatch
.
io
.
renameBypass
rename
.
io
.
dispatchInfo
<>
dispatch
.
io
.
preDpInfo
dispatch
.
io
.
redirect
<>
backendRedirect
dispatch
.
io
.
flush
:=
flushReg
...
...
src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
浏览文件 @
0a6d33c1
...
...
@@ -28,6 +28,7 @@ class Dispatch extends XSModule {
// from rename
val
fromRename
=
Vec
(
RenameWidth
,
Flipped
(
DecoupledIO
(
new
MicroOp
)))
val
renameBypass
=
Input
(
new
RenameBypassInfo
)
val
preDpInfo
=
Input
(
new
PreDispatchInfo
)
// to busytable: set pdest to busy (not ready) when they are dispatched
val
allocPregs
=
Vec
(
RenameWidth
,
Output
(
new
ReplayPregReq
))
// enq Roq
...
...
@@ -66,6 +67,7 @@ class Dispatch extends XSModule {
// dispatch 1: accept uops from rename and dispatch them to the three dispatch queues
// dispatch1.io.redirect <> io.redirect
dispatch1
.
io
.
renameBypass
:=
RegEnable
(
io
.
renameBypass
,
io
.
fromRename
(
0
).
valid
&&
dispatch1
.
io
.
fromRename
(
0
).
ready
)
dispatch1
.
io
.
preDpInfo
:=
RegEnable
(
io
.
preDpInfo
,
io
.
fromRename
(
0
).
valid
&&
dispatch1
.
io
.
fromRename
(
0
).
ready
)
dispatch1
.
io
.
enqRoq
<>
io
.
enqRoq
dispatch1
.
io
.
enqLsq
<>
io
.
enqLsq
dispatch1
.
io
.
toIntDq
<>
intDq
.
io
.
enq
...
...
src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala
浏览文件 @
0a6d33c1
...
...
@@ -10,12 +10,18 @@ import xiangshan.backend.rename.RenameBypassInfo
import
xiangshan.mem.LsqEnqIO
import
xiangshan.backend.fu.HasExceptionNO
class
PreDispatchInfo
extends
XSBundle
{
val
lsqNeedAlloc
=
Vec
(
RenameWidth
,
UInt
(
2.
W
))
}
// read rob and enqueue
class
Dispatch1
extends
XSModule
with
HasExceptionNO
{
val
io
=
IO
(
new
Bundle
()
{
// from rename
val
fromRename
=
Vec
(
RenameWidth
,
Flipped
(
DecoupledIO
(
new
MicroOp
)))
val
renameBypass
=
Input
(
new
RenameBypassInfo
)
val
preDpInfo
=
Input
(
new
PreDispatchInfo
)
val
recv
=
Output
(
Vec
(
RenameWidth
,
Bool
()))
// enq Roq
val
enqRoq
=
Flipped
(
new
RoqEnqIO
)
...
...
@@ -147,7 +153,7 @@ class Dispatch1 extends XSModule with HasExceptionNO {
io
.
enqRoq
.
req
(
i
).
bits
:=
updatedUop
(
i
)
XSDebug
(
io
.
enqRoq
.
req
(
i
).
valid
,
p
"pc 0x${Hexadecimal(io.fromRename(i).bits.cf.pc)} receives nroq ${io.enqRoq.resp(i)}\n"
)
io
.
enqLsq
.
needAlloc
(
i
)
:=
io
.
fromRename
(
i
).
valid
&&
isLs
(
i
)
io
.
enqLsq
.
needAlloc
(
i
)
:=
Mux
(
io
.
fromRename
(
i
).
valid
,
io
.
preDpInfo
.
lsqNeedAlloc
(
i
),
0.
U
)
io
.
enqLsq
.
req
(
i
).
valid
:=
io
.
fromRename
(
i
).
valid
&&
isLs
(
i
)
&&
thisCanActualOut
(
i
)
&&
io
.
enqRoq
.
canAccept
&&
io
.
toIntDq
.
canAccept
&&
io
.
toFpDq
.
canAccept
&&
io
.
toLsDq
.
canAccept
io
.
enqLsq
.
req
(
i
).
bits
:=
updatedUop
(
i
)
io
.
enqLsq
.
req
(
i
).
bits
.
roqIdx
:=
io
.
enqRoq
.
resp
(
i
)
...
...
src/main/scala/xiangshan/backend/rename/Rename.scala
浏览文件 @
0a6d33c1
...
...
@@ -5,6 +5,7 @@ import chisel3.util._
import
xiangshan._
import
utils._
import
xiangshan.backend.roq.RoqPtr
import
xiangshan.backend.dispatch.PreDispatchInfo
class
RenameBypassInfo
extends
XSBundle
{
val
lsrc1_bypass
=
MixedVec
(
List
.
tabulate
(
RenameWidth
-
1
)(
i
=>
UInt
((
i
+
1
).
W
)))
...
...
@@ -23,6 +24,7 @@ class Rename extends XSModule with HasCircularQueuePtrHelper {
// to dispatch1
val
out
=
Vec
(
RenameWidth
,
DecoupledIO
(
new
MicroOp
))
val
renameBypass
=
Output
(
new
RenameBypassInfo
)
val
dispatchInfo
=
Output
(
new
PreDispatchInfo
)
})
def
printRenameInfo
(
in
:
DecoupledIO
[
CfCtrl
],
out
:
DecoupledIO
[
MicroOp
])
=
{
...
...
@@ -202,6 +204,12 @@ class Rename extends XSModule with HasCircularQueuePtrHelper {
}).
reverse
)
}
val
isLs
=
VecInit
(
uops
.
map
(
uop
=>
FuType
.
isLoadStore
(
uop
.
ctrl
.
fuType
)))
val
isStore
=
VecInit
(
uops
.
map
(
uop
=>
FuType
.
isStoreExu
(
uop
.
ctrl
.
fuType
)))
val
isAMO
=
VecInit
(
uops
.
map
(
uop
=>
FuType
.
isAMO
(
uop
.
ctrl
.
fuType
)))
io
.
dispatchInfo
.
lsqNeedAlloc
:=
VecInit
((
0
until
RenameWidth
).
map
(
i
=>
Mux
(
isLs
(
i
),
Mux
(
isStore
(
i
)
&&
!
isAMO
(
i
),
2.
U
,
1.
U
),
0.
U
)))
/**
* Instructions commit: update freelist and rename table
*/
...
...
src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
浏览文件 @
0a6d33c1
...
...
@@ -29,7 +29,7 @@ class InflightBlockInfo extends XSBundle {
class
LsqEnqIO
extends
XSBundle
{
val
canAccept
=
Output
(
Bool
())
val
needAlloc
=
Vec
(
RenameWidth
,
Input
(
Bool
(
)))
val
needAlloc
=
Vec
(
RenameWidth
,
Input
(
UInt
(
2.
W
)))
val
req
=
Vec
(
RenameWidth
,
Flipped
(
ValidIO
(
new
MicroOp
)))
val
resp
=
Vec
(
RenameWidth
,
Output
(
new
LSIdx
))
}
...
...
@@ -75,14 +75,12 @@ class LsqWrappper extends XSModule with HasDCacheParameters {
loadQueue
.
io
.
enq
.
sqCanAccept
:=
storeQueue
.
io
.
enq
.
canAccept
storeQueue
.
io
.
enq
.
lqCanAccept
:=
loadQueue
.
io
.
enq
.
canAccept
for
(
i
<-
0
until
RenameWidth
)
{
val
isStore
=
CommitType
.
lsInstIsStore
(
io
.
enq
.
req
(
i
).
bits
.
ctrl
.
commitType
)
loadQueue
.
io
.
enq
.
needAlloc
(
i
)
:=
io
.
enq
.
needAlloc
(
i
)
&&
!
isStore
loadQueue
.
io
.
enq
.
req
(
i
).
valid
:=
!
isStore
&&
io
.
enq
.
req
(
i
).
valid
loadQueue
.
io
.
enq
.
needAlloc
(
i
)
:=
io
.
enq
.
needAlloc
(
i
)(
0
)
loadQueue
.
io
.
enq
.
req
(
i
).
valid
:=
io
.
enq
.
needAlloc
(
i
)(
0
)
&&
io
.
enq
.
req
(
i
).
valid
loadQueue
.
io
.
enq
.
req
(
i
).
bits
:=
io
.
enq
.
req
(
i
).
bits
storeQueue
.
io
.
enq
.
needAlloc
(
i
)
:=
io
.
enq
.
needAlloc
(
i
)
&&
isStore
storeQueue
.
io
.
enq
.
req
(
i
).
valid
:=
isStore
&&
io
.
enq
.
req
(
i
).
valid
storeQueue
.
io
.
enq
.
needAlloc
(
i
)
:=
io
.
enq
.
needAlloc
(
i
)
(
1
)
storeQueue
.
io
.
enq
.
req
(
i
).
valid
:=
io
.
enq
.
needAlloc
(
i
)(
1
)
&&
io
.
enq
.
req
(
i
).
valid
storeQueue
.
io
.
enq
.
req
(
i
).
bits
:=
io
.
enq
.
req
(
i
).
bits
io
.
enq
.
resp
(
i
).
lqIdx
:=
loadQueue
.
io
.
enq
.
resp
(
i
)
...
...
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