• W
    ldu: set load to use latency to 4 (#1623) · c837faaa
    William Wang 提交于
    This commit adds an extra cycle for load pipeline. It should fix timing problem caused by load pipeline.
    Huge perf loss is expected. Now load data result is sent to rs in load_s3, load may hit hint
    (fastUop.valid) is sent to rs in load_s2.
    
    We add a 3 cycle load to load fast forward data path. There should be enough time to forward
    data inside memory block.
    
    We will refactor code and add a load_s3 module in the future.
    
    BREAKING CHANGE: load pipeline reorginized
    c837faaa
Parameters.scala 15.4 KB