* but byte/word register writes are infrequent in microbench

Rv64 opt

See merge request projectn/nemu!44

* this makes it more readable

* this makes it easier to perform constant propagation

* this helps to reduce data movement

Refactor rtl

See merge request projectn/nemu!43

* byte/word register accessing still need data movement

* this may write $0, so reset $0 when reading from $0, and do not check
  $0 during difftest
* also do not write dsrc1/dsrc2, and be careful about dsrc1/dsrc2 ==
  ddest

* jump instructions do not need to load the immediate to rtl registers,
  which saves rtl instructions

* this still works with RVC

* they can be easily mapped to riscv instructions

Refactor engine rv64

See merge request projectn/nemu!42

Engine rv64

See merge request projectn/nemu!41

* we can not access runtime value at the translation time
* fix by guarding the shift amount with mask in the interpreter

* some isa-dependent code should be refactored later

* the include/isa/riscv64.h file will be included with ISA64 undefined,
  we should explicitly use uint64_t instead of vaddr_t or rtlreg_t

* this engine will dynamically link with riscv64-nemu-interpreter-so,
  and control the rv64 interpreter by difftest API