riscv64,exec: use imm instructions for non-RVC

src/isa/riscv64/exec/compute.h

@@ -13,7 +13,6 @@ static inline make_EHelper(sub) {
 }
 
 static inline make_EHelper(sll) {
-  rtl_andi(s, dsrc2, dsrc2, 0x3f);
   rtl_shl(s, s0, dsrc1, dsrc2);
   rtl_sr(s, id_dest->reg, s0, 4);
 
@@ -21,10 +20,10 @@ static inline make_EHelper(sll) {
 }
 
 static inline make_EHelper(sra) {
-  rtl_andi(s, dsrc2, dsrc2, 0x3f);
   rtl_sar(s, s0, dsrc1, dsrc2);
-  print_asm_template3(sra);
   rtl_sr(s, id_dest->reg, s0, 4);
+
+  print_asm_template3(sra);
 }
 
 static inline make_EHelper(srl) {
@@ -34,7 +33,6 @@ static inline make_EHelper(srl) {
     exec_sra(s);
     return;
   }
-  rtl_andi(s, dsrc2, dsrc2, 0x3f);
   rtl_shr(s, s0, dsrc1, dsrc2);
   print_asm_template3(srl);
   rtl_sr(s, id_dest->reg, s0, 4);
@@ -75,16 +73,77 @@ static inline make_EHelper(and) {
   print_asm_template3(and);
 }
 
+static inline make_EHelper(addi) {
+  rtl_addi(s, s0, dsrc1, id_src2->imm);
+  rtl_sr(s, id_dest->reg, s0, 4);
+
+  print_asm_template3(addi);
+}
+
+static inline make_EHelper(slli) {
+  rtl_shli(s, s0, dsrc1, id_src2->imm);
+  rtl_sr(s, id_dest->reg, s0, 4);
+
+  print_asm_template3(slli);
+}
+
+static inline make_EHelper(srli) {
+  // the LSB of funct7 may be "1" due to the shift amount can be >= 32
+  // this rule is disabled when a compressed inst comes in
+  if ((s->isa.instr.r.funct7 & ~0x1) == 32 && s->isa.instr.r.opcode1_0 == 0x3) {
+    rtl_sari(s, s0, dsrc1, id_src2->imm);
+    print_asm_template3(srai);
+  } else {
+    rtl_shri(s, s0, dsrc1, id_src2->imm);
+    print_asm_template3(srli);
+  }
+  rtl_sr(s, id_dest->reg, s0, 4);
+}
+
+static inline make_EHelper(slti) {
+  rtl_setrelopi(s, RELOP_LT, s0, dsrc1, id_src2->imm);
+  rtl_sr(s, id_dest->reg, s0, 4);
+
+  print_asm_template3(slti);
+}
+
+static inline make_EHelper(sltui) {
+  rtl_setrelopi(s, RELOP_LTU, s0, dsrc1, id_src2->imm);
+  rtl_sr(s, id_dest->reg, s0, 4);
+
+  print_asm_template3(sltui);
+}
+
+static inline make_EHelper(xori) {
+  rtl_xori(s, s0, dsrc1, id_src2->imm);
+  rtl_sr(s, id_dest->reg, s0, 4);
+
+  print_asm_template3(xori);
+}
+
+static inline make_EHelper(ori) {
+  rtl_ori(s, s0, dsrc1, id_src2->imm);
+  rtl_sr(s, id_dest->reg, s0, 4);
+
+  print_asm_template3(ori);
+}
+
+static inline make_EHelper(andi) {
+  rtl_andi(s, s0, dsrc1, id_src2->imm);
+  rtl_sr(s, id_dest->reg, s0, 4);
+
+  print_asm_template3(andi);
+}
+
 static inline make_EHelper(auipc) {
-  rtl_shli(s, s0, dsrc2, 12);
-  rtl_add(s, s0, s0, &cpu.pc);
+  rtl_li(s, s0, id_src2->imm + cpu.pc);
   rtl_sr(s, id_dest->reg, s0, 4);
 
   print_asm("auipc " FMT_WORD ",%s", *s0, id_dest->str);
 }
 
 static inline make_EHelper(lui) {
-  rtl_shli(s, s0, dsrc2, 12);
+  rtl_li(s, s0, id_src2->imm);
   rtl_sr(s, id_dest->reg, s0, 4);
 
   print_asm("lui " FMT_WORD ",%s", *s0, id_dest->str);
@@ -139,3 +198,38 @@ static inline make_EHelper(srlw) {
 static inline make_EHelper(sraw) {
   exec_srlw(s);
 }
+
+static inline make_EHelper(addiw) {
+  rtl_addi(s, s0, dsrc1, id_src2->imm);
+  rtl_sext(s, s0, s0, 4);
+  rtl_sr(s, id_dest->reg, s0, 4);
+
+  print_asm_template3(addiw);
+}
+
+static inline make_EHelper(slliw) {
+  rtl_shli(s, s0, dsrc1, id_src2->imm & 0x1f);
+  rtl_sext(s, s0, s0, 4);
+  rtl_sr(s, id_dest->reg, s0, 4);
+
+  print_asm_template3(slliw);
+}
+
+static inline make_EHelper(srliw) {
+  assert((s->isa.instr.r.funct7 & 0x1) == 0);
+  if (s->isa.instr.r.funct7 == 32) {
+    // sraw
+    rtl_sext(s, dsrc1, dsrc1, 4);
+    rtl_sari(s, s0, dsrc1, id_src2->imm & 0x1f);
+    print_asm_template3(sraiw);
+  }
+  else {
+    // srlw
+    rtl_andi(s, dsrc1, dsrc1, 0xffffffffu);
+    rtl_shri(s, s0, dsrc1, id_src2->imm & 0x1f);
+    print_asm_template3(srliw);
+  }
+
+  rtl_sext(s, s0, s0, 4);
+  rtl_sr(s, id_dest->reg, s0, 4);
+}

src/isa/riscv64/exec/control.h

@@ -12,7 +12,7 @@ static inline make_EHelper(jalr) {
   rtl_li(s, s0, s->seq_pc);
   rtl_sr(s, id_dest->reg, s0, 4);
 
-  rtl_add(s, s0, dsrc1, dsrc2);
+  rtl_addi(s, s0, dsrc1, id_src2->imm);
   rtl_andi(s, s0, s0, ~0x1lu);
   rtl_jr(s, s0);
 

src/isa/riscv64/exec/exec.c

@@ -33,14 +33,14 @@ static inline make_EHelper(store) {
 
 static inline make_EHelper(op_imm) {
   switch (s->isa.instr.i.funct3) {
-    EX(0, add)  EX(1, sll)  EX(2, slt) EX(3, sltu)
-    EX(4, xor)  EX(5, srl)  EX(6, or)  EX(7, and)
+    EX(0, addi)  EX(1, slli)  EX(2, slti) EX(3, sltui)
+    EX(4, xori)  EX(5, srli)  EX(6, ori)  EX(7, andi)
   }
 }
 
 static inline make_EHelper(op_imm32) {
   switch (s->isa.instr.i.funct3) {
-    EX(0, addw) EX(1, sllw) EX(5, srlw)
+    EX(0, addiw) EX(1, slliw) EX(5, srliw)
     default: exec_inv(s);
   }
 }
@@ -182,9 +182,9 @@ static inline void exec(DecodeExecState *s) {
 
   if (s->isa.instr.r.opcode1_0 == 0x3) {
     switch (s->isa.instr.r.opcode6_2) {
-      IDEX (000, ld, load)  EX   (001, fp)                                  EX   (003, fence)
+      IDEX (000, I, load)   EX   (001, fp)                                  EX   (003, fence)
       IDEX (004, I, op_imm) IDEX (005, U, auipc)  IDEX (006, I, op_imm32)
-      IDEX (010, st, store) EX   (011, fp)                                  IDEX (013, R, atomic)
+      IDEX (010, S, store)  EX   (011, fp)                                  IDEX (013, R, atomic)
       IDEX (014, R, op)     IDEX (015, U, lui)    IDEX (016, R, op32)
       EX   (020, fp)
       EX   (024, fp)

src/isa/riscv64/exec/ldst.h

 #include "../local-include/intr.h"
 
 static inline make_EHelper(ld) {
-  rtl_lm(s, s0, &id_src1->addr, 0, s->width);
+  rtl_lm(s, s0, dsrc1, id_src2->imm, s->width);
   check_mem_ex();
   rtl_sr(s, id_dest->reg, s0, 0);
 
+  print_Dop(id_src1->str, OP_STR_SIZE, "%d(%s)", id_src2->val, reg_name(id_src1->reg, 4));
   switch (s->width) {
     case 8: print_asm_template2(ld); break;
     case 4: print_asm_template2(lwu); break;
@@ -16,11 +17,12 @@ static inline make_EHelper(ld) {
 
 // load sign value
 static inline make_EHelper(lds) {
-  rtl_lm(s, s0, &id_src1->addr, 0, s->width);
+  rtl_lm(s, s0, dsrc1, id_src2->imm, s->width);
   check_mem_ex();
   rtl_sext(s, s0, s0, s->width);
   rtl_sr(s, id_dest->reg, s0, 0);
 
+  print_Dop(id_src1->str, OP_STR_SIZE, "%d(%s)", id_src2->val, reg_name(id_src1->reg, 4));
   switch (s->width) {
     case 4: print_asm_template2(lw); break;
     case 2: print_asm_template2(lh); break;
@@ -30,9 +32,10 @@ static inline make_EHelper(lds) {
 }
 
 static inline make_EHelper(st) {
-  rtl_sm(s, &id_src1->addr, 0, ddest, s->width);
+  rtl_sm(s, dsrc1, id_src2->imm, ddest, s->width);
   check_mem_ex();
 
+  print_Dop(id_src1->str, OP_STR_SIZE, "%d(%s)", id_src2->val, reg_name(id_src1->reg, 4));
   switch (s->width) {
     case 8: print_asm_template2(sd); break;
     case 4: print_asm_template2(sw); break;

src/isa/riscv64/exec/system.h

@@ -14,7 +14,7 @@ static inline bool csr_check(DecodeExecState *s, uint32_t addr) {
 }
 
 static inline make_EHelper(csrrw) {
-  uint32_t addr = *dsrc2;
+  uint32_t addr = id_src2->imm;
   if (!csr_check(s, addr)) return;
   csr_read(s0, addr);
   rtl_sr(s, id_dest->reg, s0, 8);
@@ -24,7 +24,7 @@ static inline make_EHelper(csrrw) {
 }
 
 static inline make_EHelper(csrrs) {
-  uint32_t addr = *dsrc2;
+  uint32_t addr = id_src2->imm;
   if (!csr_check(s, addr)) return;
   csr_read(s0, addr);
   rtl_sr(s, id_dest->reg, s0, 8);
@@ -37,7 +37,7 @@ static inline make_EHelper(csrrs) {
 }
 
 static inline make_EHelper(csrrc) {
-  uint32_t addr = id_src2->val;
+  uint32_t addr = id_src2->imm;
   if (!csr_check(s, addr)) return;
   csr_read(s0, addr);
   rtl_sr(s, id_dest->reg, s0, 8);

src/isa/riscv64/local-include/decode.h

@@ -8,7 +8,6 @@
 static inline make_DopHelper(i) {
   op->type = OP_TYPE_IMM;
   op->imm = val;
-  rtl_li(s, &op->val, op->imm);
 
   print_Dop(op->str, OP_STR_SIZE, "%ld", op->imm);
 }
@@ -36,8 +35,7 @@ static inline make_DHelper(R) {
 }
 
 static inline make_DHelper(U) {
-  // shift at execute stage
-  decode_op_i(s, id_src2, (sword_t)s->isa.instr.u.simm31_12, true);
+  decode_op_i(s, id_src2, (sword_t)s->isa.instr.u.simm31_12 << 12, true);
   decode_op_r(s, id_dest, s->isa.instr.u.rd, false);
 
   print_Dop(id_src2->str, OP_STR_SIZE, "0x%x", s->isa.instr.u.simm31_12);
@@ -47,7 +45,6 @@ static inline make_DHelper(J) {
   sword_t offset = (s->isa.instr.j.simm20 << 20) | (s->isa.instr.j.imm19_12 << 12) |
     (s->isa.instr.j.imm11 << 11) | (s->isa.instr.j.imm10_1 << 1);
   s->jmp_pc = cpu.pc + offset;
-  decode_op_i(s, id_src1, s->jmp_pc, true);
   print_Dop(id_src1->str, OP_STR_SIZE, "0x%lx", s->jmp_pc);
 
   decode_op_r(s, id_dest, s->isa.instr.j.rd, false);
@@ -57,33 +54,16 @@ static inline make_DHelper(B) {
   sword_t offset = (s->isa.instr.b.simm12 << 12) | (s->isa.instr.b.imm11 << 11) |
     (s->isa.instr.b.imm10_5 << 5) | (s->isa.instr.b.imm4_1 << 1);
   s->jmp_pc = cpu.pc + offset;
-  decode_op_i(s, id_dest, s->jmp_pc, true);
-  print_Dop(id_dest->str, OP_STR_SIZE, "0x%lx", s->jmp_pc);
+  print_Dop(id_dest->str, OP_STR_SIZE, "0x%x", s->jmp_pc);
 
   decode_op_r(s, id_src1, s->isa.instr.b.rs1, true);
   decode_op_r(s, id_src2, s->isa.instr.b.rs2, true);
 }
 
-static inline make_DHelper(ld) {
-  decode_op_r(s, id_src1, s->isa.instr.i.rs1, true);
-  decode_op_i(s, id_src2, s->isa.instr.i.simm11_0, true);
-
-  print_Dop(id_src1->str, OP_STR_SIZE, "%ld(%s)", id_src2->val, reg_name(id_src1->reg, 4));
-
-  rtl_add(s, &id_src1->addr, dsrc1, dsrc2);
-
-  decode_op_r(s, id_dest, s->isa.instr.i.rd, false);
-}
-
-static inline make_DHelper(st) {
+static inline make_DHelper(S) {
   decode_op_r(s, id_src1, s->isa.instr.s.rs1, true);
   sword_t simm = (s->isa.instr.s.simm11_5 << 5) | s->isa.instr.s.imm4_0;
   decode_op_i(s, id_src2, simm, true);
-
-  print_Dop(id_src1->str, OP_STR_SIZE, "%ld(%s)", id_src2->val, reg_name(id_src1->reg, 4));
-
-  rtl_add(s, &id_src1->addr, dsrc1, dsrc2);
-
   decode_op_r(s, id_dest, s->isa.instr.s.rs2, true);
 }