riscv64,csr: trigger illegal instruction with rdtime

src/isa/riscv64/intr.c

 #include "rtl/rtl.h"
 #include "csr.h"
 #include <setjmp.h>
+#include "intr.h"
 
 #define INTR_BIT (1ULL << 63)
 enum {
@@ -23,6 +24,7 @@ void raise_intr(word_t NO, vaddr_t epc) {
     mstatus->sie = 0;
     cpu.mode = MODE_S;
     rtl_li(&s0, stvec->val);
+    if (NO == EX_II) stval->val = 0;
   } else {
     mcause->val = NO;
     mepc->val = epc;
@@ -31,6 +33,7 @@ void raise_intr(word_t NO, vaddr_t epc) {
     mstatus->mie = 0;
     cpu.mode = MODE_M;
     rtl_li(&s0, mtvec->val);
+    if (NO == EX_II) mtval->val = 0;
   }
 
   rtl_jr(&s0);

src/isa/riscv64/reg.c

 #include "nemu.h"
 #include "monitor/diff-test.h"
 #include "csr.h"
+#include "intr.h"
 
 const char *regsl[] = {
   "$0", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
@@ -50,6 +51,10 @@ static bool csr_exist[4096] = {
 
 static inline word_t* csr_decode(uint32_t addr) {
   assert(addr < 4096);
+  if (addr == 0xc01) {
+    // time
+    longjmp_raise_intr(EX_II);
+  }
   Assert(csr_exist[addr], "unimplemented CSR 0x%x at pc = " FMT_WORD, addr, cpu.pc);
   return &csr_array[addr];
 }