riscv64,exec: add lr/sc

src/isa/riscv64/exec/all-instr.h

@@ -52,6 +52,8 @@ make_EHelper(remuw);
 make_EHelper(sraw);
 make_EHelper(srlw);
 
+make_EHelper(lr);
+make_EHelper(sc);
 make_EHelper(amoswap);
 make_EHelper(amoadd);
 make_EHelper(amoor);

src/isa/riscv64/exec/amo.c

 #include "cpu/exec.h"
 
+make_EHelper(lr) {
+  rtl_lm(&s0, &id_src->val, decinfo.width);
+  rtl_sext(&s0, &s0, decinfo.width);
+  rtl_sr(id_dest->reg, &s0, 0);
+
+  cpu.lr = true;
+  cpu.lr_addr = id_src->val;
+
+  print_asm_template3(lr);
+}
+
+make_EHelper(sc) {
+  // should check overlapping instead of equality
+  if (cpu.lr && cpu.lr_addr == id_src->val) {
+    rtl_sm(&id_src->val, &id_src2->val, decinfo.width);
+    rtl_li(&s0, 0);
+  } else {
+    rtl_li(&s0, 1);
+  }
+  rtl_sr(id_dest->reg, &s0, 0);
+  cpu.lr = false;
+
+  print_asm_template3(sc);
+}
+
 make_EHelper(amoswap) {
   rtl_lm(&s0, &id_src->val, decinfo.width);
   rtl_sext(&s0, &s0, decinfo.width);

src/isa/riscv64/exec/exec.c

@@ -67,7 +67,7 @@ static make_EHelper(system) {
 
 static make_EHelper(atomic) {
   static OpcodeEntry table_lo [4] = {
-    EMPTY, EX(amoswap), EMPTY, EMPTY
+    EMPTY, EX(amoswap), EX(lr), EX(sc)
   };
   static OpcodeEntry table_hi [8] = {
     EX(amoadd), EMPTY, EX(amoor), EMPTY, EMPTY, EMPTY, EMPTY, EMPTY

src/isa/riscv64/exec/system.c

@@ -51,6 +51,7 @@ make_EHelper(priv) {
       mstatus->mpp = MODE_U;
       rtl_li(&s0, sepc->val);
       rtl_jr(&s0);
+      cpu.lr = false;
       print_asm("sret");
       break;
     case 0x120:
@@ -63,6 +64,7 @@ make_EHelper(priv) {
       mstatus->mpp = MODE_U;
       rtl_li(&s0, mepc->val);
       rtl_jr(&s0);
+      cpu.lr = false;
       print_asm("mret");
       break;
     default: panic("unimplemented priv instruction type = 0x%x", type);

src/isa/riscv64/include/isa/reg.h

@@ -19,6 +19,10 @@ typedef struct {
 
   bool fetching;
 
+  // for LR/SC
+  bool lr;
+  vaddr_t lr_addr;
+
   bool INTR;
 } CPU_state;