update mini2440 bsp.

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@206 bbd45198-f89e-11dd-88c7-29a3b14d5316

bsp/mini2440/SConstruct

@@ -4,7 +4,7 @@ import rtconfig
 RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
 target = 'rtthread-s3c2440'
 
-# search path for C compiler 
+# search path for C compiler
 bsp_path  = RTT_ROOT + '/bsp/mini2440'
 
 env = Environment(tools = ['mingw'],
@@ -36,7 +36,7 @@ if rtconfig.RT_USING_LWIP:
 	objs = objs + SConscript(RTT_ROOT + '/net/lwip/SConscript', variant_dir='build/net/lwip', duplicate=0)
 
 src_bsp = ['application.c', 'startup.c', 'board.c']
-src_drv = ['rtc.c', 'console.c']
+src_drv = ['console.c']
 
 if rtconfig.RT_USING_DFS:
 	src_drv += ['sdcard.c']

bsp/mini2440/application.c

@@ -14,179 +14,97 @@
  */
 
 /**
- * @addtogroup s3ceb2410
- */ 
-
+ * @addtogroup mini2440
+ */
 /*@{*/
-#include <rtthread.h>
 
-#ifdef RT_USING_RTGUI
-#include <rtgui/rtgui.h>
-#endif
+#include <board.h>
+#include <rtthread.h>
 
 #ifdef RT_USING_DFS
 /* dfs init */
 #include <dfs_init.h>
-/* dfs filesystem:FAT filesystem init */
-#include <dfs_fat.h>
 /* dfs filesystem:EFS filesystem init */
-#include <dfs_efs.h> 
+#include <dfs_efs.h>
 /* dfs Filesystem APIs */
 #include <dfs_fs.h>
-
-void dfs_init_entry(void* parameter)
-{	
-	/* init the device filesystem */
-	dfs_init();
-	/* init the fat filesystem */
-	fatfs_init();
-	/* init the efsl filesystam*/
-	efsl_init();
-
-	/* mount sd card fat partition 1 as root directory */
-	dfs_mount("sd1", "/", "efs", 0, 0);
-	/* mount sd card fat partition 0 */
-	//dfs_mount("sd0", "/DEV", "efs", 0, 0);
-
-	rt_kprintf("File System initialized!\n");
-}
 #endif
 
 #ifdef RT_USING_LWIP
-#include "lwip/sys.h"
-#include "lwip/api.h"
-
-#ifdef RT_USING_WEBSERVER
-extern void thread_webserver(void *parameter);
+#include <netif/ethernetif.h>
 #endif
 
-#ifdef RT_USING_FTPSERVER
-extern void thread_ftpserver(void *parameter);
-#endif
-
-void thread_tcpecho(void *parameter)
+void rt_init_thread_entry(void* parameter)
 {
-	struct netconn *conn, *newconn;
-	err_t err;
-
-	/* Create a new connection identifier. */
-	conn = netconn_new(NETCONN_TCP);
-
-	/* Bind connection to well known port number 7. */
-	netconn_bind(conn, NULL, 7);
+/* Filesystem Initialization */
+#ifdef RT_USING_DFS
+	{
+		/* init the device filesystem */
+		dfs_init();
 
-	/* Tell connection to go into listening mode. */
-	netconn_listen(conn);
+#ifdef RT_USING_DFS_EFSL
+		/* init the efsl filesystam*/
+		efsl_init();
 
-	while(1)
-	{
-		/* Grab new connection. */
-		newconn = netconn_accept(conn);
-		/* Process the new connection. */
-		if(newconn != NULL)
+		/* mount sd card fat partition 1 as root directory */
+		if (dfs_mount("sd0", "/", "efs", 0, 0) == 0)
 		{
-			struct netbuf *buf;
-			void *data;
-			u16_t len;
-
-			while((buf = netconn_recv(newconn)) != NULL)
-			{
-				do
-				{
-					netbuf_data(buf, &data, &len);
-					err = netconn_write(newconn, data, len, NETCONN_COPY);
-					if(err != ERR_OK){}
-				}
-				while(netbuf_next(buf) >= 0);
-				netbuf_delete(buf);
-			}
-			/* Close connection and discard connection identifier. */
-			netconn_delete(newconn);
+			rt_kprintf("File System initialized!\n");
 		}
-	}
-}
-
-void lwip_init_entry(void* parameter)
-{
-	/* init lwip system */
-	lwip_sys_init();
-	rt_kprintf("TCP/IP initialized!\n");
-}
+		else
+			rt_kprintf("File System initialzation failed!\n");
+#elif defined(RT_USING_DFS_ELMFAT)
+		/* init the elm chan FatFs filesystam*/
+		elm_init();
+
+		/* mount sd card fat partition 1 as root directory */
+		if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
+		{
+			rt_kprintf("File System initialized!\n");
+		}
+		else
+			rt_kprintf("File System initialzation failed!\n");
 #endif
-
-/* application start function */
-void rt_application_init()
-{
-#ifdef RT_USING_DFS
-	rt_thread_t dfs_init;
-
-	dfs_init = rt_thread_create("tdfs",
-								dfs_init_entry, RT_NULL,
-								2048, 150, 20);
-	rt_thread_startup(dfs_init);
+	}
 #endif
 
+/* LwIP Initialization */
 #ifdef RT_USING_LWIP
-	rt_thread_t lwip_init;
-	rt_thread_t echo;
-
-	lwip_init = rt_thread_create("tlwip",
-								 lwip_init_entry, RT_NULL,
-								 1024, 100,20);
-	rt_thread_startup(lwip_init);
-
-	echo = rt_thread_create("echo",
-							thread_tcpecho, RT_NULL,
-							1024, 200,20);
-	rt_thread_startup(echo);
-	
-#ifdef RT_USING_WEBSERVER
-	rt_thread_t webserver;
-
-	webserver = rt_thread_create("twebserv",
-							thread_webserver, RT_NULL,
-							4096, 140, 20); 
-	rt_thread_startup(webserver);
-#endif
+	{
+		extern void lwip_sys_init(void);
+		eth_system_device_init();
 
-#ifdef RT_USING_FTPSERVER
-	rt_thread_t ftpserver;
+		/* register ethernetif device */
+		rt_hw_dm9000_init();
 
-	ftpserver = rt_thread_create("tftpserv",
-							thread_ftpserver, RT_NULL, 
-							1024, 200, 20);
-	rt_thread_startup(ftpserver);
-#endif
+		/* re-init device driver */
+		rt_device_init_all();
 
+		/* init lwip system */
+		lwip_sys_init();
+		rt_kprintf("TCP/IP initialized!\n");
+	}
 #endif
+}
 
-#ifdef RT_USING_RTGUI
-	{
-		rtgui_rect_t rect;
-
-		/* init rtgui system */
-		rtgui_system_server_init();
-
-		/* init graphic driver */
-		rt_hw_lcd_init();
-
-		/* register dock panel */
-		rect.x1 = 0;
-		rect.y1 = 0;
-		rect.x2 = 240;
-		rect.y2 = 25;
-		rtgui_panel_register("dock", &rect);
+int rt_application_init()
+{
+	rt_thread_t init_thread;
+
+#if (RT_THREAD_PRIORITY_MAX == 32)
+	init_thread = rt_thread_create("init",
+								rt_init_thread_entry, RT_NULL,
+								2048, 8, 20);
+#else
+	init_thread = rt_thread_create("init",
+								rt_init_thread_entry, RT_NULL,
+								2048, 80, 20);
+#endif
 
-		/* register main panel */
-		rect.x1 = 0;
-		rect.y1 = 25;
-		rect.x2 = 240;
-		rect.y2 = 320;
-		rtgui_panel_register("main", &rect);
+	if (init_thread != RT_NULL)
+		rt_thread_startup(init_thread);
 
-		rtgui_system_app_init();
-	}
-#endif
+	return 0;
 }
- 
-/*@}*/ 
+
+/*@}*/

bsp/mini2440/board.c

@@ -21,7 +21,7 @@
 #include "board.h"
 
 /**
- * @addtogroup s3ceb2410
+ * @addtogroup mini2440
  */
 /*@{*/
 
@@ -42,9 +42,9 @@ extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv);
 
 static rt_uint32_t timer_load_val = 0;
 
-#define UART0	((struct uartport *)U0BASE)	
+#define UART0	((struct uartport *)U0BASE)
 struct serial_int_rx uart0_int_rx;
-struct serial_device uart0 = 
+struct serial_device uart0 =
 {
 	UART0,
 	&uart0_int_rx,
@@ -84,17 +84,17 @@ void rt_serial_handler(int vector)
 void rt_hw_uart_init(void)
 {
 	int i;
-	
+
 	GPHCON |= 0xa0;
 	/*PULLUP is enable */
-	GPHUP  |= 0x0c;  
-	
+	GPHUP  |= 0x0c;
+
 	/* FIFO enable, Tx/Rx FIFO clear */
 	uart0.uart_device->ufcon = 0x1;
 	/* disable the flow control */
-	uart0.uart_device->umcon = 0x0;	
+	uart0.uart_device->umcon = 0x0;
 	/* Normal,No parity,1 stop,8 bit */
-	uart0.uart_device->ulcon = 0x3;	
+	uart0.uart_device->ulcon = 0x3;
 	/*
 	 * tx=level,rx=edge,disable timeout int.,enable rx error int.,
 	 * normal,interrupt or polling
@@ -104,13 +104,13 @@ void rt_hw_uart_init(void)
 	/* output PCLK to UART0/1, PWMTIMER */
 	CLKCON |= 0x0D00;
 
-	for (i = 0; i < 100; i++);	
+	for (i = 0; i < 100; i++);
 
 	/* install uart isr */
 	INTSUBMSK &= ~(BIT_SUB_RXD0);
 
 	rt_hw_interrupt_install(INTUART0, rt_serial_handler, RT_NULL);
-	rt_hw_interrupt_umask(INTUART0);		
+	rt_hw_interrupt_umask(INTUART0);
 }
 
 /**
@@ -160,9 +160,6 @@ void rt_hw_board_init()
 	/* initialize mmu */
 	rt_hw_mmu_init();
 
-	/* initialize keypad */
-	rt_kbd_init();
-
 	/* initialize console */
 	//rt_console_init(&_rt_hw_framebuffer[0], &asc16_font[0], 2);
 

bsp/mini2440/board.h

@@ -15,11 +15,10 @@
 #ifndef __BOARD_H__
 #define __BOARD_H__
 
-#include <s3c2410.h>
+#include <s3c24x0.h>
 #include <serial.h>
 
 void rt_hw_board_init(void);
-
 void rt_hw_sdcard_init(void);
 
 #endif

bsp/mini2440/console.c

@@ -25,7 +25,7 @@ struct rt_console
 	/* bpp and pixel of width */
 	rt_uint8_t bpp;
 	rt_uint32_t pitch;
-	
+
 	/* current cursor */
 	rt_uint8_t current_col;
 	rt_uint8_t current_row;
@@ -33,9 +33,9 @@ struct rt_console
 struct rt_console console;
 
 void rt_hw_console_init(rt_uint8_t* video_ptr, rt_uint8_t* font_ptr, rt_uint8_t bpp);
-void rt_hw_console_newline();
+void rt_hw_console_newline(void);
 void rt_hw_console_putc(char c);
-void rt_hw_console_clear();
+void rt_hw_console_clear(void);
 
 void rt_hw_console_init(rt_uint8_t* video_ptr, rt_uint8_t* font_ptr, rt_uint8_t bpp)
 {
@@ -45,7 +45,7 @@ void rt_hw_console_init(rt_uint8_t* video_ptr, rt_uint8_t* font_ptr, rt_uint8_t
 	console.font_ptr = font_ptr;
 	console.bpp = bpp;
 	console.pitch = console.bpp * RT_CONSOLE_WIDTH;
-	
+
 	rt_hw_console_clear();
 }
 
@@ -68,19 +68,23 @@ void rt_hw_console_putc(char c)
 
         default:
 			{
+				rt_uint8_t* font_ptr;
+				register rt_uint32_t cursor;
+				register rt_uint32_t i, j;
+
 				if (console.current_col == RT_CONSOLE_COL)
 				{
 					rt_hw_console_newline();
 					console.current_col = 0;
-					
+
 					rt_hw_console_putc(c);
 					return;
 				}
 
-				rt_uint8_t* font_ptr = console.font_ptr + c * RT_CONSOLE_FONT_HEIGHT;
-				register rt_uint32_t cursor = (console.current_row * RT_CONSOLE_FONT_HEIGHT) * console.pitch
+				font_ptr = console.font_ptr + c * RT_CONSOLE_FONT_HEIGHT;
+				cursor = (console.current_row * RT_CONSOLE_FONT_HEIGHT) * console.pitch
 					+ console.current_col * RT_CONSOLE_FONT_WIDTH * console.bpp;
-				register rt_uint32_t i, j;
+
 				for (i = 0; i < RT_CONSOLE_FONT_HEIGHT; i ++ )
 				{
 					for (j = 0; j < RT_CONSOLE_FONT_WIDTH; j ++)
@@ -109,7 +113,7 @@ void rt_hw_console_putc(char c)
 						}
 					}
 				}
-				
+
 				console.current_col ++;
 			}
 			break;
@@ -135,7 +139,7 @@ void rt_hw_console_newline()
 		rt_memset(console.video_ptr + (RT_CONSOLE_ROW - 1) * RT_CONSOLE_FONT_HEIGHT * console.pitch,
 			0,
 			RT_CONSOLE_FONT_HEIGHT * console.pitch);
-		
+
 		console.current_row = RT_CONSOLE_ROW - 1;
 	}
 }
@@ -144,7 +148,7 @@ void rt_hw_console_clear()
 {
 	console.current_col = 0;
 	console.current_row = 0;
-	
+
 	rt_memset(console.video_ptr, 0, RT_CONSOLE_HEIGHT * console.pitch);
 }
 
@@ -167,11 +171,10 @@ void rt_hw_serial_putc(const char c)
  * @param str the displayed string
  */
 void rt_hw_console_output(const char* str)
-{		
+{
 	while (*str)
 	{
-		rt_hw_serial_putc(*str++);		
-		//rt_hw_console_putc(*str++);		
+		rt_hw_serial_putc(*str++);
 	}
 }
 

bsp/mini2440/dm9000.c

+#include <rtthread.h>
+#include <netif/ethernetif.h>
+
+#include "dm9000a.h"
+
+// #define DM9000_DEBUG		1
+#if DM9000_DEBUG
+#define DM9000_TRACE	rt_kprintf
+#else
+#define DM9000_TRACE(...)
+#endif
+
+/*
+ * DM9000 interrupt line is connected to PF7
+ */
+//--------------------------------------------------------
+
+#define DM9000_PHY          0x40    /* PHY address 0x01 */
+#define RST_1()             GPIO_SetBits(GPIOF,GPIO_Pin_6)
+#define RST_0()             GPIO_ResetBits(GPIOF,GPIO_Pin_6)
+
+#define MAX_ADDR_LEN 6
+enum DM9000_PHY_mode
+{
+    DM9000_10MHD = 0, DM9000_100MHD = 1,
+    DM9000_10MFD = 4, DM9000_100MFD = 5,
+    DM9000_AUTO  = 8, DM9000_1M_HPNA = 0x10
+};
+
+enum DM9000_TYPE
+{
+    TYPE_DM9000E,
+    TYPE_DM9000A,
+    TYPE_DM9000B
+};
+
+struct rt_dm9000_eth
+{
+    /* inherit from ethernet device */
+    struct eth_device parent;
+
+    enum DM9000_TYPE type;
+	enum DM9000_PHY_mode mode;
+
+    rt_uint8_t imr_all;
+
+    rt_uint8_t packet_cnt;                  /* packet I or II */
+    rt_uint16_t queue_packet_len;           /* queued packet (packet II) */
+
+    /* interface address info. */
+    rt_uint8_t  dev_addr[MAX_ADDR_LEN];		/* hw address	*/
+};
+static struct rt_dm9000_eth dm9000_device;
+static struct rt_semaphore sem_ack, sem_lock;
+
+void rt_dm9000_isr(void);
+
+static void delay_ms(rt_uint32_t ms)
+{
+    rt_uint32_t len;
+    for (;ms > 0; ms --)
+        for (len = 0; len < 100; len++ );
+}
+
+/* Read a byte from I/O port */
+rt_inline rt_uint8_t dm9000_io_read(rt_uint16_t reg)
+{
+    DM9000_IO = reg;
+    return (rt_uint8_t) DM9000_DATA;
+}
+
+/* Write a byte to I/O port */
+rt_inline void dm9000_io_write(rt_uint16_t reg, rt_uint16_t value)
+{
+    DM9000_IO = reg;
+    DM9000_DATA = value;
+}
+
+/* Read a word from phyxcer */
+rt_inline rt_uint16_t phy_read(rt_uint16_t reg)
+{
+    rt_uint16_t val;
+
+    /* Fill the phyxcer register into REG_0C */
+    dm9000_io_write(DM9000_EPAR, DM9000_PHY | reg);
+    dm9000_io_write(DM9000_EPCR, 0xc);	/* Issue phyxcer read command */
+
+    delay_ms(100);		/* Wait read complete */
+
+    dm9000_io_write(DM9000_EPCR, 0x0);	/* Clear phyxcer read command */
+    val = (dm9000_io_read(DM9000_EPDRH) << 8) | dm9000_io_read(DM9000_EPDRL);
+
+    return val;
+}
+
+/* Write a word to phyxcer */
+rt_inline void phy_write(rt_uint16_t reg, rt_uint16_t value)
+{
+    /* Fill the phyxcer register into REG_0C */
+    dm9000_io_write(DM9000_EPAR, DM9000_PHY | reg);
+
+    /* Fill the written data into REG_0D & REG_0E */
+    dm9000_io_write(DM9000_EPDRL, (value & 0xff));
+    dm9000_io_write(DM9000_EPDRH, ((value >> 8) & 0xff));
+    dm9000_io_write(DM9000_EPCR, 0xa);	/* Issue phyxcer write command */
+
+    delay_ms(500);		/* Wait write complete */
+
+    dm9000_io_write(DM9000_EPCR, 0x0);	/* Clear phyxcer write command */
+}
+
+/* Set PHY operationg mode */
+rt_inline void phy_mode_set(rt_uint32_t media_mode)
+{
+    rt_uint16_t phy_reg4 = 0x01e1, phy_reg0 = 0x1000;
+    if (!(media_mode & DM9000_AUTO))
+    {
+        switch (media_mode)
+        {
+        case DM9000_10MHD:
+            phy_reg4 = 0x21;
+            phy_reg0 = 0x0000;
+            break;
+        case DM9000_10MFD:
+            phy_reg4 = 0x41;
+            phy_reg0 = 0x1100;
+            break;
+        case DM9000_100MHD:
+            phy_reg4 = 0x81;
+            phy_reg0 = 0x2000;
+            break;
+        case DM9000_100MFD:
+            phy_reg4 = 0x101;
+            phy_reg0 = 0x3100;
+            break;
+        }
+        phy_write(4, phy_reg4);	/* Set PHY media mode */
+        phy_write(0, phy_reg0);	/*  Tmp */
+    }
+
+    dm9000_io_write(DM9000_GPCR, 0x01);	/* Let GPIO0 output */
+    dm9000_io_write(DM9000_GPR, 0x00);	/* Enable PHY */
+}
+
+/* interrupt service routine */
+void rt_dm9000_isr()
+{
+    rt_uint16_t int_status;
+    rt_uint16_t last_io;
+
+    last_io = DM9000_IO;
+
+    /* Disable all interrupts */
+    dm9000_io_write(DM9000_IMR, IMR_PAR);
+
+    /* Got DM9000 interrupt status */
+    int_status = dm9000_io_read(DM9000_ISR);               /* Got ISR */
+    dm9000_io_write(DM9000_ISR, int_status);    /* Clear ISR status */
+
+	DM9000_TRACE("dm9000 isr: int status %04x\n", int_status);
+
+    /* receive overflow */
+    if (int_status & ISR_ROS)
+    {
+        rt_kprintf("overflow\n");
+    }
+
+    if (int_status & ISR_ROOS)
+    {
+        rt_kprintf("overflow counter overflow\n");
+    }
+
+    /* Received the coming packet */
+    if (int_status & ISR_PRS)
+    {
+	    /* disable receive interrupt */
+	    dm9000_device.imr_all = IMR_PAR | IMR_PTM;
+
+        /* a frame has been received */
+        eth_device_ready(&(dm9000_device.parent));
+    }
+
+    /* Transmit Interrupt check */
+    if (int_status & ISR_PTS)
+    {
+        /* transmit done */
+        int tx_status = dm9000_io_read(DM9000_NSR);    /* Got TX status */
+
+        if (tx_status & (NSR_TX2END | NSR_TX1END))
+        {
+            dm9000_device.packet_cnt --;
+            if (dm9000_device.packet_cnt > 0)
+            {
+            	DM9000_TRACE("dm9000 isr: tx second packet\n");
+
+                /* transmit packet II */
+                /* Set TX length to DM9000 */
+                dm9000_io_write(DM9000_TXPLL, dm9000_device.queue_packet_len & 0xff);
+                dm9000_io_write(DM9000_TXPLH, (dm9000_device.queue_packet_len >> 8) & 0xff);
+
+                /* Issue TX polling command */
+                dm9000_io_write(DM9000_TCR, TCR_TXREQ);	/* Cleared after TX complete */
+            }
+
+            /* One packet sent complete */
+            rt_sem_release(&sem_ack);
+        }
+    }
+
+    /* Re-enable interrupt mask */
+    dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);
+
+    DM9000_IO = last_io;
+}
+
+/* RT-Thread Device Interface */
+/* initialize the interface */
+static rt_err_t rt_dm9000_init(rt_device_t dev)
+{
+    int i, oft, lnk;
+    rt_uint32_t value;
+
+    /* RESET device */
+    dm9000_io_write(DM9000_NCR, NCR_RST);
+    delay_ms(1000);		/* delay 1ms */
+
+    /* identfy DM9000 */
+    value  = dm9000_io_read(DM9000_VIDL);
+    value |= dm9000_io_read(DM9000_VIDH) << 8;
+    value |= dm9000_io_read(DM9000_PIDL) << 16;
+    value |= dm9000_io_read(DM9000_PIDH) << 24;
+    if (value == DM9000_ID)
+    {
+        rt_kprintf("dm9000 id: 0x%x\n", value);
+    }
+    else
+    {
+        return -RT_ERROR;
+    }
+
+    /* GPIO0 on pre-activate PHY */
+    dm9000_io_write(DM9000_GPR, 0x00);	            /* REG_1F bit0 activate phyxcer */
+    dm9000_io_write(DM9000_GPCR, GPCR_GEP_CNTL);    /* Let GPIO0 output */
+    dm9000_io_write(DM9000_GPR, 0x00);                 /* Enable PHY */
+
+    /* Set PHY */
+    phy_mode_set(dm9000_device.mode);
+
+    /* Program operating register */
+    dm9000_io_write(DM9000_NCR, 0x0);	/* only intern phy supported by now */
+    dm9000_io_write(DM9000_TCR, 0);	    /* TX Polling clear */
+    dm9000_io_write(DM9000_BPTR, 0x3f);	/* Less 3Kb, 200us */
+    dm9000_io_write(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));	/* Flow Control : High/Low Water */
+    dm9000_io_write(DM9000_FCR, 0x0);	/* SH FIXME: This looks strange! Flow Control */
+    dm9000_io_write(DM9000_SMCR, 0);	/* Special Mode */
+    dm9000_io_write(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);	/* clear TX status */
+    dm9000_io_write(DM9000_ISR, 0x0f);	/* Clear interrupt status */
+    dm9000_io_write(DM9000_TCR2, 0x80);	/* Switch LED to mode 1 */
+
+    /* set mac address */
+    for (i = 0, oft = 0x10; i < 6; i++, oft++)
+        dm9000_io_write(oft, dm9000_device.dev_addr[i]);
+    /* set multicast address */
+    for (i = 0, oft = 0x16; i < 8; i++, oft++)
+        dm9000_io_write(oft, 0xff);
+
+    /* Activate DM9000 */
+    dm9000_io_write(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);	/* RX enable */
+    dm9000_io_write(DM9000_IMR, IMR_PAR);
+
+	if (dm9000_device.mode == DM9000_AUTO)
+	{
+	    while (!(phy_read(1) & 0x20))
+	    {
+	        /* autonegation complete bit */
+	        rt_thread_delay(10);
+	        i++;
+	        if (i == 10000)
+	        {
+	            rt_kprintf("could not establish link\n");
+	            return 0;
+	        }
+	    }
+	}
+
+    /* see what we've got */
+    lnk = phy_read(17) >> 12;
+    rt_kprintf("operating at ");
+    switch (lnk)
+    {
+    case 1:
+        rt_kprintf("10M half duplex ");
+        break;
+    case 2:
+        rt_kprintf("10M full duplex ");
+        break;
+    case 4:
+        rt_kprintf("100M half duplex ");
+        break;
+    case 8:
+        rt_kprintf("100M full duplex ");
+        break;
+    default:
+        rt_kprintf("unknown: %d ", lnk);
+        break;
+    }
+    rt_kprintf("mode\n");
+
+    dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);	/* Enable TX/RX interrupt mask */
+
+    return RT_EOK;
+}
+
+static rt_err_t rt_dm9000_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    return RT_EOK;
+}
+
+static rt_err_t rt_dm9000_close(rt_device_t dev)
+{
+    /* RESET devie */
+    phy_write(0, 0x8000);	/* PHY RESET */
+    dm9000_io_write(DM9000_GPR, 0x01);	/* Power-Down PHY */
+    dm9000_io_write(DM9000_IMR, 0x80);	/* Disable all interrupt */
+    dm9000_io_write(DM9000_RCR, 0x00);	/* Disable RX */
+
+    return RT_EOK;
+}
+
+static rt_size_t rt_dm9000_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
+}
+
+static rt_size_t rt_dm9000_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
+}
+
+static rt_err_t rt_dm9000_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+    switch (cmd)
+    {
+    case NIOCTL_GADDR:
+        /* get mac address */
+        if (args) rt_memcpy(args, dm9000_device.dev_addr, 6);
+        else return -RT_ERROR;
+        break;
+
+    default :
+        break;
+    }
+
+    return RT_EOK;
+}
+
+/* ethernet device interface */
+/* transmit packet. */
+rt_err_t rt_dm9000_tx( rt_device_t dev, struct pbuf* p)
+{
+	DM9000_TRACE("dm9000 tx: %d\n", p->tot_len);
+
+    /* lock DM9000 device */
+    rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
+
+    /* disable dm9000a interrupt */
+    dm9000_io_write(DM9000_IMR, IMR_PAR);
+
+    /* Move data to DM9000 TX RAM */
+    DM9000_outb(DM9000_IO_BASE, DM9000_MWCMD);
+
+    {
+		/* q traverses through linked list of pbuf's
+		 * This list MUST consist of a single packet ONLY */
+		struct pbuf *q;
+		rt_uint16_t pbuf_index = 0;
+		rt_uint8_t word[2], word_index = 0;
+
+		q = p;
+		/* Write data into dm9000a, two bytes at a time
+		 * Handling pbuf's with odd number of bytes correctly
+		 * No attempt to optimize for speed has been made */
+		while (q)
+		{
+			if (pbuf_index < q->len)
+			{
+				word[word_index++] = ((u8_t*)q->payload)[pbuf_index++];
+				if (word_index == 2)
+				{
+				    DM9000_outw(DM9000_DATA_BASE, (word[1] << 8) | word[0]);
+					word_index = 0;
+				}
+			}
+			else
+			{
+				q = q->next;
+				pbuf_index = 0;
+			}
+		}
+		/* One byte could still be unsent */
+		if (word_index == 1)
+		{
+		    DM9000_outw(DM9000_DATA_BASE, word[0]);
+		}
+    }
+
+    if (dm9000_device.packet_cnt == 0)
+    {
+    	DM9000_TRACE("dm9000 tx: first packet\n");
+
+        dm9000_device.packet_cnt ++;
+        /* Set TX length to DM9000 */
+        dm9000_io_write(DM9000_TXPLL, p->tot_len & 0xff);
+        dm9000_io_write(DM9000_TXPLH, (p->tot_len >> 8) & 0xff);
+
+        /* Issue TX polling command */
+        dm9000_io_write(DM9000_TCR, TCR_TXREQ);	/* Cleared after TX complete */
+    }
+    else
+    {
+    	DM9000_TRACE("dm9000 tx: second packet\n");
+
+        dm9000_device.packet_cnt ++;
+        dm9000_device.queue_packet_len = p->tot_len;
+    }
+
+    /* enable dm9000a interrupt */
+    dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);
+
+    /* unlock DM9000 device */
+    rt_sem_release(&sem_lock);
+
+    /* wait ack */
+    rt_sem_take(&sem_ack, RT_WAITING_FOREVER);
+
+	DM9000_TRACE("dm9000 tx done\n");
+
+    return RT_EOK;
+}
+
+/* reception packet. */
+struct pbuf *rt_dm9000_rx(rt_device_t dev)
+{
+    struct pbuf* p;
+    rt_uint32_t rxbyte;
+
+    /* init p pointer */
+    p = RT_NULL;
+
+    /* lock DM9000 device */
+    rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
+
+    /* Check packet ready or not */
+    dm9000_io_read(DM9000_MRCMDX);	    		/* Dummy read */
+    rxbyte = DM9000_inb(DM9000_DATA_BASE);		/* Got most updated data */
+    if (rxbyte)
+    {
+        rt_uint16_t rx_status, rx_len;
+        rt_uint16_t* data;
+
+        if (rxbyte > 1)
+        {
+			DM9000_TRACE("dm9000 rx: rx error, stop device\n");
+
+            dm9000_io_write(DM9000_RCR, 0x00);	/* Stop Device */
+            dm9000_io_write(DM9000_ISR, 0x80);	/* Stop INT request */
+        }
+
+        /* A packet ready now  & Get status/length */
+        DM9000_outb(DM9000_IO_BASE, DM9000_MRCMD);
+
+        rx_status = DM9000_inw(DM9000_DATA_BASE);
+        rx_len = DM9000_inw(DM9000_DATA_BASE);
+
+		DM9000_TRACE("dm9000 rx: status %04x len %d\n", rx_status, rx_len);
+
+        /* allocate buffer */
+        p = pbuf_alloc(PBUF_LINK, rx_len, PBUF_RAM);
+        if (p != RT_NULL)
+        {
+            struct pbuf* q;
+            rt_int32_t len;
+
+            for (q = p; q != RT_NULL; q= q->next)
+            {
+                data = (rt_uint16_t*)q->payload;
+                len = q->len;
+
+                while (len > 0)
+                {
+                    *data = DM9000_inw(DM9000_DATA_BASE);
+                    data ++;
+                    len -= 2;
+                }
+            }
+			DM9000_TRACE("\n");
+        }
+        else
+        {
+            rt_uint16_t dummy;
+
+			DM9000_TRACE("dm9000 rx: no pbuf\n");
+
+            /* no pbuf, discard data from DM9000 */
+            data = &dummy;
+            while (rx_len)
+            {
+                *data = DM9000_inw(DM9000_DATA_BASE);
+                rx_len -= 2;
+            }
+        }
+
+        if ((rx_status & 0xbf00) || (rx_len < 0x40)
+                || (rx_len > DM9000_PKT_MAX))
+        {
+			rt_kprintf("rx error: status %04x\n", rx_status);
+
+            if (rx_status & 0x100)
+            {
+                rt_kprintf("rx fifo error\n");
+            }
+            if (rx_status & 0x200)
+            {
+                rt_kprintf("rx crc error\n");
+            }
+            if (rx_status & 0x8000)
+            {
+                rt_kprintf("rx length error\n");
+            }
+            if (rx_len > DM9000_PKT_MAX)
+            {
+                rt_kprintf("rx length too big\n");
+
+                /* RESET device */
+                dm9000_io_write(DM9000_NCR, NCR_RST);
+                rt_thread_delay(1); /* delay 5ms */
+            }
+
+            /* it issues an error, release pbuf */
+            pbuf_free(p);
+            p = RT_NULL;
+        }
+    }
+    else
+    {
+        /* restore receive interrupt */
+	    dm9000_device.imr_all = IMR_PAR | IMR_PTM | IMR_PRM;
+        dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);
+    }
+
+    /* unlock DM9000 device */
+    rt_sem_release(&sem_lock);
+
+    return p;
+}
+
+void rt_hw_dm9000_init()
+{
+    rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO);
+    rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
+
+    dm9000_device.type  = TYPE_DM9000A;
+	dm9000_device.mode	= DM9000_AUTO;
+	dm9000_device.packet_cnt = 0;
+	dm9000_device.queue_packet_len = 0;
+
+    /*
+     * SRAM Tx/Rx pointer automatically return to start address,
+     * Packet Transmitted, Packet Received
+     */
+    dm9000_device.imr_all = IMR_PAR | IMR_PTM | IMR_PRM;
+
+    dm9000_device.dev_addr[0] = 0x01;
+    dm9000_device.dev_addr[1] = 0x60;
+    dm9000_device.dev_addr[2] = 0x6E;
+    dm9000_device.dev_addr[3] = 0x11;
+    dm9000_device.dev_addr[4] = 0x02;
+    dm9000_device.dev_addr[5] = 0x0F;
+
+    dm9000_device.parent.parent.init       = rt_dm9000_init;
+    dm9000_device.parent.parent.open       = rt_dm9000_open;
+    dm9000_device.parent.parent.close      = rt_dm9000_close;
+    dm9000_device.parent.parent.read       = rt_dm9000_read;
+    dm9000_device.parent.parent.write      = rt_dm9000_write;
+    dm9000_device.parent.parent.control    = rt_dm9000_control;
+    dm9000_device.parent.parent.private    = RT_NULL;
+
+    dm9000_device.parent.eth_rx     = rt_dm9000_rx;
+    dm9000_device.parent.eth_tx     = rt_dm9000_tx;
+
+    eth_device_init(&(dm9000_device.parent), "e0");
+}
+
+void dm9000a(void)
+{
+    rt_kprintf("\n");
+    rt_kprintf("NCR   (0x00): %02x\n", dm9000_io_read(DM9000_NCR));
+    rt_kprintf("NSR   (0x01): %02x\n", dm9000_io_read(DM9000_NSR));
+    rt_kprintf("TCR   (0x02): %02x\n", dm9000_io_read(DM9000_TCR));
+    rt_kprintf("TSRI  (0x03): %02x\n", dm9000_io_read(DM9000_TSR1));
+    rt_kprintf("TSRII (0x04): %02x\n", dm9000_io_read(DM9000_TSR2));
+    rt_kprintf("RCR   (0x05): %02x\n", dm9000_io_read(DM9000_RCR));
+    rt_kprintf("RSR   (0x06): %02x\n", dm9000_io_read(DM9000_RSR));
+    rt_kprintf("ORCR  (0x07): %02x\n", dm9000_io_read(DM9000_ROCR));
+    rt_kprintf("CRR   (0x2C): %02x\n", dm9000_io_read(DM9000_CHIPR));
+    rt_kprintf("CSCR  (0x31): %02x\n", dm9000_io_read(DM9000_CSCR));
+    rt_kprintf("RCSSR (0x32): %02x\n", dm9000_io_read(DM9000_RCSSR));
+    rt_kprintf("ISR   (0xFE): %02x\n", dm9000_io_read(DM9000_ISR));
+    rt_kprintf("IMR   (0xFF): %02x\n", dm9000_io_read(DM9000_IMR));
+    rt_kprintf("\n");
+}
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+FINSH_FUNCTION_EXPORT(dm9000a, dm9000a register dump);
+#endif

bsp/mini2440/dm9000.h

+#ifndef __DM9000_H__
+#define __DM9000_H__
+
+#define DM9000_IO_BASE		0x6C000000
+#define DM9000_DATA_BASE	0x6C000008
+
+#define DM9000_IO 			(*((volatile rt_uint16_t *) 0x6C000000)) // CMD = 0
+#define DM9000_DATA 		(*((volatile rt_uint16_t *) 0x6C000008)) // CMD = 1
+
+#define DM9000_inb(r) 		(*(volatile rt_uint8_t  *)r)
+#define DM9000_outb(r, d) 	(*(volatile rt_uint8_t  *)r = d)
+#define DM9000_inw(r) 		(*(volatile rt_uint16_t *)r)
+#define DM9000_outw(r, d) 	(*(volatile rt_uint16_t *)r = d)
+
+#define DM9000_ID		    0x90000A46  /* DM9000 ID */
+#define DM9000_PKT_MAX		1536	    /* Received packet max size */
+#define DM9000_PKT_RDY		0x01	    /* Packet ready to receive */
+
+#define DM9000_NCR          0x00
+#define DM9000_NSR          0x01
+#define DM9000_TCR          0x02
+#define DM9000_TSR1         0x03
+#define DM9000_TSR2         0x04
+#define DM9000_RCR          0x05
+#define DM9000_RSR          0x06
+#define DM9000_ROCR         0x07
+#define DM9000_BPTR         0x08
+#define DM9000_FCTR         0x09
+#define DM9000_FCR          0x0A
+#define DM9000_EPCR         0x0B
+#define DM9000_EPAR         0x0C
+#define DM9000_EPDRL        0x0D
+#define DM9000_EPDRH        0x0E
+#define DM9000_WCR          0x0F
+
+#define DM9000_PAR          0x10
+#define DM9000_MAR          0x16
+
+#define DM9000_GPCR         0x1e
+#define DM9000_GPR          0x1f
+#define DM9000_TRPAL        0x22
+#define DM9000_TRPAH        0x23
+#define DM9000_RWPAL        0x24
+#define DM9000_RWPAH        0x25
+
+#define DM9000_VIDL         0x28
+#define DM9000_VIDH         0x29
+#define DM9000_PIDL         0x2A
+#define DM9000_PIDH         0x2B
+
+#define DM9000_CHIPR        0x2C
+#define DM9000_TCR2			0x2D
+#define DM9000_OTCR			0x2E
+#define DM9000_SMCR         0x2F
+
+#define DM9000_ETCR			0x30	/* early transmit control/status register */
+#define DM9000_CSCR			0x31	/* check sum control register */
+#define DM9000_RCSSR		0x32	/* receive check sum status register */
+
+#define DM9000_MRCMDX       0xF0
+#define DM9000_MRCMD        0xF2
+#define DM9000_MRRL         0xF4
+#define DM9000_MRRH         0xF5
+#define DM9000_MWCMDX       0xF6
+#define DM9000_MWCMD        0xF8
+#define DM9000_MWRL         0xFA
+#define DM9000_MWRH         0xFB
+#define DM9000_TXPLL        0xFC
+#define DM9000_TXPLH        0xFD
+#define DM9000_ISR          0xFE
+#define DM9000_IMR          0xFF
+
+#define CHIPR_DM9000A       0x19
+#define CHIPR_DM9000B       0x1B
+
+#define NCR_EXT_PHY         (1<<7)
+#define NCR_WAKEEN          (1<<6)
+#define NCR_FCOL            (1<<4)
+#define NCR_FDX             (1<<3)
+#define NCR_LBK             (3<<1)
+#define NCR_RST             (1<<0)
+
+#define NSR_SPEED           (1<<7)
+#define NSR_LINKST          (1<<6)
+#define NSR_WAKEST          (1<<5)
+#define NSR_TX2END          (1<<3)
+#define NSR_TX1END          (1<<2)
+#define NSR_RXOV            (1<<1)
+
+#define TCR_TJDIS           (1<<6)
+#define TCR_EXCECM          (1<<5)
+#define TCR_PAD_DIS2        (1<<4)
+#define TCR_CRC_DIS2        (1<<3)
+#define TCR_PAD_DIS1        (1<<2)
+#define TCR_CRC_DIS1        (1<<1)
+#define TCR_TXREQ           (1<<0)
+
+#define TSR_TJTO            (1<<7)
+#define TSR_LC              (1<<6)
+#define TSR_NC              (1<<5)
+#define TSR_LCOL            (1<<4)
+#define TSR_COL             (1<<3)
+#define TSR_EC              (1<<2)
+
+#define RCR_WTDIS           (1<<6)
+#define RCR_DIS_LONG        (1<<5)
+#define RCR_DIS_CRC         (1<<4)
+#define RCR_ALL             (1<<3)
+#define RCR_RUNT            (1<<2)
+#define RCR_PRMSC           (1<<1)
+#define RCR_RXEN            (1<<0)
+
+#define RSR_RF              (1<<7)
+#define RSR_MF              (1<<6)
+#define RSR_LCS             (1<<5)
+#define RSR_RWTO            (1<<4)
+#define RSR_PLE             (1<<3)
+#define RSR_AE              (1<<2)
+#define RSR_CE              (1<<1)
+#define RSR_FOE             (1<<0)
+
+#define FCTR_HWOT(ot)       (( ot & 0xf ) << 4 )
+#define FCTR_LWOT(ot)       ( ot & 0xf )
+
+#define IMR_PAR             (1<<7)
+#define IMR_ROOM            (1<<3)
+#define IMR_ROM             (1<<2)
+#define IMR_PTM             (1<<1)
+#define IMR_PRM             (1<<0)
+
+#define ISR_ROOS            (1<<3)
+#define ISR_ROS             (1<<2)
+#define ISR_PTS             (1<<1)
+#define ISR_PRS             (1<<0)
+#define ISR_CLR_STATUS      (ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS)
+
+#define EPCR_REEP           (1<<5)
+#define EPCR_WEP            (1<<4)
+#define EPCR_EPOS           (1<<3)
+#define EPCR_ERPRR          (1<<2)
+#define EPCR_ERPRW          (1<<1)
+#define EPCR_ERRE           (1<<0)
+
+#define GPCR_GEP_CNTL       (1<<0)
+
+void rt_hw_dm9000_init(void);
+
+#endif

bsp/mini2440/lcd.c

@@ -14,7 +14,7 @@
 
 #include <rtthread.h>
 
-#include <s3c2410.h>
+#include <s3c24x0.h>
 
 #define MVAL		(13)
 #define MVAL_USED 	(0)		//0=each frame   1=rate by MVAL

bsp/mini2440/rtconfig.h

@@ -31,9 +31,6 @@
 /* Using Event*/
 #define RT_USING_EVENT
 
-/* Using Faset Event*/
-#define RT_USING_FASTEVENT
-
 /* Using MailBox*/
 #define RT_USING_MAILBOX
 
@@ -64,10 +61,13 @@
 /* SECTION: FinSH shell options */
 /* Using FinSH as Shell*/
 #define RT_USING_FINSH
+/* Using symbol table */
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
 
 /* SECTION: a runtime libc library */
 /* a runtime libc library*/
-#define RT_USING_NEWLIB
+/* #define RT_USING_NEWLIB */
 
 /* SECTION: a mini libc */
 /* Using mini libc library*/
@@ -79,11 +79,13 @@
 
 /* SECTION: RTGUI support */
 /* using RTGUI support*/
-#define RT_USING_RTGUI
+/* #define RT_USING_RTGUI */
 
 /* SECTION: Device filesystem support */
 /* using DFS support*/
 #define RT_USING_DFS
+#define RT_USING_DFS_EFSL
+#define RT_USING_DFS_YAFFS2
 
 #define RT_USING_WORKDIR
 

bsp/mini2440/rtconfig.py

 # component options
+
+# finsh shell option
 RT_USING_FINSH = True
+
+# device file system options
 RT_USING_DFS = True
-RT_USING_DFS_YAFFS2 = False
 RT_USING_DFS_EFSL = True
+RT_USING_DFS_ELMFAT = False
+RT_USING_DFS_YAFFS2 = False
+
+# lwip options
 RT_USING_LWIP = True
 
+# rtgui options
+RT_USING_RTGUI = False
+
 # toolchains options
 ARCH='arm'
 CPU='s3c24x0'
-PLATFORM = 'gcc'
-EXEC_PATH = 'd:/SourceryGCC/bin'
-#PLATFORM = 'armcc'
-#EXEC_PATH = 'C:/Keil'
+TextBase='0x30000000'
+
+#PLATFORM = 'gcc'
+#EXEC_PATH = 'd:/SourceryGCC/bin'
+PLATFORM = 'armcc'
+EXEC_PATH = 'C:/Keil'
 BUILD = 'debug'
 
 if PLATFORM == 'gcc':
@@ -51,10 +63,10 @@ elif PLATFORM == 'armcc':
     LINK = 'armlink'
     TARGET_EXT = 'axf'
 
-    DEVICE = ' --device DARMSTM'
+    DEVICE = ' --device DARMSS9'
     CFLAGS = DEVICE + ' --apcs=interwork'
     AFLAGS = DEVICE
-    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-stm32.map --scatter mini2440_rom.sct'
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-mini2440.map --ro-base 0x30000000 --entry Entry_Point --first Entry_Point'
 
     CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
     LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'

bsp/mini2440/sdcard.c

@@ -20,21 +20,21 @@ volatile rt_uint32_t wt_cnt;
 volatile rt_int32_t RCA;
 
 /**
- * This function will set a hook function, which will be invoked when a memory 
+ * This function will set a hook function, which will be invoked when a memory
  * block is allocated from heap memory.
- * 
+ *
  * @param hook the hook function
  */
 static void sd_delay(rt_uint32_t ms)
 {
 	ms *= 7326;
-	while(--ms);	
+	while(--ms);
 }
 
 /**
- * This function will set a hook function, which will be invoked when a memory 
+ * This function will set a hook function, which will be invoked when a memory
  * block is allocated from heap memory.
- * 
+ *
  * @param hook the hook function
  */
 static int sd_cmd_end(int cmd, int be_resp)
@@ -44,12 +44,12 @@ static int sd_cmd_end(int cmd, int be_resp)
 	if(!be_resp)
 	{
 		finish0=SDICSTA;
-		
+
 		while((finish0&0x800)!=0x800)
 	    		finish0=SDICSTA;
 
 		SDICSTA=finish0;
-		
+
 		return RT_EOK;
 	}
 	else
@@ -86,9 +86,9 @@ static int sd_cmd_end(int cmd, int be_resp)
 }
 
 /**
- * This function will set a hook function, which will be invoked when a memory 
+ * This function will set a hook function, which will be invoked when a memory
  * block is allocated from heap memory.
- * 
+ *
  * @param hook the hook function
  */
 static int sd_data_end(void)
@@ -109,9 +109,9 @@ static int sd_data_end(void)
 }
 
 /**
- * This function will set a hook function, which will be invoked when a memory 
+ * This function will set a hook function, which will be invoked when a memory
  * block is allocated from heap memory.
- * 
+ *
  * @param hook the hook function
  */
 static void sd_cmd0(void)
@@ -123,9 +123,9 @@ static void sd_cmd0(void)
 }
 
 /**
- * This function will set a hook function, which will be invoked when a memory 
+ * This function will set a hook function, which will be invoked when a memory
  * block is allocated from heap memory.
- * 
+ *
  * @param hook the hook function
  */
 static int sd_cmd55(void)
@@ -140,28 +140,28 @@ static int sd_cmd55(void)
 }
 
 /**
- * This function will set a hook function, which will be invoked when a memory 
+ * This function will set a hook function, which will be invoked when a memory
  * block is allocated from heap memory.
- * 
+ *
  * @param hook the hook function
  */
 static void sd_sel_desel(char sel_desel)
 {
 	if(sel_desel)
 	{
-RECMDS7:    
+RECMDS7:
 		SDICARG =RCA << 16;
 		SDICCON = (0x1 << 9) | (0x1 << 8) | 0x47;
 
 		if(sd_cmd_end(7, 1) == RT_ERROR)
 	    		goto RECMDS7;
-	    	
+
 		if( SDIRSP0 & (0x1e00 != 0x800))
 	    		goto RECMDS7;
 	}
 	else
 	{
-RECMDD7:    
+RECMDD7:
 		SDICARG=0<<16;
 		SDICCON=(0x1<<8)|0x47;
 
@@ -171,9 +171,9 @@ RECMDD7:
 }
 
 /**
- * This function will set a hook function, which will be invoked when a memory 
+ * This function will set a hook function, which will be invoked when a memory
  * block is allocated from heap memory.
- * 
+ *
  * @param hook the hook function
  */
 static void sd_setbus(void)
@@ -189,9 +189,9 @@ SET_BUS:
 }
 
 /**
- * This function will set a hook function, which will be invoked when a memory 
+ * This function will set a hook function, which will be invoked when a memory
  * block is allocated from heap memory.
- * 
+ *
  * @param hook the hook function
  */
 int sd_mmc_ocr(void)
@@ -212,14 +212,14 @@ int sd_mmc_ocr(void)
 		}
 	}
 	SDICSTA=0xa00;
-	
+
 	return RT_ERROR;
 }
 
 /**
- * This function will set a hook function, which will be invoked when a memory 
+ * This function will set a hook function, which will be invoked when a memory
  * block is allocated from heap memory.
- * 
+ *
  * @param hook the hook function
  */
 int sd_ocr(void)
@@ -242,26 +242,26 @@ int sd_ocr(void)
 			SDICSTA=0xa00;
 	    		return RT_EOK;
 		}
-			
+
 		sd_delay(200);
 	}
 	SDICSTA=0xa00;
-	
+
 	return RT_ERROR;
 }
 
 /**
- * This function will set a hook function, which will be invoked when a memory 
+ * This function will set a hook function, which will be invoked when a memory
  * block is allocated from heap memory.
- * 
+ *
  * @param hook the hook function
  */
 rt_uint8_t sd_init(void)
-{  
+{
 	//-- SD controller & card initialize
 	int i;
 	/* Important notice for MMC test condition */
-	/* Cmd & Data lines must be enabled by pull up resister */	
+	/* Cmd & Data lines must be enabled by pull up resister */
 	SDIPRE=PCLK/(INICLK)-1;
 	SDICON=1;
 	SDIFSTA=SDIFSTA|(1<<16);
@@ -293,18 +293,18 @@ rt_uint8_t sd_init(void)
 RECMD2:
 	SDICARG=0x0;
 	SDICCON=(0x1<<10)|(0x1<<9)|(0x1<<8)|0x42;
-	if(sd_cmd_end(2, 1) == RT_ERROR) 
+	if(sd_cmd_end(2, 1) == RT_ERROR)
 		goto RECMD2;
 
-RECMD3:					    
+RECMD3:
 	SDICARG=0<<16;
 	SDICCON=(0x1<<9)|(0x1<<8)|0x43;
-	if(sd_cmd_end(3, 1) == RT_ERROR) 
+	if(sd_cmd_end(3, 1) == RT_ERROR)
 		goto RECMD3;
 
 	RCA=(SDIRSP0 & 0xffff0000 )>>16;
 	SDIPRE=(PCLK/(SDCLK*2))-1;
-	if( SDIRSP0 & (0x1e00!=0x600) ) 
+	if( SDIRSP0 & (0x1e00!=0x600) )
 		goto RECMD3;
 
 	sd_sel_desel(1);
@@ -315,16 +315,16 @@ RECMD3:
 }
 
 /**
- * This function will set a hook function, which will be invoked when a memory 
+ * This function will set a hook function, which will be invoked when a memory
  * block is allocated from heap memory.
- * 
+ *
  * @param hook the hook function
  */
 rt_uint8_t sd_readblock(rt_uint32_t address, rt_uint8_t* buf)
 {
 	int status;
 
-	rd_cnt=0;    
+	rd_cnt=0;
 	// SDICON |= (1<<1);
 	SDIDCON = (2 << 22) | (1 << 19) | (1 << 17) | (1 << 16) | (1 << 14) | (2 << 12) | (1 << 0);
 	SDICARG = address;
@@ -332,7 +332,7 @@ rt_uint8_t sd_readblock(rt_uint32_t address, rt_uint8_t* buf)
 RERDCMD:
 	SDICCON = (0x1 << 9 ) | (0x1 << 8) | 0x51;
 	if(sd_cmd_end(17, 1) == RT_ERROR)
-		goto RERDCMD;       
+		goto RERDCMD;
 
 	SDICSTA = 0xa00;
 
@@ -376,16 +376,16 @@ RERDCMD:
 }
 
 /**
- * This function will set a hook function, which will be invoked when a memory 
+ * This function will set a hook function, which will be invoked when a memory
  * block is allocated from heap memory.
- * 
+ *
  * @param hook the hook function
  */
 rt_uint8_t sd_writeblock(rt_uint32_t address, rt_uint8_t* buf)
 {
 	int status;
 
-	wt_cnt=0;    
+	wt_cnt=0;
 	SDIFSTA = SDIFSTA | (1 << 16);
 	SDIDCON = (2 << 22) | (1 << 20) | (1 << 17) | (1 << 16) | (1 << 14) | (3 << 12) | (1 << 0);
 	SDICARG = address;
@@ -395,13 +395,13 @@ REWTCMD:
 
 	if(sd_cmd_end(24, 1) == RT_ERROR)
 		goto REWTCMD;
-	    
+
 	SDICSTA=0xa00;
 
     	while(wt_cnt < 128*1)
     	{
     		status = SDIFSTA;
-    		if((status & 0x2000) == 0x2000) 
+    		if((status & 0x2000) == 0x2000)
     		{
         		SDIDAT=*(rt_uint32_t*)buf;
         		wt_cnt++;
@@ -412,7 +412,7 @@ REWTCMD:
 	{
 		rt_kprintf("Data Error\n");
 		return RT_ERROR;
-	}	
+	}
 	SDIDCON = SDIDCON &~ (7<<12);
 	SDIDSTA = 0x10;
 
@@ -428,20 +428,20 @@ REWTCMD:
 struct rt_device sdcard_device[4];
 struct dfs_partition part[4];
 /**
- * This function will set a hook function, which will be invoked when a memory 
+ * This function will set a hook function, which will be invoked when a memory
  * block is allocated from heap memory.
- * 
+ *
  * @param hook the hook function
  */
 static rt_err_t rt_sdcard_init(rt_device_t dev)
-{	
+{
 	return 0;
 }
 
 /**
- * This function will set a hook function, which will be invoked when a memory 
+ * This function will set a hook function, which will be invoked when a memory
  * block is allocated from heap memory.
- * 
+ *
  * @param hook the hook function
  */
 static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag)
@@ -450,9 +450,9 @@ static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag)
 }
 
 /**
- * This function will set a hook function, which will be invoked when a memory 
+ * This function will set a hook function, which will be invoked when a memory
  * block is allocated from heap memory.
- * 
+ *
  * @param hook the hook function
  */
 static rt_err_t rt_sdcard_close(rt_device_t dev)
@@ -461,9 +461,9 @@ static rt_err_t rt_sdcard_close(rt_device_t dev)
 }
 
 /**
- * This function will set a hook function, which will be invoked when a memory 
+ * This function will set a hook function, which will be invoked when a memory
  * block is allocated from heap memory.
- * 
+ *
  * @param hook the hook function
  */
 static rt_err_t rt_sdcard_control(rt_device_t dev, rt_uint8_t cmd, void *args)
@@ -472,9 +472,9 @@ static rt_err_t rt_sdcard_control(rt_device_t dev, rt_uint8_t cmd, void *args)
 }
 
 /**
- * This function will set a hook function, which will be invoked when a memory 
+ * This function will set a hook function, which will be invoked when a memory
  * block is allocated from heap memory.
- * 
+ *
  * @param hook the hook function
  */
 static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
@@ -482,49 +482,58 @@ static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_
 	int i;
 	struct dfs_partition *part = (struct dfs_partition *)dev->private;
 
-	if ( dev == RT_NULL ) return -DFS_STATUS_EINVAL;
-	
+	if ( dev == RT_NULL )
+	{
+		rt_set_errno(-DFS_STATUS_EINVAL);
+		return 0;
+	}
+
 	/* read all sectors */
 	for (i = 0; i < size / SECTOR_SIZE; i ++)
 	{
 		rt_sem_take(part->lock, RT_WAITING_FOREVER);
-		sd_readblock((part->offset + i)*SECTOR_SIZE + pos, 
-			(rt_uint8_t*)(buffer + i * SECTOR_SIZE));
+		sd_readblock((part->offset + i)*SECTOR_SIZE + pos,
+			(rt_uint8_t*)((rt_uint8_t*)buffer + i * SECTOR_SIZE));
 		rt_sem_release(part->lock);
 	}
+
 	/* the length of reading must align to SECTOR SIZE */
 	return size;
 }
 
 /**
- * This function will set a hook function, which will be invoked when a memory 
+ * This function will set a hook function, which will be invoked when a memory
  * block is allocated from heap memory.
- * 
+ *
  * @param hook the hook function
  */
-static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) 
+static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
 	int i;
 	struct dfs_partition *part = (struct dfs_partition *)dev->private;
 
-	if ( dev == RT_NULL ) return -DFS_STATUS_EINVAL;
-	
+	if ( dev == RT_NULL )
+	{
+		rt_set_errno(-DFS_STATUS_EINVAL);
+		return 0;
+	}
+
 	/* read all sectors */
 	for (i = 0; i < size / SECTOR_SIZE; i++)
 	{
 		rt_sem_take(part->lock, RT_WAITING_FOREVER);
-		sd_writeblock((part->offset + i)*SECTOR_SIZE + pos, 
-			(rt_uint8_t*)(buffer + i * SECTOR_SIZE));
+		sd_writeblock((part->offset + i)*SECTOR_SIZE + pos,
+			(rt_uint8_t*)((rt_uint8_t*)buffer + i * SECTOR_SIZE));
 		rt_sem_release(part->lock);
 	}
-	
+
 	/* the length of reading must align to SECTOR SIZE */
 	return size;
 }
 
 /**
  * This function will register sd card to device system
- * 
+ *
  * @param hook the hook function
  */
 void rt_hw_sdcard_init()
@@ -532,13 +541,13 @@ void rt_hw_sdcard_init()
 	rt_uint8_t i, status;
 	rt_uint8_t *sector;
 	char dname[4];
-	char sname[8];	
-		
+	char sname[8];
+
 	if (sd_init() == RT_EOK)
 	{
 		/* get the first sector to read partition table */
 		sector = (rt_uint8_t*) rt_malloc (512);
-		if (sector == RT_NULL) 
+		if (sector == RT_NULL)
 		{
 			rt_kprintf("allocate partition sector buffer failed\n");
 			return;
@@ -554,7 +563,7 @@ void rt_hw_sdcard_init()
 				{
 					rt_snprintf(dname, 4, "sd%d",  i);
 					rt_snprintf(sname, 8, "sem_sd%d",  i);
-					part[i].lock = rt_sem_create(sname, 1, RT_IPC_FLAG_FIFO); 
+					part[i].lock = rt_sem_create(sname, 1, RT_IPC_FLAG_FIFO);
 
 					/* register sdcard device */
 					sdcard_device[i].init = rt_sdcard_init;
@@ -565,17 +574,17 @@ void rt_hw_sdcard_init()
 					sdcard_device[i].control = rt_sdcard_control;
 					sdcard_device[i].private= &part[i];
 
-					rt_device_register(&sdcard_device[i], dname, 
+					rt_device_register(&sdcard_device[i], dname,
 						RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
 				}
-				else		
+				else
 				{
 					if(i == 0)
 					{
 						/* there is no partition table */
 						part[0].offset = 0;
 						part[0].size   = 0;
-						part[0].lock = rt_sem_create("sem_sd0", 1, RT_IPC_FLAG_FIFO); 
+						part[0].lock = rt_sem_create("sem_sd0", 1, RT_IPC_FLAG_FIFO);
 
 						/* register sdcard device */
 						sdcard_device[0].init = rt_sdcard_init;
@@ -586,13 +595,13 @@ void rt_hw_sdcard_init()
 						sdcard_device[0].control = rt_sdcard_control;
 						sdcard_device[0].private= &part[0];
 
-						rt_device_register(&sdcard_device[0], "sd0", 
+						rt_device_register(&sdcard_device[0], "sd0",
 							RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
 
 						break;
 					}
 				}
-			}	
+			}
 		}
 		else
 		{
@@ -601,7 +610,7 @@ void rt_hw_sdcard_init()
 
 		/* release sector buffer */
 		rt_free(sector);
-		
+
 		return;
 	}
 	else

bsp/mini2440/sdcard.h

 #ifndef __SDCARD_H
 #define __SDCARD_H
 
-#include  <s3c2410.h>
+#include  <s3c24x0.h>
 
 #define INICLK	300000
 #define SDCLK	24000000

bsp/mini2440/startup.c

@@ -18,13 +18,7 @@
 #include <rtthread.h>
 #include <rthw.h>
 
-#include <s3c2410.h>
-
-rt_uint8_t _irq_stack_start[1024];
-rt_uint8_t _fiq_stack_start[1024];
-rt_uint8_t _undefined_stack_start[512];
-rt_uint8_t _abort_stack_start[512];
-rt_uint8_t _svc_stack_start[1024] SECTION(".nobss");
+#include <s3c24x0.h>
 
 extern void rt_hw_interrupt_init(void);
 extern void rt_hw_board_init(void);
@@ -37,54 +31,23 @@ extern void rt_show_version(void);
 extern void rt_system_heap_init(void*, void*);
 extern void rt_hw_finsh_init(void);
 extern void rt_application_init(void);
-extern int rtl8019_device_register(char*);
 
 extern struct serial_device uart0;
 extern struct rt_device uart0_device;
 
 /**
- * @addtogroup s3ceb2410
+ * @addtogroup mini2440
  */
 
 /*@{*/
-
-#ifdef __CC_ARM
-	extern rt_uint8_t* __bss_start;
-	extern rt_uint8_t* __bss_end;
-#else
-	extern rt_uint8_t __bss_start;
-	extern rt_uint8_t __bss_end;
+#if defined(__CC_ARM)
+	extern int Image$$ER_ZI$$ZI$$Base;
+	extern int Image$$ER_ZI$$ZI$$Length;
+	extern int Image$$ER_ZI$$ZI$$Limit;
+#elif defined(__GNU_C__)
+	extern int __bss_end;
 #endif
 
-/*
- * 4 LEDs on S3CEB2410 : GPF4~GPF7
- */
-void led_set(rt_uint32_t led)
-{
-	GPFDAT = led;
-}
-
-/* led loop */
-void led_flash(void)
-{
-	rt_uint32_t i;
-
-	/* change the pin mux to enable the LED output */
-	GPFCON = 0x5500;
-
-	led_set(1 << 4);
-	for ( i = 0; i < 2000000; i++);
-
-	led_set(1 << 5);
-	for ( i = 0; i < 2000000; i++);
-
-	led_set(1 << 6);
-	for ( i = 0; i < 2000000; i++);
-
-	led_set(1 << 17);
-	for ( i = 0; i < 2000000; i++);
-}
-
 #ifdef RT_USING_FINSH
 extern void finsh_system_init(void);
 #endif
@@ -118,7 +81,7 @@ void rtthread_startup(void)
 
 	/* init heap memory system */
 #ifdef __CC_ARM
-	rt_system_heap_init((void*)__bss_end, (void*)0x34000000);
+	rt_system_heap_init((void*)&Image$$ER_ZI$$ZI$$Limit, (void*)0x07400000);
 #else
 	rt_system_heap_init(&__bss_end, (void*)0x34000000);
 #endif
@@ -126,22 +89,12 @@ void rtthread_startup(void)
 	/* init scheduler system */
 	rt_system_scheduler_init();
 
-	/* set idle thread hook */
-	rt_thread_idle_sethook(led_flash);
-
 #ifdef RT_USING_DEVICE
 	/* register uart1 */
-	rt_hw_serial_register(&uart0_device, "uart0", 
+	rt_hw_serial_register(&uart0_device, "uart0",
 		RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
-		&uart0);		
+		&uart0);
 	rt_hw_sdcard_init();
-#ifdef RT_USING_LWIP
-	/* init ethernet task */
-	eth_system_device_init();
-
-	/* init rtl8019 device */
-	rt_rtl8019_device_register("e0");
-#endif
 
 	/*init all registed devices */
 	rt_device_init_all();
@@ -155,7 +108,7 @@ void rtthread_startup(void)
 	finsh_system_init();
 #ifdef RT_USING_DEVICE
 	finsh_set_device("uart0");
-#endif	
+#endif
 #endif
 
 	/* init idle thread */
@@ -168,4 +121,17 @@ void rtthread_startup(void)
 	return ;
 }
 
+int main(void)
+{
+	rt_uint32_t UNUSED level;
+
+	/* disable interrupt first */
+	level = rt_hw_interrupt_disable();
+
+	/* startup RT-Thread RTOS */
+	rtthread_startup();
+
+	return 0;
+}
+
 /*@}*/

bsp/mini2440/touch.c

 #include <rthw.h>
 #include <rtthread.h>
-#include <s3c2410.h>
+#include <s3c24x0.h>
 
 /* ADCCON Register Bits */
 #define S3C2410_ADCCON_ECFLG		(1<<15)

libcpu/arm/s3c24x0/cpu.c

@@ -23,7 +23,8 @@
 #define ICACHE_MASK	(rt_uint32_t)(1 << 12)
 #define DCACHE_MASK	(rt_uint32_t)(1 << 2)
 
-static rt_uint32_t cp15_rd(void)
+#ifdef __GNU_C__
+rt_inline rt_uint32_t cp15_rd(void)
 {
 	rt_uint32_t i;
 
@@ -41,16 +42,56 @@ rt_inline void cache_enable(rt_uint32_t bit)
 		:"r" (bit)					\
 		:"memory");
 }
+
 rt_inline void cache_disable(rt_uint32_t bit)
 {
 	__asm__ __volatile__(			\
 		"mrc  p15,0,r0,c1,c0,0\n\t"	\
 		"bic  r0,r0,%0\n\t"			\
-		"mcr  p15,0,%0,c1,c0,0"		\
+		"mcr  p15,0,r0,c1,c0,0"		\
 		:							\
 		:"r" (bit)					\
 		:"memory");
 }
+#endif
+
+#ifdef __CC_ARM
+rt_inline rt_uint32_t cp15_rd(void)
+{
+	rt_uint32_t i;
+
+	__asm
+	{
+		mrc p15, 0, i, c1, c0, 0
+	}
+
+	return i;
+}
+
+rt_inline void cache_enable(rt_uint32_t bit)
+{
+	rt_uint32_t value;
+
+	__asm
+	{
+		mrc p15, 0, value, c1, c0, 0
+		orr value, value, bit
+		mcr p15, 0, value, c1, c0, 0
+	}
+}
+
+rt_inline void cache_disable(rt_uint32_t bit)
+{
+	rt_uint32_t value;
+
+	__asm
+	{
+		mrc p15, 0, value, c1, c0, 0
+		bic value, value, bit
+		mcr p15, 0, value, c1, c0, 0
+	}
+}
+#endif
 
 /**
  * enable I-Cache
@@ -126,7 +167,7 @@ void rt_hw_cpu_reset()
 
 	while(1);	/* loop forever and wait for reset to happen */
 
-	/*NOTREACHED*/
+	/* NEVER REACHED */
 }
 
 /**

libcpu/arm/s3c24x0/mmu.c

@@ -40,8 +40,7 @@
 #define RW_NCNB		(AP_RW|DOMAIN0|NCNB|DESC_SEC)
 #define RW_FAULT	(AP_RW|DOMAIN1|NCNB|DESC_SEC)
 
-void rt_hw_mmu_init(void);
-
+#ifdef __GNU_C__
 void mmu_setttbase(register rt_uint32_t i)
 {
 	asm ("mcr p15, 0, %0, c2, c2, 0": :"r" (i));
@@ -170,6 +169,92 @@ void mmu_invalidateicache()
 {
 	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
 }
+#endif
+
+#ifdef __CC_ARM
+__asm void mmu_setttbase(rt_uint32_t i)
+{
+	mcr p15, 0, r0, c2, c2, 0
+}
+
+__asm void mmu_setdomain(rt_uint32_t i)
+{
+	mcr p15,0, r0, c3, c0,  0
+}
+
+__asm void mmu_enablemmu()
+{
+	mrc p15, 0, r0, c1, c0, 0
+	orr r0, r0, #0x01
+	mcr p15, 0, r0, c1, c0, 0
+}
+
+__asm void mmu_disablemmu()
+{
+	mrc p15, 0, r0, c1, c0, 0
+	bic r0, r0, #0x01
+	mcr p15, 0, r0, c1, c0, 0
+}
+
+__asm void mmu_enableicache()
+{
+	mrc p15, 0, r0, c1, c0, 0
+	orr r0, r0, #0x100
+	mcr p15, 0, r0, c1, c0, 0
+}
+
+__asm void mmu_enabledcache()
+{
+	mrc p15, 0, r0, c1, c0, 0
+	orr r0, r0, #0x02
+	mcr p15, 0, r0, c1, c0, 0
+}
+
+__asm void mmu_disableicache()
+{
+	mrc p15, 0, r0, c1, c0, 0
+	bic r0, r0, #0x100
+	mcr p15, 0, r0, c1, c0, 0
+}
+
+__asm void mmu_disabledcache()
+{
+	mrc p15, 0, r0, c1, c0, 0
+	bic r0, r0, #0x100
+	mcr p15, 0, r0, c1, c0, 0
+}
+
+__asm void mmu_enablealignfault()
+{
+	mrc p15, 0, r0, c1, c0, 0
+	bic r0, r0, #0x01
+	mcr p15, 0, r0, c1, c0, 0
+}
+
+__asm void mmu_disablealignfault()
+{
+	mrc p15, 0, r0, c1, c0, 0
+	bic r0, r0, #0x02
+	mcr p15, 0, r0, c1, c0, 0
+}
+
+__asm void mmu_cleaninvalidatedcacheindex(int index)
+{
+	mcr p15, 0, r0, c7, c14, 2
+}
+
+__asm void mmu_invalidatetlb()
+{
+	mov r0, #0x0
+	mcr p15, 0, r0, c8, c7, 0
+}
+
+__asm void mmu_invalidateicache()
+{
+	mov r0, #0
+	mcr p15, 0, r0, c7, c5, 0
+}
+#endif
 
 void mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr)
 {

libcpu/arm/s3c24x0/rtc.c

@@ -17,26 +17,26 @@
 /**
  * This function access to rtc
  */
-static inline void rt_hw_rtc_access(int a)
+rt_inline void rt_hw_rtc_access(int a)
 {
 	switch (a)
 	{
 	case RTC_ENABLE:
-		RTCCON |= 0x01; 
+		RTCCON |= 0x01;
 		break;
 
 	case RTC_DISABLE:
-		RTCCON &= ~0x01; 
+		RTCCON &= ~0x01;
 		break;
 	}
 }
 
-static inline rt_uint32_t BCD2BIN(rt_uint8_t n)
+rt_inline rt_uint32_t BCD2BIN(rt_uint8_t n)
 {
         return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F));
 }
 
-static inline rt_uint8_t BIN2BCD(rt_uint32_t n)
+rt_inline rt_uint8_t BIN2BCD(rt_uint32_t n)
 {
         return (((n / 10) << 4) | (n % 10));
 }
@@ -53,7 +53,7 @@ void rt_hw_rtc_get (struct rtc_time *tmp)
 	rt_hw_rtc_access(RTC_ENABLE);
 
 	/* read RTC registers */
-	do 
+	do
 	{
 		sec = BCDSEC;
 		min = BCDMIN;