[bsp][lpc55sxx] update NXP SDK to 2_12_0

update NXP SDK to 2_12_0

bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_compiler.h → bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_compiler.h

 /**************************************************************************//**
  * @file     cmsis_compiler.h
  * @brief    CMSIS compiler generic header file
- * @version  V5.0.4
- * @date     10. January 2018
+ * @version  V5.1.0
+ * @date     09. October 2018
  ******************************************************************************/
 /*
  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,9 +35,15 @@
 
 
 /*
- * Arm Compiler 6 (armclang)
+ * Arm Compiler 6.6 LTM (armclang)
  */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
   #include "cmsis_armclang.h"
 
 
@@ -115,8 +121,11 @@
     #define __ALIGNED(x)                           __attribute__((aligned(x)))
   #endif
   #ifndef   __RESTRICT
-    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
-    #define __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
   #endif
 
 
@@ -187,6 +196,10 @@
     #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
     #define __RESTRICT
   #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
 
 
 /*
@@ -255,6 +268,10 @@
     #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
     #define __RESTRICT
   #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
 
 
 #else

bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_iccarm.h → bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_iccarm.h

 /**************************************************************************//**
  * @file     cmsis_iccarm.h
  * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
- * @version  V5.0.5
- * @date     10. January 2018
+ * @version  V5.3.0
+ * @date     14. April 2021
  ******************************************************************************/
 
 //------------------------------------------------------------------------------
 //
-// Copyright (c) 2017-2018 IAR Systems
+// Copyright (c) 2017-2021 IAR Systems
+// Copyright (c) 2017-2021 Arm Limited. All rights reserved.
+//
+// SPDX-License-Identifier: Apache-2.0
 //
 // Licensed under the Apache License, Version 2.0 (the "License")
 // you may not use this file except in compliance with the License.
@@ -110,6 +113,10 @@
   #define __ASM __asm
 #endif
 
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
 #ifndef __INLINE
   #define __INLINE inline
 #endif
@@ -150,7 +157,12 @@
 #endif
 
 #ifndef   __RESTRICT
-  #define __RESTRICT            restrict
+  #if __ICCARM_V8
+    #define __RESTRICT            __restrict
+  #else
+    /* Needs IAR language extensions */
+    #define __RESTRICT            restrict
+  #endif
 #endif
 
 #ifndef   __STATIC_INLINE
@@ -226,6 +238,7 @@ __packed struct  __iar_u32 { uint32_t v; };
   #endif
 #endif
 
+#undef __WEAK                           /* undo the definition from DLib_Defaults.h */
 #ifndef   __WEAK
   #if __ICCARM_V8
     #define __WEAK __attribute__((weak))
@@ -234,6 +247,43 @@ __packed struct  __iar_u32 { uint32_t v; };
   #endif
 #endif
 
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __iar_program_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              CSTACK$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             CSTACK$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __vector_table
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  @".intvec"
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#ifndef __STACK_SEAL
+#define __STACK_SEAL              STACKSEAL$$Base
+#endif
+
+#ifndef __TZ_STACK_SEAL_SIZE
+#define __TZ_STACK_SEAL_SIZE      8U
+#endif
+
+#ifndef __TZ_STACK_SEAL_VALUE
+#define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL
+#endif
+
+__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
+  *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
+}
+#endif
 
 #ifndef __ICCARM_INTRINSICS_VERSION__
   #define __ICCARM_INTRINSICS_VERSION__  0
@@ -305,7 +355,13 @@ __packed struct  __iar_u32 { uint32_t v; };
 
   #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
   #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
-  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __arm_wsr("CONTROL", control);
+  __iar_builtin_ISB();
+}
+
   #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
   #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
 
@@ -327,7 +383,13 @@ __packed struct  __iar_u32 { uint32_t v; };
   #endif
 
   #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
-  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __arm_wsr("CONTROL_NS", control);
+  __iar_builtin_ISB();
+}
+
   #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
   #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
   #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
@@ -340,8 +402,17 @@ __packed struct  __iar_u32 { uint32_t v; };
   #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
   #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
   #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
-  #define __TZ_get_PSPLIM_NS()        (__arm_rsr("PSPLIM_NS"))
-  #define __TZ_set_PSPLIM_NS(VALUE)   (__arm_wsr("PSPLIM_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
   #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
   #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
 
@@ -558,7 +629,7 @@ __packed struct  __iar_u32 { uint32_t v; };
     __IAR_FT uint32_t __RRX(uint32_t value)
     {
       uint32_t result;
-      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      __ASM volatile("RRX      %0, %1" : "=r"(result) : "r" (value));
       return(result);
     }
 
@@ -640,6 +711,7 @@ __packed struct  __iar_u32 { uint32_t v; };
     __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
     {
       __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+      __iar_builtin_ISB();
     }
 
     __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
@@ -716,12 +788,25 @@ __packed struct  __iar_u32 { uint32_t v; };
     __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
     {
       uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
       __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
       return res;
     }
+
     __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
     {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
       __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
     }
 
     __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
@@ -784,37 +869,37 @@ __packed struct  __iar_u32 { uint32_t v; };
   __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
   {
     uint32_t res;
-    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
     return ((uint8_t)res);
   }
 
   __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
   {
     uint32_t res;
-    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
     return ((uint16_t)res);
   }
 
   __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
   {
     uint32_t res;
-    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
     return res;
   }
 
   __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
   {
-    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+    __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
   }
 
   __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
   {
-    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+    __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
   }
 
   __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
   {
-    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+    __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
   }
 
 #endif /* (__CORTEX_M >= 0x03) */
@@ -826,78 +911,78 @@ __packed struct  __iar_u32 { uint32_t v; };
   __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return ((uint8_t)res);
   }
 
   __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return ((uint16_t)res);
   }
 
   __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return res;
   }
 
   __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
   {
-    __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
   }
 
   __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
   {
-    __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
   }
 
   __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
   {
-    __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
   }
 
   __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return ((uint8_t)res);
   }
 
   __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return ((uint16_t)res);
   }
 
   __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return res;
   }
 
   __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
     return res;
   }
 
   __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
     return res;
   }
 
   __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
     return res;
   }
 
@@ -910,4 +995,8 @@ __packed struct  __iar_u32 { uint32_t v; };
 #pragma diag_default=Pe940
 #pragma diag_default=Pe177
 
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
 #endif /* __CMSIS_ICCARM_H__ */