Remove duplicate PCI exports from ixp4xx machine class.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Convert all uses of kmalloc followed by memset to use kzalloc instead.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Patch from Rod Whitby

PAGE_SHIFT is undeclared in include/asm-arm/arch-ixp4xx/memory.h, identified by the following kernel compilation error:

CC [M] sound/core/memory.o
In file included from include/asm/memory.h:27,
from include/asm/io.h:28,
from sound/core/memory.c:24:
include/asm/arch/memory.h: In function `__arch_adjust_zones':
include/asm/arch/memory.h:28: error: `PAGE_SHIFT' undeclared (first use
in this function)

This patch replaces my previous attempt at fixing this problem (Patch 3214/1) and is based on the following feedback:

Russell King wrote:
> The error you see came up on SA1100.  The best solution was to move
> the __arch_adjust_zones() function out of line.  I suggest ixp4xx
> does the same.

I have moved the function out of line into arch/arm/mach-ixp4xx/common-pci.c as suggested.
Signed-off-by: NRod Whitby <rod@whitby.id.au>
Signed-off-by: NDeepak Saxena <dsaxena@plexity.net>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Patch from Alessandro Zummo

  This patch fixes AHB/PCI endianness problems when the
 processor is in little-endian mode.

 The patch configures the CSR register closely following the directives
 in [1], paragraph 4.1, page 19.

 According to the considerations in [1], page 11, while the AHB bus
 supports both endian modes, on the IXP4XX it always uses big-endian.

 The PCI bus is connected to the South AHB. A wrong setting in the CSR
 register will thus cause a malfunctional PCI bus.

 A schematic diagram of the bus interconnections on the IXP4XX
 can be found in [1], page 18.

 The patch has been verified to work on the NSLU2 in
 both LE and BE modes.

 The author is Peter Korsgaard.

 [1] Intel® IXP4XX Product Line of Network Processors and IXC1100
 Control Plane Processor:
 Understanding Big Endian and Little Endian Modes

 http://www.intel.com/design/network/applnots/25423701.pdfSigned-off-by: NAlessandro Zummo <a.zummo@towertech.it>
Signed-off-by: NDeepak Saxena <dsaxena@plexity.net>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Patch from Deepak Saxena

This patch implements the iomap API for Intel IXP4xx NPU systems.
We need to implement our own version of the API functions b/c of the
PCI hostbridge does not provide the capability to map PCI I/O space
into the CPU's physical memory space. In addition, if a system has
more than 64M of PCI memory mapped BARs, PCI memory must also be
accessed indirectly.  This patch changes the assignment of PCI I/O
resources to fall into to 0x0000:0xffff range so that we can trap
I/O areas in our ioread/iowrite macros.

Signed-off-by: Deepak Saxena
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

pci_dac_set_dma_mask is currently completely unused.
Signed-off-by: NAdrian Bunk <bunk@stusta.de>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!