1. 19 3月, 2011 3 次提交
  2. 17 3月, 2011 31 次提交
  3. 28 2月, 2011 1 次提交
  4. 16 2月, 2011 1 次提交
    • D
      sparc64: Fix NMI startup bug which also breaks perf. · b62818e5
      David S. Miller 提交于
      Doing NMI startup as an early initcall doesn't work because we need
      to have SMP started up by then.
      
      So we'd only NMI startup one cpu, which causes perf PMU grab to
      BUG because the nmi_active count isn't what it's supposed to be.
      
      This also points out that we don't have proper CPU up/down notifiers
      for the NMI code which will need to be fixed at some point.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      b62818e5
  5. 09 2月, 2011 1 次提交
    • A
      sparc: fix size argument to find_next_zero_bit() · 711c71a0
      Akinobu Mita 提交于
      iommu_alloc_ctx() finds a zero bit in iommu->ctx_bitmap.  It starts
      searching from iommu->ctx_lowest_free to the end of the bitmap.
      But the size argument to find_next_zero_bit() in iommu_alloc_ctx()
      is wrong.  It should be the bitmap size, not the maximum size to
      search from the offset argument.
      
      Fortunately iommu->ctx_lowest_free is almost unused and it will not
      be more than 1. So the bug wasted only 1-bit at the end of
      iommu->ctx_bitmap.
      Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com>
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: sparclinux@vger.kernel.org
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      711c71a0
  6. 02 2月, 2011 1 次提交
  7. 31 1月, 2011 1 次提交
  8. 25 1月, 2011 1 次提交
    • T
      percpu: align percpu readmostly subsection to cacheline · 19df0c2f
      Tejun Heo 提交于
      Currently percpu readmostly subsection may share cachelines with other
      percpu subsections which may result in unnecessary cacheline bounce
      and performance degradation.
      
      This patch adds @cacheline parameter to PERCPU() and PERCPU_VADDR()
      linker macros, makes each arch linker scripts specify its cacheline
      size and use it to align percpu subsections.
      
      This is based on Shaohua's x86 only patch.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Cc: Shaohua Li <shaohua.li@intel.com>
      19df0c2f