- 21 5月, 2009 9 次提交
-
-
由 Michael Ellerman 提交于
Don't call __do_IRQ() directly in gatwick_action(), use generic_handle_irq(). Signed-off-by: NMichael Ellerman <michael@ellerman.id.au> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
-
由 Michael Ellerman 提交于
We should no longer have any irq code that needs __do_IRQ(), so remove the fallback to __do_IRQ(). Signed-off-by: NMichael Ellerman <michael@ellerman.id.au> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
-
由 Michael Ellerman 提交于
The guts of do_IRQ() isn't really the right place to be documenting the ppc_md.get_irq() interface. So move the comment into machdep.h Signed-off-by: NMichael Ellerman <michael@ellerman.id.au> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
-
由 Michael Ellerman 提交于
Makes do_IRQ() shorter and clearer. Signed-off-by: NMichael Ellerman <michael@ellerman.id.au> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
-
由 Michael Ellerman 提交于
Rather than a giant ifdef in the body of do_IRQ(), including a dangling else, move the irq stack logic into a separate routine and do the ifdef there. Signed-off-by: NMichael Ellerman <michael@ellerman.id.au> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
-
由 Geoff Levand 提交于
ps3 has 4 ipis per cpu and can use the new smp_request_message_ipi to reduce path length when receiving an ipi. This has the side effect of setting IRQF_PERCPU. Signed-off-by: NMilton Miller <miltonm@bga.com> Acked-by: NGeoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
-
由 Robert Jennings 提交于
Adds support for the "unused" page hint which can be used in shared memory partitions to flag pages not in use, which will then be stolen before active pages by the hypervisor when memory needs to be moved to LPARs in need of additional memory. Failure to mark pages as 'unused' makes the LPAR slower to give up unused memory to other partitions. This adds the kernel parameter 'cmo_free_hint' to disable this functionality. Signed-off-by: NBrian King <brking@linux.vnet.ibm.com> Signed-off-by: NRobert Jennings <rcj@linux.vnet.ibm.com> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
-
由 Tony Breeds 提交于
mpic_find() was overloaded to do two things, finding the mpic instance for a given interrupt and returning if it's an IPI. Instead we introduce mpic_is_ipi() and simplify mpic_find() to just return the mpic instance Also silences the warning: arch/powerpc/sysdev/mpic.c: In function 'mpic_irq_set_priority': arch/powerpc/sysdev/mpic.c:1382: warning: 'is_ipi' may be used uninitialized in this function Signed-off-by: NTony Breeds <tony@bakeyournoodle.com> Acked-by: NMichael Ellerman <michael@ellerman.id.au> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
-
由 Sean MacLennan 提交于
Now that leds-gpio is a proper OF platform driver, the Warp can use the leds-gpio driver rather than the old out-of-kernel driver. One side-effect is the leds-gpio driver always turns the leds off while the old driver left them alone. So we have to set them back to the correct settings. Signed-off-by: NSean MacLennan <smaclennan@pikatech.com> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
-
- 19 5月, 2009 31 次提交
-
-
由 Kumar Gala 提交于
Previouslly we just always set the inbound window to 2G. This was broken for systems with >2G. If a system has >=4G we will need SWIOTLB support to handle that case. We now allocate PCICSRBAR/PEXCSRBAR right below the lowest PCI outbound address for MMIO or the 4G boundary (if the lowest PCI address is above 4G). Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Kumar Gala 提交于
The P2020 is a dual e500v2 core based SOC with: * 3 PCIe controllers * 2 General purpose DMA controllers * 2 sRIO controllers * 3 eTSECS * USB 2.0 * SDHC * SPI, I2C, DUART * enhanced localbus * and optional Security (P2020E) security w/XOR acceleration The p2020 DS reference board is pretty similar to the existing MPC85xx DS boards and has a ULI 1575 connected on one of the PCIe controllers. Signed-off-by: NTed Peters <Ted.Peters@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Kumar Gala 提交于
Updated the binding spec to use "fsl,eshdc" as the base compatible rather than the first chip in the family. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Li Yang 提交于
Signed-off-by: NLi Yang <leoli@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Li Yang 提交于
Instead of fixed address in old code. Signed-off-by: NLi Yang <leoli@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Kumar Gala 提交于
We we build with resource_size_t as a 64-bit quantity we get: arch/powerpc/sysdev/fsl_rio.c: In function 'fsl_rio_setup': arch/powerpc/sysdev/fsl_rio.c:1029: warning: format '%08x' expects type 'unsigned int', but argument 4 has type 'resource_size_t' arch/powerpc/sysdev/fsl_rio.c:1029: warning: format '%08x' expects type 'unsigned int', but argument 5 has type 'resource_size_t' Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Kumar Gala 提交于
In these configuration we expect to have large amounts of memory (> 4G) and thus will bounce via swiotlb some region of PCI address space. The outbound windows were wasting 512M of address space by leaving a gap between the top of the outbound window and the 4G boundary. By moving the top of the outbound window up to the 4G boundary we can reclaim the vast majority of the 512M (minus space needed for PEXCSRBAR) and thus reduces the amount of memory we have to bounce. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Kumar Gala 提交于
Its feasible based on how the PCI address map is setup that the region of PCI address space used for MSIs differs for each PHB on the same SoC. Instead of assuming that the address mappes to CCSRBAR 1:1 we read PEXCSRBAR (BAR0) for the PHB that the given pci_dev is on. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Kumar Gala 提交于
The MPC8568/9 chips support MSIs on PCIe so no reason not to enable them. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Kumar Gala 提交于
We we build with dma_addr_t as a 64-bit quantity we get: drivers/dma/fsldma.c: In function 'fsl_chan_xfer_ld_queue': drivers/dma/fsldma.c:625: warning: cast to pointer from integer of different size drivers/dma/fsldma.c: In function 'fsl_dma_chan_do_interrupt': drivers/dma/fsldma.c:737: warning: cast to pointer from integer of different size drivers/dma/fsldma.c:737: warning: cast to pointer from integer of different size drivers/dma/fsldma.c: In function 'of_fsl_dma_probe': drivers/dma/fsldma.c:927: warning: cast to pointer from integer of different Signed-off-by: NKumar Gala <galak@kernel.crashing.org> Acked-by: NDan Williams <dan.j.williams@intel.com>
-
由 Anton Vorontsov 提交于
For serial flash support we need to: - Add QE Par IO Bank E device tree node, a GPIO from this bank is used for SPI chip-select line; - Add serial-flash node; - Add proper module alias into of/base.c. Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Anton Vorontsov 提交于
Select HAS_RAPIDIO symbol and add rio nodes for MPC8568E-MDS and MPC8569E-MDS boards. Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Anton Vorontsov 提交于
Note that eSDHC and DUART0 are mutually exclusive on MPC8569E-MDS boards. Default option is DUART0, so eSDHC is disabled by default. U-Boot will fixup device tree if eSDHC should be used instead of DUART0. Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Anton Vorontsov 提交于
This patch fixes bogus reg = <> property in the localbus node, and fixes interrupt property (should be "interrupts"). Also add node for NAND support. Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Anton Vorontsov 提交于
fsl,exec-units-mask should be 0xbfe to include SNOW unit in MPC8569E's security engine. Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Anton Vorontsov 提交于
This patch adds PCI IDs for MPC8569 and MPC8569E processors, plus adds appropriate quirks for these IDs, and thus makes PCI-E actually work on MPC8569E-MDS boards. Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Kumar Gala 提交于
Between the addition of the ecm/mcm law nodes and the fact that the get_immrbase() has been using the range property of the SoC to determine the base address of CCSR space we no longer need the reg property at the soc node level. It has been ill specified and varied between device trees to cover either the {e,m}cm-law node, some odd subset of CCSR space or all of CCSR space. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Haiying Wang 提交于
Add fsl,qe-num-riscs and fsl,qe-num-snums to all the devices trees which have qe node. Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Haiying Wang 提交于
The MPC8569 is similiar to the MPC8568. It doubles the number of QUICC Engine RISC cores from 2 to 4. Removes eTSECs, TLU and adds the eSDHC controller. Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Haiying Wang 提交于
In the case the QE has 46 SNUMs for the threads to support four UCC Ethernet at 1000Base-T simultaneously. Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com> Acked-by: NDavid S. Miller <davem@davemloft.net> Acked-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Haiying Wang 提交于
The latest QE chip may have more Serial Number(SNUM)s of thread to use. We will get the number of SNUMs from device tree by reading the new property "fsl,qe-num-snums", and set 28 as the default number of SNUMs so that it is compatible with the old QE chips' device trees which don't have this new property. The macro QE_NUM_OF_SNUM is defined as the maximum number in QE snum table which is 256. Also we update the snum_init[] array with 18 more new SNUMs which are confirmed to be useful on new chip. Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com> Acked-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Haiying Wang 提交于
Change the definition of riscTx and riscRx to unsigned integer instead of enum, and change their values to support 4 risc allocation if the qe has 4 RISC engines. Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com> Acked-by: NDavid S. Miller <davem@davemloft.net> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Haiying Wang 提交于
Change the RISC allocation to macros instead of enum, add function to read the number of risc engines from the new property "fsl,qe-num-riscs" under the qe node in dts. Add new property "fsl,qe-num-riscs" description in qe.txt Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com> Acked-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Haiying Wang 提交于
Keep an unique machine def for the MPC8568 MDS board to handle some subtle differences between the future MDS board. Also set the bcsrs in setup_arch() only for mpc8568_mds because other mds has different bcsr settings. Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Kumar Gala 提交于
Removed the need for asm/mpc86xx.h as it was only used in mpc86xx_smp.c and just moved the defines it cared about into there. Also fixed up the ioremap to only map the one 4k page we need access to and to iounmap when we are done. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Kumar Gala 提交于
Kill of some old defines and macros that we no longer use like CPM_MAP_ADDR and CPM_IRQ_OFFSET. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Becky Bruce 提交于
Also, convert them to resource_size_t (which is unsigned long on 64-bit, so it's not a change there). We will be using these on fsl 32b to indicate the start and size address of memory that the pci controller can actually reach - this is needed to determine if an address requires bounce buffering. For now, initialize them to a standard value; in the near future, the value will be calculated based on how the inbound windows are programmed. Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org> Acked-by: NBen Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Kumar Gala 提交于
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Kumar Gala 提交于
The first 4k region of CCSR space is well defined for local access windows, CCSRBAR, etc. The second 4k region is well defined as register for configuring and getting errors for the MPX coherency module. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Kumar Gala 提交于
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Kumar Gala 提交于
The first 4k region of CCSR space is well defined for local access windows, CCSRBAR, etc. The second 4k region is well defined as register for configuring and getting errors for the ECM coherency module. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-