1. 29 11月, 2010 12 次提交
  2. 28 11月, 2010 2 次提交
  3. 25 11月, 2010 8 次提交
  4. 24 11月, 2010 1 次提交
  5. 23 11月, 2010 7 次提交
    • C
      carl9170: fix virtual interface setup crash · b397492a
      Christian Lamparter 提交于
      This patch fixes a faulty bound check which caused a
      crash when too many virtual interface were brought up.
      
      BUG: unable to handle kernel NULL pointer dereference at 00000004
      IP: [<f8125f67>] carl9170_op_add_interface+0x1d7/0x2c0 [carl9170]
      *pde = 00000000
      Oops: 0002 [#1] PREEMPT
      Modules linked in: carl9170 [...]
      Pid: 4720, comm: wpa_supplicant Not tainted 2.6.37-rc2-wl+
      EIP: 0060:[<f8125f67>] EFLAGS: 00210206 CPU: 0
      EIP is at carl9170_op_add_interface+0x1d7/0x2c0 [carl9170]
      EAX: 00000000 ...
      Process wpa_supplicant
      Stack:
       f4f88f34 fffffff4 ..
      Call Trace:
       [<f8f4e666>] ? ieee80211_do_open+0x406/0x5c0 [mac80211]
       [...]
      Code: <89> 42 04 ...
      EIP: [<f8125f67>] carl9170_op_add_interface+0x1d7/0x2c0 [carl9170]
      CR2: 0000000000000004
      Signed-off-by: NChristian Lamparter <chunkeey@googlemail.com>
      Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
      b397492a
    • D
      ssb: b43-pci-bridge: Add new vendor for BCM4318 · 1d8638d4
      Daniel Klaffenbach 提交于
      Add new vendor for Broadcom 4318.
      Signed-off-by: NDaniel Klaffenbach <danielklaffenbach@gmail.com>
      Signed-off-by: NLarry Finger <Larry.Finger@lwfinger.net>
      Cc: Stable <stable@kernel.org>
      Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
      1d8638d4
    • F
      ath9k: fix timeout on stopping rx dma · d47844a0
      Felix Fietkau 提交于
      It seems that using ath9k_hw_stoppcurecv to stop rx dma is not enough.
      When it's time to stop DMA, the PCU is still busy, so the rx enable
      bit never clears.
      Using ath9k_hw_abortpcurecv helps with getting rx stopped much faster,
      with this change, I cannot reproduce the rx stop related WARN_ON anymore.
      Signed-off-by: NFelix Fietkau <nbd@openwrt.org>
      Cc: stable@kernel.org
      Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
      d47844a0
    • D
      of/phylib: Use device tree properties to initialize Marvell PHYs. · cf41a51d
      David Daney 提交于
      Some aspects of PHY initialization are board dependent, things like
      indicator LED connections and some clocking modes cannot be determined
      by probing.  The dev_flags element of struct phy_device can be used to
      control these things if an appropriate value can be passed from the
      Ethernet driver.  We run into problems however if the PHY connections
      are specified by the device tree.  There is no way for the Ethernet
      driver to know what flags it should pass.
      
      If we are using the device tree, the struct phy_device will be
      populated with the device tree node corresponding to the PHY, and we
      can extract extra configuration information from there.
      
      The next question is what should the format of that information be?
      It is highly device specific, and the device tree representation
      should not be tied to any arbitrary kernel defined constants.  A
      straight forward representation is just to specify the exact bits that
      should be set using the "marvell,reg-init" property:
      
            phy5: ethernet-phy@5 {
              reg = <5>;
              compatible = "marvell,88e1149r";
              marvell,reg-init =
                      /* led[0]:1000, led[1]:100, led[2]:10, led[3]:tx */
                      <3 0x10 0 0x5777>, /* Reg 3,16 <- 0x5777 */
                      /* mix %:0, led[0123]:drive low off hiZ */
                      <3 0x11 0 0x00aa>, /* Reg 3,17 <- 0x00aa */
                      /* default blink periods. */
                      <3 0x12 0 0x4105>, /* Reg 3,18 <- 0x4105 */
                      /* led[4]:rx, led[5]:dplx, led[45]:drive low off hiZ */
                      <3 0x13 0 0x0a60>; /* Reg 3,19 <- 0x0a60 */
            };
      
            phy6: ethernet-phy@6 {
              reg = <6>;
              compatible = "marvell,88e1118";
              marvell,reg-init =
                      /* Fix rx and tx clock transition timing */
                      <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
                      /* Adjust LED drive. */
                      <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
                      /* irq, blink-activity, blink-link */
                      <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
            };
      
      The Marvell PHYs have a page select register at register 22 (0x16), we
      can specify any register by its page and register number.  These are
      the first and second word.  The third word contains a mask to be ANDed
      with the existing register value, and the fourth word is ORed with the
      result to yield the new register value.  The new marvell_of_reg_init
      function leaves the page select register unchanged, so a call to it
      can be dropped into the .config_init functions without unduly
      affecting the state of the PHY.
      
      If CONFIG_OF_MDIO is not set, there is no of_node, or no
      "marvell,reg-init" property, the PHY initialization is unchanged.
      Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
      Cc: Grant Likely <grant.likely@secretlab.ca>
      Cc: Cyril Chemparathy <cyril@ti.com>
      Cc: David Daney <ddaney@caviumnetworks.com>
      Cc: Arnaud Patard <arnaud.patard@rtp-net.org>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Reviewed-by: NGrant Likely <grant.likely@secretlab.ca>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      cf41a51d
    • D
      phylib: Add support for Marvell 88E1149R devices. · 90600732
      David Daney 提交于
      The 88E1149R is 10/100/1000 quad-gigabit Ethernet PHY.  The
      .config_aneg function can be shared with 88E1118, but it needs its own
      .config_init.
      Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
      Cc: Cyril Chemparathy <cyril@ti.com>
      Cc: Arnaud Patard <arnaud.patard@rtp-net.org>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Wolfram Sang <w.sang@pengutronix.de>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      90600732
    • D
      phylib: Use common page register definition for Marvell PHYs. · 27d916d6
      David Daney 提交于
      The definition of the Marvell PHY page register is not specific to
      88E1121, so rename the macro to MII_MARVELL_PHY_PAGE, and use it
      throughout.
      Suggested-by: NCyril Chemparathy <cyril@ti.com>
      Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
      Cc: Cyril Chemparathy <cyril@ti.com>
      Cc: Arnaud Patard <arnaud.patard@rtp-net.org>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      27d916d6
    • S
      qlge: Fix incorrect usage of module parameters and netdev msg level · 84cf7029
      Sonny Rao 提交于
      Driver appears to be mistaking the permission field with default value
      in the case of debug and qlge_irq_type.
      
      Driver is also passing debug as a bitmask into netif_msg_init()
      which wants a number of bits.  Ron Mercer suggests we should
      change this to pass in -1 so the defaults get used instead,
      which makes the default much less verbose.
      Signed-off-by: NMilton Miller <miltonm@bga.com>
      Signed-off-by: NSonny Rao <sonnyrao@linux.vnet.ibm.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      84cf7029
  6. 22 11月, 2010 6 次提交
  7. 20 11月, 2010 2 次提交
  8. 19 11月, 2010 2 次提交