- 18 4月, 2008 15 次提交
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由 Tejun Heo 提交于
SError used to be cleared in ->postreset. This has small hotplug race condition. If a device is plugged in after reset is complete but postreset hasn't run yet, its hotplug event gets lost when SError is cleared. This patch makes sata_link_resume() clear SError. This kills the race condition and makes a lot of sense as some PMP and host PHYs don't work properly without SError cleared. This change makes sata_pmp_std_{pre|post}_reset()'s unnecessary as they become identical to ata_std counterparts. It also simplifies sata_pmp_hardreset() and ahci_vt8251_hardreset(). Signed-off-by: NTejun Heo <htejun@gmail.com>
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由 Tejun Heo 提交于
sata_sff_hardreset() contains link readiness wait logic which isn't SFF specific. Move that part into sata_link_hardreset(), which now takes two more parameters - @online and @check_ready. Both are optional. The former is out parameter for link onlineness after reset. The latter is used to wait for link readiness after hardreset. Users of sata_link_hardreset() is updated to use new funtionality and ahci_hardreset() is updated to use sata_link_hardreset() instead of sata_sff_hardreset(). This doesn't really cause any behavior change. Signed-off-by: NTejun Heo <htejun@gmail.com>
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由 Tejun Heo 提交于
Implement ahci_check_ready() and replace ata_sff_wait_after_reset() with ata_wait_after_reset(). As ahci was faking TF access, this change doesn't result in any functional difference. Signed-off-by: NTejun Heo <htejun@gmail.com>
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由 Tejun Heo 提交于
Previously, post-softreset readiness is waited as follows. 1. ata_sff_wait_after_reset() waits for 150ms and then for ATA_TMOUT_FF_WAIT if status is 0xff and other conditions meet. 2. ata_bus_softreset() finishes with -ENODEV if status is still 0xff. If not, continue to #3. 3. ata_bus_post_reset() waits readiness of dev0 and/or dev1 depending on devmask using ata_sff_wait_ready(). And for post-hardreset readiness, 1. ata_sff_wait_after_reset() waits for 150ms and then for ATA_TMOUT_FF_WAIT if status is 0xff and other conditions meet. 2. sata_sff_hardreset waits for device readiness using ata_sff_wait_ready(). This patch merges and unifies post-reset readiness waits into ata_sff_wait_ready() and ata_sff_wait_after_reset(). ATA_TMOUT_FF_WAIT handling is merged into ata_sff_wait_ready(). If TF status is 0xff, link status is unknown and the port is SATA, it will continue polling till ATA_TMOUT_FF_WAIT. ata_sff_wait_after_reset() is updated to perform the following steps. 1. waits for 150ms. 2. waits for dev0 readiness using ata_sff_wait_ready(). Note that this is done regardless of devmask, as ata_sff_wait_ready() handles 0xff status correctly, this preserves the original behavior except that it may wait longer after softreset if link is online but status is 0xff. This behavior change is very unlikely to cause any actual difference and is intended. It brings softreset behavior to that of hardreset. 3. waits for dev1 readiness just the same way ata_bus_post_reset() did. Now both soft and hard resets call ata_sff_wait_after_reset() after reset to wait for readiness after resets. As ata_sff_wait_after_reset() contains calls to ->sff_dev_select(), explicit call near the end of sata_sff_hardreset() is removed. This change makes reset implementation simpler and more consistent. While at it, make the magical 150ms wait post-reset wait duration a constant and ata_sff_wait_ready() and ata_sff_wait_after_reset() take @link instead of @ap. This is to make them consistent with other reset helpers and ease core changes. pata_scc is updated accordingly. Signed-off-by: NTejun Heo <htejun@gmail.com>
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由 Tejun Heo 提交于
Separate out generic ATA portion from ata_sff_postreset() into ata_std_postreset() and implement ata_sff_postreset() using the std version. ata_base_port_ops now has ata_std_postreset() for its postreset and ata_sff_port_ops overrides it to ata_sff_postreset(). This change affects pdc_adma, ahci, sata_fsl and sata_sil24. pdc_adma now specifies postreset to ata_sff_postreset() explicitly. sata_fsl and sata_sil24 now use ata_std_postreset() which makes no difference to them. ahci now calls ata_std_postreset() from its own postreset method, which causes no behavior difference. Signed-off-by: NTejun Heo <htejun@gmail.com>
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由 Tejun Heo 提交于
Add sff_ prefix to SFF specific port ops. This rename is in preparation of separating SFF support out of libata core layer. This patch strictly renames ops and doesn't introduce any behavior difference. Signed-off-by: NTejun Heo <htejun@gmail.com>
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由 Tejun Heo 提交于
SFF functions have confusing names. Some have sff prefix, some have bmdma, some std, some pci and some none. Unify the naming by... * SFF functions which are common to both BMDMA and non-BMDMA are prefixed with ata_sff_. * SFF functions which are specific to BMDMA are prefixed with ata_bmdma_. * SFF functions which are specific to PCI but apply to both BMDMA and non-BMDMA are prefixed with ata_pci_sff_. * SFF functions which are specific to PCI and BMDMA are prefixed with ata_pci_bmdma_. * Drop generic prefixes from LLD specific routines. For example, bfin_std_dev_select -> bfin_dev_select. The following renames are noteworthy. ata_qc_issue_prot() -> ata_sff_qc_issue() ata_pci_default_filter() -> ata_bmdma_mode_filter() ata_dev_try_classify() -> ata_sff_dev_classify() This rename is in preparation of separating SFF support out of libata core layer. This patch strictly renames functions and doesn't introduce any behavior difference. Signed-off-by: NTejun Heo <htejun@gmail.com>
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由 Tejun Heo 提交于
Currently reset methods are not specified directly in the ata_port_operations table. If a LLD wants to use custom reset methods, it should construct and use a error_handler which uses those reset methods. It's done this way for two reasons. First, the ops table already contained too many methods and adding four more of them would noticeably increase the amount of necessary boilerplate code all over low level drivers. Second, as ->error_handler uses those reset methods, it can get confusing. ie. By overriding ->error_handler, those reset ops can be made useless making layering a bit hazy. Now that ops table uses inheritance, the first problem doesn't exist anymore. The second isn't completely solved but is relieved by providing default values - most drivers can just override what it has implemented and don't have to concern itself about higher level callbacks. In fact, there currently is no driver which actually modifies error handling behavior. Drivers which override ->error_handler just wraps the standard error handler only to prepare the controller for EH. I don't think making ops layering strict has any noticeable benefit. This patch makes ->prereset, ->softreset, ->hardreset, ->postreset and their PMP counterparts propoer ops. Default ops are provided in the base ops tables and drivers are converted to override individual reset methods instead of creating custom error_handler. * ata_std_error_handler() doesn't use sata_std_hardreset() if SCRs aren't accessible. sata_promise doesn't need to use separate error_handlers for PATA and SATA anymore. * softreset is broken for sata_inic162x and sata_sx4. As libata now always prefers hardreset, this doesn't really matter but the ops are forced to NULL using ATA_OP_NULL for documentation purpose. * pata_hpt374 needs to use different prereset for the first and second PCI functions. This used to be done by branching from hpt374_error_handler(). The proper way to do this is to use separate ops and port_info tables for each function. Converted. Signed-off-by: NTejun Heo <htejun@gmail.com>
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由 Tejun Heo 提交于
libata lets low level drivers build ata_port_operations table and register it with libata core layer. This allows low level drivers high level of flexibility but also burdens them with lots of boilerplate entries. This becomes worse for drivers which support related similar controllers which differ slightly. They share most of the operations except for a few. However, the driver still needs to list all operations for each variant. This results in large number of duplicate entries, which is not only inefficient but also error-prone as it becomes very difficult to tell what the actual differences are. This duplicate boilerplates all over the low level drivers also make updating the core layer exteremely difficult and error-prone. When compounded with multi-branched development model, it ends up accumulating inconsistencies over time. Some of those inconsistencies cause immediate problems and fixed. Others just remain there dormant making maintenance increasingly difficult. To rectify the problem, this patch implements ata_port_operations inheritance. To allow LLDs to easily re-use their own ops tables overriding only specific methods, this patch implements poor man's class inheritance. An ops table has ->inherits field which can be set to any ops table as long as it doesn't create a loop. When the host is started, the inheritance chain is followed and any operation which isn't specified is taken from the nearest ancestor which has it specified. This operation is called finalization and done only once per an ops table and the LLD doesn't have to do anything special about it other than making the ops table non-const such that libata can update it. libata provides four base ops tables lower drivers can inherit from - base, sata, pmp, sff and bmdma. To avoid overriding these ops accidentaly, these ops are declared const and LLDs should always inherit these instead of using them directly. After finalization, all the ops table are identical before and after the patch except for setting .irq_handler to ata_interrupt in drivers which didn't use to. The .irq_handler doesn't have any actual effect and the field will soon be removed by later patch. * sata_sx4 is still using old style EH and currently doesn't take advantage of ops inheritance. Signed-off-by: NTejun Heo <htejun@gmail.com>
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由 Tejun Heo 提交于
libata lets low level drivers build scsi_host_template and register it to the SCSI layer. This allows low level drivers high level of flexibility but also burdens them with lots of boilerplate entries. This patch implements SHT initializers which can be used to initialize all the boilerplate entries in a sht. Three variants of them are implemented - BASE, BMDMA and NCQ - for different types of drivers. Note that entries can be overriden by putting individual initializers after the helper macro. All sht tables are identical before and after this patch. Signed-off-by: NTejun Heo <htejun@gmail.com>
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由 Tejun Heo 提交于
Over the time, port info, ops and sht structures developed quite a bit of inconsistencies. This patch updates drivers. * Enable/disable_pm callbacks added to all ahci ops tables. * Every driver for SFF controllers now uses ata_sff_port_start() instead of ata_port_start() unless the driver has custom implementation. * Every driver for SFF controllers now uses ata_pci_default_filter() unless the driver has custom implementation. * Removed an odd port_info->sht initialization from ata_piix.c. Likely a merge byproduct. * A port which has ATA_FLAG_SATA set doesn't need to set cable_detect to ata_cable_sata(). Remove it from via and mv port ops. * Some drivers had unnecessary .max_sectors initialization which is ignored and was missing .slave_destroy callback. Fixed. * Removed unnecessary sht initializations port_info's. * Removed onsolete scsi device suspend/resume callbacks from pata_bf54x. * No reason to set ata_pci_default_filter() and bmdma functions for PIO-only drivers. Remove those callbacks and replace ata_bmdma_irq_clear with ata_noop_irq_clear. * pata_platform sets port_start to ata_dummy_ret0. port_start can just be set to NULL. * sata_fsl supports NCQ but was missing qc_defer. Fixed. * pata_rb600_cf implements dummy port_start. Removed. Signed-off-by: NTejun Heo <htejun@gmail.com>
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由 Tejun Heo 提交于
->irq_clear() is used to clear IRQ bit of a SFF controller and isn't useful for drivers which don't use libata SFF HSM implementation. However, it's a required callback and many drivers implement their own noop version as placeholder. This patch implements ata_noop_irq_clear and use it to replace those custom placeholders. Also, SFF drivers which don't support BMDMA don't need to use ata_bmdma_irq_clear(). It becomes noop if BMDMA address isn't initialized. Convert them to use ata_noop_irq_clear(). Signed-off-by: NTejun Heo <htejun@gmail.com>
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由 Tejun Heo 提交于
Some controllers can't reliably record the initial D2H FIS after SATA link is brought online for whatever reason. Advanced controllers which don't have traditional TF register based interface often have this problem as they don't really have the TF registers to update while the controller and link are being initialized. SKIP_D2H_BSY works around the problem by skipping the wait for device readiness before issuing SRST, so for such controllers libata issues SRST blindly and hopes for the best. Now that libata defaults to hardreset, this workaround is no longer necessary. For controllers which have support for hardreset, SRST is never issued by itself. It is only issued as follow-up SRST for device classification and PMP initialization, so there's no need to wait for it from prereset. Kill ATA_LFLAG_SKIP_D2H_BSY. Signed-off-by: NTejun Heo <htejun@gmail.com>
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由 Tejun Heo 提交于
Now that hardreset is the preferred method of resetting, there's no need for ATA_LFLAG_HRST_TO_RESUME flag. Kill it. Signed-off-by: NTejun Heo <htejun@gmail.com>
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由 Tejun Heo 提交于
When both soft and hard resets are available, libata preferred softreset till now. The logic behind it was to be softer to devices; however, this doesn't really help much. Rationales for the change: * BIOS may freeze lock certain things during boot and softreset can't unlock those. This by itself is okay but during operation PHY event or other error conditions can trigger hardreset and the device may end up with different configuration. For example, after a hardreset, previously unlockable HPA can be unlocked resulting in different device size and thus revalidation failure. Similar condition can occur during or after resume. * Certain ATAPI devices require hardreset to recover after certain error conditions. On PATA, this is done by issuing the DEVICE RESET command. On SATA, COMRESET has equivalent effect. The problem is that DEVICE RESET needs its own execution protocol. For SFF controllers with bare TF access, it can be easily implemented but more advanced controllers (e.g. ahci and sata_sil24) require specialized implementations. Simply using hardreset solves the problem nicely. * COMRESET initialization sequence is the norm in SATA land and many SATA devices don't work properly if only SRST is used. For example, some PMPs behave this way and libata works around by always issuing hardreset if the host supports PMP. Like the above example, libata has developed a number of mechanisms aiming to promote softreset to hardreset if softreset is not going to work. This approach is time consuming and error prone. Also, note that, dependingon how you read the specs, it could be argued that PMP fan-out ports require COMRESET to start operation. In fact, all the PMPs on the market except one don't work properly if COMRESET is not issued to fan-out ports after PMP reset. * COMRESET is an integral part of SATA connection and any working device should be able to handle COMRESET properly. After all, it's the way to signal hardreset during reboot. This is the most used and recommended (at least by the ahci spec) method of resetting devices. So, this patch makes libata prefer hardreset over softreset by making the following changes. * Rename ATA_EH_RESET_MASK to ATA_EH_RESET and use it whereever ATA_EH_{SOFT|HARD}RESET used to be used. ATA_EH_{SOFT|HARD}RESET is now only used to tell prereset whether soft or hard reset will be issued. * Strip out now unneeded promote-to-hardreset logics from ata_eh_reset(), ata_std_prereset(), sata_pmp_std_prereset() and other places. Signed-off-by: NTejun Heo <htejun@gmail.com>
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- 25 3月, 2008 1 次提交
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由 Jeff Garzik 提交于
At least one report claims that a878539e failed to solve lockups, whereas the old limit-to-32-bit trick worked. Restore the 32-bit limit, but also leave the 255-sector limit in place, because we know that's needed as well. Signed-off-by: NJeff Garzik <jgarzik@redhat.com>
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- 17 3月, 2008 3 次提交
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由 Jose Alberto Reguero 提交于
Signed-off-by: NJose Alberto Reguero <jareguero@telefonica.net> Signed-off-by: NJeff Garzik <jeff@garzik.org>
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由 Tejun Heo 提交于
Under certain circumstances (SSP turned off by the BIOS) and for debugging purposes, skipping global controller reset is helpful. Add a kernel parameter for it. Signed-off-by: NTejun Heo <htejun@gmail.com> Signed-off-by: NJeff Garzik <jeff@garzik.org>
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由 Tejun Heo 提交于
ahci is often implemented with accompanying SFF compatible interface and legacy IDE driver may attach to the legacy IO ports when the controller is already claimed by ahci and vice-versa. This patch makes ahci use pcim_iomap_regions_request_all() so that all IO regions are claimed on attach. Signed-off-by: NTejun Heo <htejun@gmail.com> Signed-off-by: NJeff Garzik <jeff@garzik.org>
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- 11 3月, 2008 2 次提交
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由 Roel Kluin 提交于
logical-bitwise & confusion Signed-off-by: NRoel Kluin <12o3l@tiscali.nl> Signed-off-by: NJeff Garzik <jeff@garzik.org>
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由 peerchen 提交于
Signed-off-by: NPeer Chen <peerchen@gmail.com> Signed-off-by: NJeff Garzik <jeff@garzik.org>
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- 05 3月, 2008 1 次提交
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由 Jeff Garzik 提交于
This addresses the recent ATI SB600 errata, where the hardware does not like 256-length PRD entries during FPDMA (aka NCQ). It hurts performance on SB600, but it is more important to get a correct patch eliminating the data corruption/lockups, and then later on tune for performance. We simply limit each command to a maximum of 255 sectors, on SB600. Signed-off-by: NJeff Garzik <jgarzik@redhat.com>
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- 24 2月, 2008 2 次提交
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由 Shane Huang 提交于
SB700 SATA controller can support 64 bit DMA, the previous commit badc2341 was added with careless reference to SB600, which should be modified by this patch. Signed-off-by: NShane Huang <shane.huang@amd.com> Signed-off-by: NJeff Garzik <jeff@garzik.org>
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由 Rafael J. Wysocki 提交于
During the last step of hibernation in the "platform" mode (with the help of ACPI) we use the suspend code, including the devices' ->suspend() methods, to prepare the system for entering the ACPI S4 system sleep state. But at least for some devices the operations performed by the ->suspend() callback in that case must be different from its operations during regular suspend. For this reason, introduce the new PM event type PM_EVENT_HIBERNATE and pass it to the device drivers' ->suspend() methods during the last phase of hibernation, so that they can distinguish this case and handle it as appropriate. Modify the drivers that handle PM_EVENT_SUSPEND in a special way and need to handle PM_EVENT_HIBERNATE in the same way. These changes are necessary to fix a hibernation regression related to the i915 driver (ref. http://lkml.org/lkml/2008/2/22/488). Signed-off-by: NRafael J. Wysocki <rjw@sisk.pl> Acked-by: NPavel Machek <pavel@ucw.cz> Tested-by: NJeff Chua <jeff.chua.linux@gmail.com> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 19 2月, 2008 1 次提交
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由 James Bottomley 提交于
that provided by the block layer ATA requires that all DMA transfers begin and end on word boundaries. Because of this, a large amount of machinery grew up in ide to adjust scatterlists on this basis. However, as of 2.5, the block layer has a dma_alignment variable which ensures both the beginning and length of a DMA transfer are aligned on the dma_alignment boundary. Although the block layer does adjust the beginning of the transfer to ensure this happens, it doesn't actually adjust the length, it merely makes sure that space is allocated for transfers beyond the declared length. The upshot of this is that scatterlists may be padded to any size between the actual length and the length adjusted to the dma_alignment safely knowing that memory is allocated in this region. Right at the moment, SCSI takes the default dma_aligment which is on a 512 byte boundary. Note that this aligment only applies to transfers coming in from user space. However, since all kernel allocations are automatically aligned on a minimum of 32 byte boundaries, it is safe to adjust them in this manner as well. tj: * Adjusting sg after padding is done in block layer. Make libata set queue alignment correctly for ATAPI devices and drop broken sg mangling from ata_sg_setup(). * Use request->raw_data_len for ATAPI transfer chunk size. * Killed qc->raw_nbytes. * Separated out killing qc->n_iter. Signed-off-by: NJames Bottomley <James.Bottomley@HansenPartnership.com> Signed-off-by: NTejun Heo <htejun@gmail.com> Signed-off-by: NJens Axboe <jens.axboe@oracle.com>
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- 06 2月, 2008 1 次提交
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由 Tejun Heo 提交于
AHCI uses CAP.NP to indicate the number of ports and PI to tell which ports are enabled. The only requirement is that the number of ports indicated by CAP.NP should equal or be higher than the number of enabled ports in PI. CAP.NP and PI carry duplicate information and there have been some interesting cases. Some early AHCI controllers didn't set PI at all and just implement from port 0 to CAP.NP. An ICH8 board which wired four out of six available ports had 3 (4 ports) for CAP.NP and 0x33 for PI. While ESB2 has less bits set in PI than the value in CAP.NP. Till now, ahci driver assumed that PI is invalid if it doesn't match CAP.NP exactly. This violates AHCI standard and the driver ends up accessing unmimplemented ports on ESB2. This patch updates CAP.NP and PI handling such that PI can have less number of bits set than indicated in CAP.NP and the highest port is determined as the maximum port of what CAP.NP and PI indicate. Signed-off-by: NTejun Heo <htejun@gmail.com> Cc: Jan Beulich <jbeulich@novell.com> Signed-off-by: NJeff Garzik <jeff@garzik.org>
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- 02 2月, 2008 1 次提交
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由 Jason Gaston 提交于
This patch adds the Intel ICH10 SATA RAID Controllers DeviceID's. Signed-off-by: NJason Gaston <jason.d.gaston@intel.com> Signed-off-by: NJeff Garzik <jeff@garzik.org>
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- 23 1月, 2008 5 次提交
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由 Tejun Heo 提交于
Factor out AHCI enabling into ahci_enable_ahci() and enabling AHCI before reading CAP in ahci_save_initial_config() as the spec requires enabling AHCI mode before accessing any other registers. Signed-off-by: NTejun Heo <htejun@gmail.com> Signed-off-by: NJeff Garzik <jeff@garzik.org>
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由 Al Viro 提交于
Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk> Signed-off-by: NJeff Garzik <jeff@garzik.org>
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由 Tejun Heo 提交于
libata used private sg iterator to handle padding sg. Now that sg can be chained, padding can be handled using standard sg ops. Convert to chained sg. * s/qc->__sg/qc->sg/ * s/qc->pad_sgent/qc->extra_sg[]/. Because chaining consumes one sg entry. There need to be two extra sg entries. The renaming is also for future addition of other extra sg entries. * Padding setup is moved into ata_sg_setup_extra() which is organized in a way that future addition of other extra sg entries is easy. * qc->orig_n_elem is unused and removed. * qc->n_elem now contains the number of sg entries that LLDs should map. qc->mapped_n_elem is added to carry the original number of mapped sgs for unmapping. * The last sg of the original sg list is used to chain to extra sg list. The original last sg is pointed to by qc->last_sg and the content is stored in qc->saved_last_sg. It's restored during ata_sg_clean(). * All sg walking code has been updated. Unnecessary assertions and checks for conditions the core layer already guarantees are removed. Signed-off-by: NTejun Heo <htejun@gmail.com> Cc: Jens Axboe <jens.axboe@oracle.com> Signed-off-by: NJeff Garzik <jeff@garzik.org>
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由 Tejun Heo 提交于
Implement protocol tests - ata_is_atapi(), ata_is_nodata(), ata_is_pio(), ata_is_dma(), ata_is_ncq() and ata_is_data() and use them to replace is_atapi_taskfile() and hard coded protocol tests. Signed-off-by: NTejun Heo <htejun@gmail.com> Signed-off-by: NJeff Garzik <jeff@garzik.org>
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由 Tejun Heo 提交于
For intel ones, ahci unconditionally OR'd 0xf to PCS. This isn't correct for the following cases. * ich6/7m's which only implement P0 and P2 (0xf works fine tho) * ich8/9's which have six ports and needs 0x3f to enable all ports This patch updates PCS programming such that... * port_map determined by ahci_save_initial_config() is OR'd instead of 0xf * PCS is updated only if necessary (there are turned off enable bits) port_map is determined from PORTS_IMPL PCI register which is implemented as write or write-once register. If the register isn't programmed, ahci automatically generates it from number of ports, which is good enough for PCS programming. ICH6/7M are probably the only ones where non-contiguous enable bits are necessary && PORTS_IMPL isn't programmed properly but they're proven to work reliably with 0xf anyway. Signed-off-by: NTejun Heo <htejun@gmail.com> Signed-off-by: NJeff Garzik <jeff@garzik.org>
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- 08 12月, 2007 3 次提交
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由 Tejun Heo 提交于
Spurious NCQ completion detection implemented in ahci was incorrect. On AHCI receving and processing FISes and raising interrupts are not interlocked and spurious interrupts are expected. For example, if an interrupt occurs while interrupt handler is running and the running interrupt handler handles the event the new IRQ indicated, after IRQ handler finishes, it will be executed again because IRQ pending bit is set by the new interrupt but there won't be anything to process. Please read the following message for more information. http://article.gmane.org/gmane.linux.ide/26012 This patch... * Removes all spurious IRQ whining from ahci. Spurious NCQ completion detection was completely wrong. Spurious D2H Register FIS taught us that some early drives send spurious D2H Register FIS with I bit set while NCQ commands are in progress but none of recent drives does that and even the ones which show such behavior can do NCQ fine. * Kills all NCQ blacklist entries which were added because of spurious NCQ completions. I tracked down each commit and verified all removed ones are actually added because of spurious completions. WD740ADFD-00NLR1 wasn't deleted but moved upward because the drive not only had spurious NCQ completions but also is slow on sequential data transfers if NCQ is enabled. Maxtor 7V300F0 was added by 0e3dbc01 from Alan Cox. I can only find evidences that the drive only had troubles with spuruious completions by searching the mailing list. This entry needs to be verified and removed if it doesn't have other NCQ related problems. Signed-off-by: NTejun Heo <htejun@gmail.com> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: NJeff Garzik <jeff@garzik.org>
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由 Tejun Heo 提交于
ICH6 R/Ms share PCI ID between piix and ahci modes and we've been allowing ahci to attach regardless of how BIOS configured it. However, enabling AHCI mode when the controller is in combined mode can result in unexpected behavior. Don't attach if the controller is in combined mode. Signed-off-by: NTejun Heo <htejun@gmail.com> Cc: Bill Nottingham <notting@redhat.com> Signed-off-by: NJeff Garzik <jeff@garzik.org>
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由 Tejun Heo 提交于
There isn't much point in reporting -EOPNOTSUPP as failure. Also the message was missing newline. Signed-off-by: NTejun Heo <htejun@gmail.com> Signed-off-by: NJeff Garzik <jeff@garzik.org>
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- 05 12月, 2007 1 次提交
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由 peerchen 提交于
Add the device IDs of legacy mode of MCP79 AHCI controller to ahci.c Signed-off-by: NPeer Chen <peerchen@gmail.com> Signed-off-by: NJeff Garzik <jeff@garzik.org>
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- 29 10月, 2007 3 次提交
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由 Kristen Carlson Accardi 提交于
This patch will set the correct bits to turn on Aggressive Link Power Management (ALPM) for the ahci driver. This will cause the controller and disk to negotiate a lower power state for the link when there is no activity (see the AHCI 1.x spec for details). This feature is mutually exclusive with Hot Plug, so when ALPM is enabled, Hot Plug is disabled. ALPM will be enabled by default, but it is settable via the scsi host syfs interface. Possible settings for this feature are: Setting Effect ---------------------------------------------------------- min_power ALPM is enabled, and link set to enter lowest power state (SLUMBER) when idle Hot plug not allowed. max_performance ALPM is disabled, Hot Plug is allowed medium_power ALPM is enabled, and link set to enter second lowest power state (PARTIAL) when idle. Hot plug not allowed. Signed-off-by: NKristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: NJeff Garzik <jgarzik@redhat.com>
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由 Jeff Garzik 提交于
The recent fix to host reset introduced a problem, whereby AHCI-enable bit would be cleared upon reset, if it was not asserted prior to reset. Unconditionally enable AHCI-enable bit. Signed-off-by: NJeff Garzik <jgarzik@redhat.com>
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由 Tejun Heo 提交于
On certain device/controller combination, 0xff status is asserted after reset and doesn't get cleared during 150ms post-reset wait. As 0xff status is interpreted as no device (for good reasons), this can lead to misdetection on such cases. This patch implements ata_wait_after_reset() which replaces the 150ms sleep and waits upto ATA_TMOUT_FF_WAIT if status is 0xff. ATA_TMOUT_FF_WAIT is currently 800ms which is enough for HHD424020F7SV00 to get detected but not enough for Quantum GoVault drive which is known to take upto 2s. Without parallel probing, spending 2s on 0xff port would incur too much delay on ata_piix's which use 0xff to indicate empty port and doesn't have SCR register, so GoVault needs to wait till parallel probing. Signed-off-by: NTejun Heo <htejun@gmail.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NJeff Garzik <jeff@garzik.org>
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- 25 10月, 2007 1 次提交
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由 Tejun Heo 提交于
P5W-DH Deluxe has ICH9 which doesn't have PMP support but SIMG 4726 hardwired to the second port of AHCI controller at PCI device 1f.2. The 4726 doesn't work as PMP but as a storage processor which can do hardware RAID on downstream ports. When no device is attached to the downstream port of the 4726, pseudo ATA device for configuration appears. Unfortunately, ATA emulation on the device is very lousy and causes long hang during boot. This patch implements workaround for the board. If the mainboard is P5W-DH Deluxe (matched using DMI), only hardreset is used on the second port of AHCI controller @ 1f.2 and the hardreset doesn't depend on receiving the first FIS and just proceed to IDENTIFY. This workaround fixes bugzilla #8923. http://bugzilla.kernel.org/show_bug.cgi?id=8923Signed-off-by: NTejun Heo <htejun@gmail.com> Signed-off-by: NJeff Garzik <jeff@garzik.org>
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