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  1. 16 1月, 2012 1 次提交
  3. 29 12月, 2011 2 次提交
  5. 02 12月, 2011 1 次提交
  7. 27 11月, 2011 1 次提交
  9. 24 11月, 2011 1 次提交
  11. 23 11月, 2011 1 次提交
    • L
      ASoC: Constify snd_soc_dai_ops structs · 85e7652d
      由 Lars-Peter Clausen 提交于 
      Commit 1ee46ebd("ASoC: Make the DAI ops constant in the DAI structure")
introduced the possibility to have constant DAI ops structures, yet this is
barley used in both existing drivers and also new drivers being submitted,
although none of them modifies its DAI ops structure. The later is not
surprising since existing drivers are often used as templates for new drivers.
So this patch just constifies all existing snd_soc_dai_ops structs to eliminate
the issue altogether.

The patch was generated with the following coccinelle semantic patch:
// <smpl>
@@
identifier ops;
@@
-struct snd_soc_dai_ops ops =
+const struct snd_soc_dai_ops ops =
{ ... };
// </smpl>
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      85e7652d
  13. 20 11月, 2011 1 次提交
  15. 22 10月, 2011 1 次提交
  17. 21 10月, 2011 2 次提交
  19. 19 10月, 2011 1 次提交
  21. 12 8月, 2011 1 次提交
  23. 03 8月, 2011 1 次提交
    • W
      ASoC: sgtl5000: fix cache handling · 151798f8
      由 Wolfram Sang 提交于 
      Cache handling in this driver is broken. The chip has 16-bit registers, yet the
register numbers also increase by 2 per register, i.e.  there are only
even-numbered registers. The cache in this driver, though, simply increments
register numbers, so it does need some mapping as seen in
sgtl5000_restore_regs(), note the '>> 1':

	snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL,
                        cache[SGTL5000_CHIP_LINREG_CTRL >> 1]);

That, of course, won't work with snd_soc_update_bits(). (Thus, we won't even
notice the missing register 0x1c in the default regs which shifted all follwing
registers to wrong values.) Noticed on the MX28EVK where enabling the regulators
simply locked up the chip.

Refactor the routines and use a properly sized default_regs array which matches
the register layout of the underlying chip, i.e. create a truly flat cache.
This also saves some code which should make up for the bigger array a little.
When soc-core will somewhen have another cache type which handles a step size,
this conversion will also ease the transition.
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>
Tested-by: NDong Aisheng <b29396@freescale.com>
Tested-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NLiam Girdwood <lrg@ti.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Cc: stable@kernel.org
      151798f8
  25. 01 8月, 2011 1 次提交
  27. 30 7月, 2011 1 次提交
  29. 19 7月, 2011 2 次提交
  31. 23 3月, 2011 1 次提交
  33. 09 3月, 2011 1 次提交
  35. 28 2月, 2011 2 次提交
  37. 25 2月, 2011 1 次提交