1. 02 2月, 2008 1 次提交
  2. 31 1月, 2008 1 次提交
    • T
      percpu: change Kconfig to HAVE_SETUP_PER_CPU_AREA · 988c388a
      travis@sgi.com 提交于
      Change:
      	config ARCH_SETS_UP_PER_CPU_AREA
      to:
      	config HAVE_SETUP_PER_CPU_AREA
      
      Cc: Andi Kleen <ak@suse.de>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: David Miller <davem@davemloft.net>
      Cc: Sam Ravnborg <sam@ravnborg.org>
      Cc: Rusty Russell <rusty@rustcorp.com.au>
      Cc: Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com>
      Cc: linuxppc-dev@ozlabs.org
      Cc: linux-ia64@vger.kernel.org
      Signed-off-by: NMike Travis <travis@sgi.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      988c388a
  3. 30 1月, 2008 2 次提交
  4. 25 1月, 2008 1 次提交
  5. 24 1月, 2008 2 次提交
    • S
      b09c1644
    • P
      [POWERPC] Provide a way to protect 4k subpages when using 64k pages · fa28237c
      Paul Mackerras 提交于
      Using 64k pages on 64-bit PowerPC systems makes life difficult for
      emulators that are trying to emulate an ISA, such as x86, which use a
      smaller page size, since the emulator can no longer use the MMU and
      the normal system calls for controlling page protections.  Of course,
      the emulator can emulate the MMU by checking and possibly remapping
      the address for each memory access in software, but that is pretty
      slow.
      
      This provides a facility for such programs to control the access
      permissions on individual 4k sub-pages of 64k pages.  The idea is
      that the emulator supplies an array of protection masks to apply to a
      specified range of virtual addresses.  These masks are applied at the
      level where hardware PTEs are inserted into the hardware page table
      based on the Linux PTEs, so the Linux PTEs are not affected.  Note
      that this new mechanism does not allow any access that would otherwise
      be prohibited; it can only prohibit accesses that would otherwise be
      allowed.  This new facility is only available on 64-bit PowerPC and
      only when the kernel is configured for 64k pages.
      
      The masks are supplied using a new subpage_prot system call, which
      takes a starting virtual address and length, and a pointer to an array
      of protection masks in memory.  The array has a 32-bit word per 64k
      page to be protected; each 32-bit word consists of 16 2-bit fields,
      for which 0 allows any access (that is otherwise allowed), 1 prevents
      write accesses, and 2 or 3 prevent any access.
      
      Implicit in this is that the regions of the address space that are
      protected are switched to use 4k hardware pages rather than 64k
      hardware pages (on machines with hardware 64k page support).  In fact
      the whole process is switched to use 4k hardware pages when the
      subpage_prot system call is used, but this could be improved in future
      to switch only the affected segments.
      
      The subpage protection bits are stored in a 3 level tree akin to the
      page table tree.  The top level of this tree is stored in a structure
      that is appended to the top level of the page table tree, i.e., the
      pgd array.  Since it will often only be 32-bit addresses (below 4GB)
      that are protected, the pointers to the first four bottom level pages
      are also stored in this structure (each bottom level page contains the
      protection bits for 1GB of address space), so the protection bits for
      addresses below 4GB can be accessed with one fewer loads than those
      for higher addresses.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      fa28237c
  6. 24 12月, 2007 1 次提交
    • B
      [POWERPC] 4xx: PLB to PCI Express support · a2d2e1ec
      Benjamin Herrenschmidt 提交于
      This adds to the previous 2 patches the support for the 4xx PCI Express
      cells as found in the 440SPe revA, revB and 405EX.
      
      Unfortunately, due to significant differences between these, and other
      interesting "features" of those pieces of HW, the code isn't as simple
      as it is for PCI and PCI-X and some of the functions differ significantly
      between the 3 implementations. Thus, not only this code can only support
      those 3 implementations for now and will refuse to operate on any other,
      but there are added ifdef's to avoid the bloat of building a fairly large
      amount of code on platforms that don't need it.
      
      Also, this code currently only supports fully initializing root complex
      nodes, not endpoint. Some more code will have to be lifted from the
      arch/ppc implementation to add the endpoint support, though it's mostly
      differences in memory mapping, and the question on how to represent
      endpoint mode PCI in the device-tree is thus open.
      
      Many thanks to Stefan Roese for testing & fixing up the 405EX bits !
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NStefan Roese <sr@denx.de>
      Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
      a2d2e1ec
  7. 21 12月, 2007 1 次提交
  8. 30 11月, 2007 1 次提交
    • M
      Fix boot problem with iSeries lacking hugepage support · ba72cb8c
      Mel Gorman 提交于
      Ordinarily the size of a pageblock is determined at compile-time based on the
      hugepage size. On PPC64, the hugepage size is determined at runtime based on
      what is supported by the machine. With legacy machines such as iSeries that
      do not support hugepages, HPAGE_SHIFT is 0. This results in pageblock_order
      being set to -PAGE_SHIFT and a crash results shortly afterwards.
      
      This patch adds a function to select a sensible value for pageblock order by
      default when HUGETLB_PAGE_SIZE_VARIABLE is set. It checks that HPAGE_SHIFT
      is a sensible value before using the hugepage size; if it is not MAX_ORDER-1
      is used.
      
      This is a fix for 2.6.24.
      
      Credit goes to Stephen Rothwell for identifying the bug and testing candidate
      patches.  Additional credit goes to Andy Whitcroft for spotting a problem
      with respects to IA-64 before releasing. Additional credit to David Gibson
      for testing with the libhugetlbfs test suite.
      Signed-off-by: NMel Gorman <mel@csn.ul.ie>
      Tested-by: NStephen Rothwell <sfr@canb.auug.org.au>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Acked-by: NPaul Mackerras <paulus@samba.org>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      ba72cb8c
  9. 20 10月, 2007 1 次提交
  10. 17 10月, 2007 3 次提交
  11. 12 10月, 2007 1 次提交
  12. 05 10月, 2007 2 次提交
  13. 04 10月, 2007 1 次提交
  14. 03 10月, 2007 6 次提交
  15. 13 9月, 2007 1 次提交
  16. 24 7月, 2007 1 次提交
  17. 23 7月, 2007 1 次提交
  18. 20 7月, 2007 1 次提交
  19. 18 7月, 2007 1 次提交
  20. 17 7月, 2007 1 次提交
  21. 12 7月, 2007 1 次提交
  22. 29 6月, 2007 2 次提交
  23. 25 6月, 2007 1 次提交
  24. 14 6月, 2007 2 次提交
  25. 23 5月, 2007 1 次提交
  26. 12 5月, 2007 2 次提交
  27. 09 5月, 2007 1 次提交