- 25 5月, 2011 2 次提交
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由 Philip Rakity 提交于
32 Bit DMA/ADMA Access 32 Bit Size Support ADMA End Descriptor in current chain (no need for dummy entry) Signed-off-by: NPhilip Rakity <prakity@marvell.com> Tested-by: NChris Ball <cjb@laptop.org> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Philip Rakity 提交于
Marvell controller requires 1.8V bit in UHS control register 2 be set when doing UHS. eMMC does not require 1.8V for DDR. add platform code to handle this. Signed-off-by: NPhilip Rakity <prakity@marvell.com> Reviewed-by: NArindam Nath <arindam.nath@amd.com> Signed-off-by: NChris Ball <cjb@laptop.org>
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- 23 11月, 2010 1 次提交
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由 Philip Rakity 提交于
We now: * check for a v3 controller before setting 8-bit bus width * offer a callback for platform code to switch to 8-bit mode, which allows non-v3 controllers to support it * rely on mmc->caps |= MMC_CAP_8_BIT_DATA; in platform code to specify that the board designers have indeed brought out all the pins for 8-bit to the slot. We were previously relying only on whether the *controller* supported 8-bit, which doesn't tell us anything about the pin configuration in the board design. This fixes the MMC card regression reported by Maxim Levitsky here: http://thread.gmane.org/gmane.linux.kernel.mmc/4336 by no longer assuming that 8-bit works by default. Signed-off-by: NPhilip Rakity <prakity@marvell.com> Tested-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: NChris Ball <cjb@laptop.org>
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- 25 10月, 2010 1 次提交
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由 Zhangfei Gao 提交于
Support Marvell PXA168/PXA910/MMP2 SD Host Controller. Signed-off-by: NZhangfei Gao <zhangfei.gao@marvell.com> Acked-by: NHaojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: NChris Ball <cjb@laptop.org>
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