- 03 1月, 2009 6 次提交
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由 Mark McLoughlin 提交于
DMA_PTE_READ/WRITE are needed by kvm. Signed-off-by: NMark McLoughlin <markmc@redhat.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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由 Mark McLoughlin 提交于
Signed-off-by: NMark McLoughlin <markmc@redhat.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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由 Mark McLoughlin 提交于
We keep the struct root_entry forward declaration for the pointer in struct intel_iommu. Signed-off-by: NMark McLoughlin <markmc@redhat.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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由 Mark McLoughlin 提交于
Signed-off-by: NMark McLoughlin <markmc@redhat.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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由 Mark McLoughlin 提交于
init_dmars() is not used outside of drivers/pci/intel-iommu.c Signed-off-by: NMark McLoughlin <markmc@redhat.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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由 Mark McLoughlin 提交于
The seg, saved_msg and sysdev fields appear to be unused since before the code was first merged. linux/msi.h is not needed in linux/intel-iommu.h anymore since there is no longer a reference to struct msi_msg. The MSI code in drivers/pci/intel-iommu.c still has linux/msi.h included via linux/dmar.h. linux/sysdev.h isn't needed because there is no reference to struct sys_device. Signed-off-by: NMark McLoughlin <markmc@redhat.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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- 19 11月, 2008 1 次提交
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由 FUJITA Tomonori 提交于
Impact: cleanup I got the following warnings on IA64: linux-2.6/drivers/pci/intel-iommu.c: In function 'init_dmars': linux-2.6/drivers/pci/intel-iommu.c:1658: warning: format '%Lx' expects type 'long long unsigned int', but argument 2 has type 'u64' linux-2.6/drivers/pci/intel-iommu.c:1663: warning: format '%Lx' expects type 'long long unsigned int', but argument 2 has type 'u64' Another victim of int-ll64.h versus int-l64.h confusion between platforms. ->reg_base_addr has a type of u64 - which can only be printed out consistently if we cast its type up to LL. [ Eventually reg_base_addr should be converted to phys_addr_t, for which we have the %pR printk helper - but that is out of the scope of late -rc's. ] Signed-off-by: NFUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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- 20 10月, 2008 1 次提交
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由 Ameya Palande 提交于
Fix for a typo and and replacing incorrect word in the comment. Signed-off-by: NAmeya Palande <2ameya@gmail.com> Cc: "Ashok Raj" <ashok.raj@intel.com> Cc: "Shaohua Li" <shaohua.li@intel.com> Cc: "Anil S Keshavamurthy" <anil.s.keshavamurthy@intel.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 18 10月, 2008 2 次提交
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由 FUJITA Tomonori 提交于
This patch fixes intel-iommu to use dev->coherent_dma_mask in alloc_coherent. Currently, intel-iommu uses dev->dma_mask in alloc_coherent but alloc_coherent is supposed to use coherent_dma_mask. It could break drivers that uses smaller coherent_dma_mask than dma_mask (though the current code works for the majority that use the same mask for coherent_dma_mask and dma_mask). [dwmw2: dma_mask can be bigger than 'unsigned long'] Signed-off-by: NFUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Reviewed-by: NGrant Grundler <grundler@parisc-linux.org> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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由 Fenghua Yu 提交于
The current Intel IOMMU code assumes that both host page size and Intel IOMMU page size are 4KiB. The first patch supports variable page size. This provides support for IA64 which has multiple page sizes. This patch also adds some other code hooks for IA64 platform including DMAR_OPERATION_TIMEOUT definition. [dwmw2: some cleanup] Signed-off-by: NFenghua Yu <fenghua.yu@intel.com> Signed-off-by: NTony Luck <tony.luck@intel.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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- 17 10月, 2008 1 次提交
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由 Youquan Song 提交于
If queued invalidation interface is available and enabled, queued invalidation interface will be used instead of the register based interface. According to Vt-d2 specification, when queued invalidation is enabled, invalidation command submit works only through invalidation queue and not through the command registers interface. Signed-off-by: NYouquan Song <youquan.song@intel.com> Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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- 15 10月, 2008 1 次提交
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由 Kay, Allen M 提交于
This patch extends the VT-d driver to support KVM [Ben: fixed memory pinning] [avi: move dma_remapping.h as well] Signed-off-by: NKay, Allen M <allen.m.kay@intel.com> Signed-off-by: NWeidong Han <weidong.han@intel.com> Signed-off-by: NBen-Ami Yassour <benami@il.ibm.com> Signed-off-by: NAmit Shah <amit.shah@qumranet.com> Acked-by: NMark Gross <mgross@linux.intel.com> Signed-off-by: NAvi Kivity <avi@qumranet.com>
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- 10 9月, 2008 1 次提交
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由 David Woodhouse 提交于
Some BIOSes (the Intel DG33BU, for example) wrongly claim to have DMAR when they don't. Avoid the resulting crashes when it doesn't work as expected. Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com> Acked-by: NIngo Molnar <mingo@elte.hu> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
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- 06 9月, 2008 1 次提交
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由 David Woodhouse 提交于
Some BIOSes (the Intel DG33BU, for example) wrongly claim to have DMAR when they don't. Avoid the resulting crashes when it doesn't work as expected. I'd still be grateful if someone could test it on a DG33BU with the old BIOS though, since I've killed mine. I tested the DMI version, but not this one. Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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- 12 7月, 2008 6 次提交
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由 Suresh Siddha 提交于
Interrupt remapping (part of Intel Virtualization Tech for directed I/O) infrastructure. Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com> Cc: akpm@linux-foundation.org Cc: arjan@linux.intel.com Cc: andi@firstfloor.org Cc: ebiederm@xmission.com Cc: jbarnes@virtuousgeek.org Cc: steiner@sgi.com Signed-off-by: NIngo Molnar <mingo@elte.hu>
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由 Suresh Siddha 提交于
Queued invalidation (part of Intel Virtualization Technology for Directed I/O architecture) infrastructure. This will be used for invalidating the interrupt entry cache in the case of Interrupt-remapping and IOTLB invalidation in the case of DMA-remapping. Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com> Cc: akpm@linux-foundation.org Cc: arjan@linux.intel.com Cc: andi@firstfloor.org Cc: ebiederm@xmission.com Cc: jbarnes@virtuousgeek.org Cc: steiner@sgi.com Signed-off-by: NIngo Molnar <mingo@elte.hu>
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由 Suresh Siddha 提交于
move IOMMU_WAIT_OP() macro to header file. This will be used by both DMA-remapping and Intr-remapping. Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com> Cc: akpm@linux-foundation.org Cc: arjan@linux.intel.com Cc: andi@firstfloor.org Cc: ebiederm@xmission.com Cc: jbarnes@virtuousgeek.org Cc: steiner@sgi.com Signed-off-by: NIngo Molnar <mingo@elte.hu>
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由 Suresh Siddha 提交于
Allocate the iommu during the parse of DMA remapping hardware definition structures. And also, introduce routines for device scope initialization which will be explicitly called during dma-remapping initialization. These will be used for enabling interrupt remapping separately from the existing DMA-remapping enabling sequence. Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com> Cc: akpm@linux-foundation.org Cc: arjan@linux.intel.com Cc: andi@firstfloor.org Cc: ebiederm@xmission.com Cc: jbarnes@virtuousgeek.org Cc: steiner@sgi.com Signed-off-by: NIngo Molnar <mingo@elte.hu>
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由 Suresh Siddha 提交于
Clean up the intel-iommu code related to deferred iommu flush logic. There is no need to allocate all the iommu's as a sequential array. This will be used later in the interrupt-remapping patch series to allocate iommu much early and individually for each device remapping hardware unit. Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com> Cc: akpm@linux-foundation.org Cc: arjan@linux.intel.com Cc: andi@firstfloor.org Cc: ebiederm@xmission.com Cc: jbarnes@virtuousgeek.org Cc: steiner@sgi.com Signed-off-by: NIngo Molnar <mingo@elte.hu>
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由 Suresh Siddha 提交于
code reorganization of the generic Intel vt-d parsing related routines and linux iommu routines specific to Intel vt-d. drivers/pci/dmar.c now contains the generic vt-d parsing related routines drivers/pci/intel_iommu.c contains the iommu routines specific to vt-d Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com> Cc: akpm@linux-foundation.org Cc: arjan@linux.intel.com Cc: andi@firstfloor.org Cc: ebiederm@xmission.com Cc: jbarnes@virtuousgeek.org Cc: steiner@sgi.com Signed-off-by: NIngo Molnar <mingo@elte.hu>
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- 11 7月, 2008 1 次提交
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由 FUJITA Tomonori 提交于
gart.h has only GART-specific stuff. Only GART code needs it. Other IOMMU stuff should include iommu.h instead of gart.h. Signed-off-by: NFUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Acked-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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- 08 7月, 2008 1 次提交
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由 Yinghai Lu 提交于
want to remove arch_get_ram_range, and use early_node_map instead. Signed-off-by: NYinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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- 11 6月, 2008 1 次提交
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由 Julia Lawall 提交于
The destination of goto error also does a kfree(g_iommus), so it is not correct to do one here. This was found using Coccinelle (http://www.emn.fr/x-info/coccinelle/). Signed-off-by: NJulia Lawall <julia@diku.dk> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
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- 14 5月, 2008 1 次提交
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由 mark gross 提交于
The following patch changes the intel-iommu.c code to use the TSC instead of jiffies for detecting bad DMAR functionality. Some systems with bad bios's have been seen to hang in early boot spinning in the IOMMU_WAIT_IO macro. This patch will replace the infinite loop with a call to panic. Signed-off-by: NMark Gross <mgross@linux.intel.com> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
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- 25 4月, 2008 1 次提交
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由 Ingo Molnar 提交于
Stephen Rothwell noticed that: Commit 2be62149 ("x86: dma-ops on highmem fix") in Linus' tree introduced a new warning (noticed in the x86_64 allmodconfig build of linux-next): drivers/pci/intel-iommu.c:2240: warning: initialization from incompatible pointer type Which points at an instance of map_single that needs updating. Fix it to the new prototype. Signed-off-by: NIngo Molnar <mingo@elte.hu>
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- 21 4月, 2008 2 次提交
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由 mark gross 提交于
The following patch is an update to use an array instead of a list of IOVA's in the implementation of defered iotlb flushes. It takes inspiration from sba_iommu.c I like this implementation better as it encapsulates the batch process within intel-iommu.c, and no longer touches iova.h (which is shared) Performance data: Netperf 32byte UDP streaming 2.6.25-rc3-mm1: IOMMU-strict : 58Mps @ 62% cpu NO-IOMMU : 71Mbs @ 41% cpu List-based IOMMU-default-batched-IOTLB flush: 66Mbps @ 57% cpu with this patch: IOMMU-strict : 73Mps @ 75% cpu NO-IOMMU : 74Mbs @ 42% cpu Array-based IOMMU-default-batched-IOTLB flush: 72Mbps @ 62% cpu Signed-off-by: <mgross@linux.intel.com> Cc: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
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由 mark gross 提交于
This patch is for batching up the flushing of the IOTLB for the DMAR implementation found in the Intel VT-d hardware. It works by building a list of to be flushed IOTLB entries and a bitmap list of which DMAR engine they are from. After either a high water mark (250 accessible via debugfs) or 10ms the list of iova's will be reclaimed and the DMAR engines associated are IOTLB-flushed. This approach recovers 15 to 20% of the performance lost when using the IOMMU for my netperf udp stream benchmark with small packets. It can be disabled with a kernel boot parameter "intel_iommu=strict". Its use does weaken the IOMMU protections a bit. Signed-off-by: NMark Gross <mgross@linux.intel.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
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- 25 3月, 2008 1 次提交
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由 Mark Gross 提交于
lockdep goes off on the iova copy_reserved_iova() because it and a function it calls grabs locks in the from, and the to of the copy operation. The function grab locks of the same lock classes triggering the warning. The first lock grabbed is for the constant reserved areas that is never accessed after early boot. Technically you could do without grabbing the locks for the "from" structure its copying reserved areas from. But dropping the from locks to me looks wrong, even though it would be ok. The affected code only runs in early boot as its setting up the DMAR engines. This patch gives the reserved_ioval_list locks special lockdep classes. Signed-off-by: NMark Gross <mgross@linux.intel.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
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- 24 2月, 2008 1 次提交
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由 mark gross 提交于
The following is a clean up and correction of the copyright holding entities for the files associated with the intel iommu code. Signed-off-by: <mgross@linux.intel.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 09 2月, 2008 2 次提交
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由 mark gross 提交于
Fix an off by one bug in the fault reason string reporting function, and clean up some of the code around this buglet. [akpm@linux-foundation.org: cleanup] Signed-off-by: Nmark gross <mgross@linux.intel.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Andi Kleen <ak@suse.de> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 mark gross 提交于
Add support for protected memory enable bits by clearing them if they are set at startup time. Some future boot loaders or firmware could have this bit set after it loads the kernel, and it needs to be cleared if DMA's are going to happen effectively. Signed-off-by: Nmark gross <mgross@intel.com> Acked-by: NMuli Ben-Yehuda <muli@il.ibm.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Andi Kleen <ak@suse.de> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 07 2月, 2008 1 次提交
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由 David Miller 提交于
I would like to potentially move the sparc64 IOMMU code over to using the nice new drivers/pci/iova.[ch] code for free area management.. In order to do that we have to detach the IOMMU page size assumptions which only really need to exist in the intel-iommu.[ch] code. This patch attempts to implement that. [akpm@linux-foundation.org: build fix] Signed-off-by: NDavid S. Miller <davem@davemloft.net> Acked-by: NAnil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 02 2月, 2008 1 次提交
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由 Joe Perches 提交于
Signed-off-by: NJoe Perches <joe@perches.com> Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
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- 30 10月, 2007 2 次提交
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由 Takashi Iwai 提交于
Fix possible array overflow: drivers/pci/intel-iommu.c: In function ¡dmar_get_fault_reason¢: drivers/pci/intel-iommu.c:753: warning: array subscript is above array bounds drivers/pci/intel-iommu.c: In function ¡iommu_page_fault¢: drivers/pci/intel-iommu.c:753: warning: array subscript is above array bounds Signed-off-by: NTakashi Iwai <tiwai@suse.de> Cc: Mark Gross <mgross@linux.intel.com> Acked-by: N"Keshavamurthy, Anil S" <anil.s.keshavamurthy@intel.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Joerg Roedel 提交于
This patch renames the include file asm-x86/iommu.h to asm-x86/gart.h to make clear to which IOMMU implementation it belongs. The patch also adds "GART" to the Kconfig line. Signed-off-by: NJoerg Roedel <joerg.roedel@amd.com> Acked-by: NMuli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: NIngo Molnar <mingo@elte.hu> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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- 29 10月, 2007 1 次提交
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由 Al Viro 提交于
- off by one in dmar_get_fault_reason() (maximal index in array is ARRAY_SIZE()-1, not ARRAY_SIZE()) - NULL noise removal - __iomem annotation fix Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 23 10月, 2007 1 次提交
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由 FUJITA Tomonori 提交于
Signed-off-by: NFUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Signed-off-by: NJens Axboe <jens.axboe@oracle.com>
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- 22 10月, 2007 3 次提交
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由 FUJITA Tomonori 提交于
x86_64 defines ARCH_HAS_SG_CHAIN. So if IOMMU implementations don't support sg chaining, we will get data corruption. Signed-off-by: NFUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Acked-by: NAnil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Cc: Jens Axboe <jens.axboe@oracle.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Keshavamurthy, Anil S 提交于
pci_dev's->sysdata is highly overloaded and currently IOMMU is broken due to IOMMU code depending on this field. This patch introduces new field in pci_dev's dev.archdata struct to hold IOMMU specific per device IOMMU private data. Signed-off-by: NAnil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Greg KH <greg@kroah.com> Cc: Jeff Garzik <jeff@garzik.org> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Keshavamurthy, Anil S 提交于
This patch adds PageSelectiveInvalidation support replacing existing DomainSelectiveInvalidation for intel_{map/unmap}_sg() calls and also enables to mapping one big contiguous DMA virtual address which is mapped to discontiguous physical address for SG map/unmap calls. "Doamin selective invalidations" wipes out the IOMMU address translation cache based on domain ID where as "Page selective invalidations" wipes out the IOMMU address translation cache for that address mask range which is more cache friendly when compared to Domain selective invalidations. Here is how it is done. 1) changes to iova.c alloc_iova() now takes a bool size_aligned argument, which when when set, returns the io virtual address that is naturally aligned to 2 ^ x, where x is the order of the size requested. Returning this io vitual address which is naturally aligned helps iommu to do the "page selective invalidations" which is IOMMU cache friendly over "domain selective invalidations". 2) Changes to driver/pci/intel-iommu.c Clean up intel_{map/unmap}_{single/sg} () calls so that s/g map/unamp calls is no more dependent on intel_{map/unmap}_single() intel_map_sg() now computes the total DMA virtual address required and allocates the size aligned total DMA virtual address and maps the discontiguous physical address to the allocated contiguous DMA virtual address. In the intel_unmap_sg() case since the DMA virtual address is contiguous and size_aligned, PageSelectiveInvalidation is used replacing earlier DomainSelectiveInvalidations. Signed-off-by: NAnil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Cc: Greg KH <greg@kroah.com> Cc: Ashok Raj <ashok.raj@intel.com> Cc: Suresh B <suresh.b.siddha@intel.com> Cc: Andi Kleen <ak@suse.de> Cc: Arjan van de Ven <arjan@infradead.org> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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