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  1. 23 8月, 2007 5 次提交
  3. 12 7月, 2007 3 次提交
  5. 01 6月, 2007 2 次提交
  7. 31 5月, 2007 1 次提交
  9. 12 5月, 2007 1 次提交
  11. 03 5月, 2007 1 次提交
  13. 29 4月, 2007 1 次提交
    • J
      libata/IDE: remove combined mode quirk · 8cdfb29c
      由 Jeff Garzik 提交于 
      Both old-IDE and libata should be able handle all controllers and
devices found using normal resource reservation methods.

This eliminates the awful, low-performing split-driver configuration
where old-IDE drove the PATA portion of a PCI device, in PIO-only mode,
and libata drove the SATA portion of the /same/ PCI device, in DMA mode.
Typically vendors would ship SATA hard drive / PATA optical
configuration, which would lend itself to slow (PIO-only) CD-ROM
performance.

For Intel users running in combined mode, it is now wholly dependent on
your driver choice (potentially link order, if you compile both drivers
in) whether old-IDE or libata will drive your hardware.

In either case, you will get full performance from both SATA and PATA
ports now, without having to pass a kernel command line parameter.
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      8cdfb29c
  15. 27 3月, 2007 1 次提交
  17. 05 3月, 2007 1 次提交
    • E
      [PATCH] msi: sanely support hardware level msi disabling · f5f2b131
      由 Eric W. Biederman 提交于 
      In some cases when we are not using msi we need a way to ensure that the
hardware does not have an msi capability enabled.  Currently the code has been
calling disable_msi_mode to try and achieve that.  However disable_msi_mode
has several other side effects and is only available when msi support is
compiled in so it isn't really appropriate.

Instead this patch implements pci_msi_off which disables all msi and msix
capabilities unconditionally with no additional side effects.

pci_disable_device was redundantly clearing the bus master enable flag and
clearing the msi enable bit.  A device that is not allowed to perform bus
mastering operations cannot generate intx or msi interrupt messages as those
are essentially a special case of dma, and require bus mastering.  So the call
in pci_disable_device to disable msi capabilities was redundant.

quirk_pcie_pxh also called disable_msi_mode and is updated to use pci_msi_off.
Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
Cc: Michael Ellerman <michael@ellerman.id.au>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Greg KH <greg@kroah.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      f5f2b131
  19. 02 3月, 2007 2 次提交
    • T
      ahci/pata_jmicron: match class not function number · e34bb370
      由 Tejun Heo 提交于 
      Make jmiron_ata quirk update pdev->class after programming the device
and update ahci and pata_jmicron such that they match class code
instead of checking function number manually.  For ahci, it matches
for vendor and class.  For pata_jmicron, it matches vendor, device and
class as IDE class isn't as well defined as AHCI class.

This makes jmicron device matching more conventional and script
friendly.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      e34bb370
    • T
      jmicron ATA: reimplement jmicron ATA quirk · 5ee2ae7f
      由 Tejun Heo 提交于 
      Reimplement jmicron ATA quirk.

* renamed to quirk_jmicron_ata()
* quirk is invoked only for the affected controllers
* programming is stricter.  e.g. conf5 bit24 is cleared if
  unnecessary.
* code factored for readability
* JMB360 and JMB368 are programmed into proper mode

Verified on JMB360, 363 and 368.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      5ee2ae7f
  21. 10 2月, 2007 1 次提交
  23. 08 2月, 2007 6 次提交
  25. 03 2月, 2007 1 次提交
    • T
      ahci/pata_jmicron: fix JMicron quirk · 77280989
      由 Tejun Heo 提交于 
      For all JMicrons except for 361 and 368, AHCI mode enable bits in the
Control(1) should be set.  This used to be done in both ahci and
pata_jmicron but while moving programming to PCI quirk, it was removed
from ahci part while still left in pata_jmicron.

The implemented JMicron PCI quirk was incorrect in that it didn't
program AHCI mode enable bits.  If pata_jmicron is loaded first and
programs those bits, the ahci ports work; otherwise, ahci device
detection fails miserably.

This patch makes JMicron PCI quirk clear SATA IDE mode bits and set
AHCI mode bits and remove the respective part from pata_jmicron.
Tested on JMB361, 363 and 368.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      77280989
  27. 02 2月, 2007 1 次提交
  29. 31 1月, 2007 1 次提交
  31. 23 1月, 2007 1 次提交
  33. 11 1月, 2007 1 次提交
    • V
      [PATCH] x86-64: pci quirks MODPOST warning fix · 9d24a81e
      由 Vivek Goyal 提交于 
      o MODPOST generates warnings for i386 if kernel is compiled with
  CONFIG_RELOCATABLE=y

WARNING: vmlinux - Section mismatch: reference to .init.data: from .text between 'asus_hides_smbus_lpc_ich6' (at offset 0xc0217d58) and 'quirk_cardbus_legacy'
WARNING: vmlinux - Section mismatch: reference to .init.data: from .text between 'asus_hides_smbus_lpc' (at offset 0xc0217fd9) and 'pci_match_id'

o Two quirk functions which are non __init, are accessing data which is
  of type __init.
Signed-off-by: NVivek Goyal <vgoyal@in.ibm.com>
Signed-off-by: NAndi Kleen <ak@suse.de>
      9d24a81e
  35. 10 1月, 2007 1 次提交
  37. 21 12月, 2006 5 次提交
  39. 02 12月, 2006 1 次提交
    • A
      PCI: quirks: fix the festering mess that claims to handle IDE quirks · 368c73d4
      由 Alan Cox 提交于 
      The number of permutations of crap we do is amazing and almost all of it
has the wrong effect in 2.6.

At the heart of this is the PCI SFF magic which says that compatibility
mode PCI IDE controllers use ISA IRQ routing and hard coded addresses
not the BAR values. The old quirks variously clears them, sets them,
adjusts them and then IDE ignores the result.

In order to drive all this garbage out and to do it portably we need to
handle the SFF rules directly and properly. Because we know the device
BAR 0-3 are not used in compatibility mode we load them with the values
that are implied (and indeed which many controllers actually
thoughtfully put there in this mode anyway).

This removes special cases in the IDE layer and libata which now knows
that bar 0/1/2/3 always contain the correct address. It means our
resource allocation map is accurate from boot, not "mostly accurate"
after ide is loaded, and it shoots lots of code. There is also lots more
code and magic constant knowledge to shoot once this is in and settled.

Been in my test tree for a while both with drivers/ide and with libata.
Wants some -mm shakedown in case I've missed something dumb or there are
corner cases lurking.
Signed-off-by: NAlan Cox <alan@redhat.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      368c73d4
  41. 15 11月, 2006 1 次提交
  43. 28 10月, 2006 2 次提交