1. 10 12月, 2008 1 次提交
  2. 21 10月, 2008 1 次提交
    • V
      PCI: probing debug message uniformization · f393d9b1
      Vincent Legoll 提交于
      This patch uniformizes PCI probing debug boot messages with dev_printk()
      intead of manual printk()
      
      It changes adress range output from [%llx, %llx] to [%#llx-%#llx], like
      in pci_request_region().
      
      For example, it goes from the mixed-style:
      
      PCI: 0000:00:1b.0 reg 10 64bit mmio: [f4280000, f4283fff]
      pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold
      
      to uniform:
      
      pci 0000:00:1b.0: reg 10 64bit mmio: [0xf4280000-0xf4283fff]
      pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold
      
      This patch has been runtime tested, boot log messages diffed, everything
      looks OK.
      Acked-by: NBjorn Helgaas <bjorn.helgaas@hp.com>
      Signed-off-by: NVincent Legoll <vincent.legoll@gmail.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      f393d9b1
  3. 17 9月, 2008 1 次提交
  4. 29 7月, 2008 3 次提交
  5. 22 5月, 2008 1 次提交
  6. 21 4月, 2008 1 次提交
    • S
      PCI: add PCI Express ASPM support · 7d715a6c
      Shaohua Li 提交于
      PCI Express ASPM defines a protocol for PCI Express components in the D0
      state to reduce Link power by placing their Links into a low power state
      and instructing the other end of the Link to do likewise. This
      capability allows hardware-autonomous, dynamic Link power reduction
      beyond what is achievable by software-only controlled power management.
      However, The device should be configured by software appropriately.
      Enabling ASPM will save power, but will introduce device latency.
      
      This patch adds ASPM support in Linux. It introduces a global policy for
      ASPM, a sysfs file /sys/module/pcie_aspm/parameters/policy can control
      it. The interface can be used as a boot option too. Currently we have
      below setting:
              -default, BIOS default setting
              -powersave, highest power saving mode, enable all available ASPM
      state and clock power management
              -performance, highest performance, disable ASPM and clock power
      management
      By default, the 'default' policy is used currently.
      
      In my test, power difference between powersave mode and performance mode
      is about 1.3w in a system with 3 PCIE links.
      
      Note: some devices might not work well with aspm, either because chipset
      issue or device issue. The patch provide API (pci_disable_link_state),
      driver can disable ASPM for specific device.
      Signed-off-by: NShaohua Li <shaohua.li@intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      7d715a6c
  7. 03 2月, 2008 1 次提交
  8. 02 2月, 2008 1 次提交
    • S
      PCI: PCIE ASPM support · 6c723d5b
      Shaohua Li 提交于
      PCI Express ASPM defines a protocol for PCI Express components in the D0
      state to reduce Link power by placing their Links into a low power state
      and instructing the other end of the Link to do likewise. This
      capability allows hardware-autonomous, dynamic Link power reduction
      beyond what is achievable by software-only controlled power management.
      However, The device should be configured by software appropriately.
      Enabling ASPM will save power, but will introduce device latency.
      
      This patch adds ASPM support in Linux. It introduces a global policy for
      ASPM, a sysfs file /sys/module/pcie_aspm/parameters/policy can control
      it. The interface can be used as a boot option too. Currently we have
      below setting:
              -default, BIOS default setting
              -powersave, highest power saving mode, enable all available ASPM
      state
      and clock power management
              -performance, highest performance, disable ASPM and clock power
      management
      By default, the 'default' policy is used currently.
      
      In my test, power difference between powersave mode and performance mode
      is about 1.3w in a system with 3 PCIE links.
      Signed-off-by: NShaohua Li <shaohua.li@intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      6c723d5b