The recently merged AT91SAM9 watchdog driver uses the
AT91SAM9X_WATCHDOG config variable, whereas the original version of
the driver (and the platform support code) used AT91SAM9_WATCHDOG.
This causes the watchdog platform_device to never be registered, and
therefore the driver not to be initialized.

This patch:
- updates the platform support code to use AT91SAM9X_WATCHDOG.
- includes <linux/io.h> to fix compile error (same fix as was applied
to at91rm9200_wdt.c)
- fixes comment regarding watchdog clock-rates in at91rm9200.
Signed-off-by: NAndrew Victor <linux@maxim.org.za>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

_omap2_clksel_get_src_field() was returning the first entry which was
either the default _or_ applicable to the SoC.  This is wrong - we
should be returning the first default which is applicable to the SoC.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The error checks for omap2_divisor_to_clksel() and comment disagree with
the actual value returned on error.  Fix this to return the correct error
value.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The C99 specification states in section 6.11.5:

The placement of a storage-class specifier other than at the beginning of the
declaration specifiers in a declaration is an obsolescent feature.
Signed-off-by: NTobias Klauser <tklauser@distanz.ch>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch adds a MX2/MX3 specific SDHC driver. The hardware is basically
the same as in the MX1, but unlike the MX1 controller the MX2
controller just works as expected. Since the MX1 driver has more
workarounds for bugs than anything else I had no success with supporting
MX1 and MX2 in a sane way in one driver.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NPierre Ossman <drzeus@drzeus.cx>

"flash" is a very generic name for a platform_driver that is only
available on SA11x0.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Nicolas Pitre <nico@marvell.com>

Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>

SPIN_LOCK_UNLOCKED is deprecated as lockdep cannot properly work with
locks initialized with it.

This fix is necessary to compile the linux-rt tree for ARM.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Steven Rostedt <srostedt@redhat.com>

In omap24xx_cpu_suspend assembly routine, the r2 register which holds
the address of the SDRC_POWER reg is set to zero before the value is
written back triggering a fault due to writing to address zero.

It's hard to tell where this change was introduced since this file
has been moved and merged.

While this fix prevents a crash, suspend on my n810 is broken with
current kernels.  I never come out of suspend.
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

By Ingo Molnar, interrupts are not masked by default.
(refer to 76d21601)

But if interrupts are not masked, the processor can wake up while in
Suspend-to-RAM state by an external interrupt. For example, if an
OMAP3 board is connected to Host PC by USB and entered to Suspend-to-RAM
state, it wake up automatically by M_IRQ_92. The disable_irq() function
can't disable the interrupt in H/W level, So I modified
arch/arm/mach-omap2/irq.c
Signed-off-by: NKim Kyuwon <chammoru@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

When 32 kHz timer is used the min_delta_ns should be initialized so
that it reflects the timer programming cost. A write to the timer
device will be usually posted, but it takes roughly 3 cycles before
it is effective. If the timer is reprogrammed before that, the CPU
will stall until the previous write completes. This was pointed out by
Richard Woodruff.

Since the lower bound for min_delta_ns is 1000, the change is visible
only with tick rates less than 3 MHz.

Also note that the old value is incorrect for 32 kHz also due to
a rounding error, and it can cause the timer queue to hang (due to
clockevent code trying to program the timer with zero ticks).
Signed-off-by: NAaro Koskinen <Aaro.Koskinen@nokia.com>
Reviewed-by: NRichard Woodruff <r-woodruff2@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The naming accidentally broke while changing the name for the
driver to not to conflict with the other mmc driver.
Signed-off-by: NTony Lindgren <tony@atomide.com>

Fix omap34xx revision detection for ES3.1
Signed-off-by: NTony Lindgren <tony@atomide.com>

This has similar symptoms than 66c23551
where just omap_request_dma, omap_dma_link_lch and omap_dma_unlink_lch
can cause incorrect dump_stack(). Here it can happen if channel has been
used before and the channel flags variable holds old status.
Signed-off-by: NJarkko Nikula <jarkko.nikula@nokia.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

CSR must be cleared before invoking the callback.

If the callback function starts a new, fast DMA transfer on the same
channel, the completion status might lost if CSR is cleared after
the callback invocation.
Signed-off-by: NJuha Yrjola <juha.yrjola@solidboot.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

A spin_lock deadlock will occur when omap_mcbsp_request() is invoked.

omap_mcbsp_request()
\- clk_enable(mcbsp->clk)         [takes and holds clockfw_lock]
    \- omap2_clk_enable()
       \- _omap2_clk_enable()
           \- omap_mcbsp_clk_enable()
              \- clk_enable(child clock)   [tries for clockfw_lock again]

mcbsp_clk is a virtual clock and it comprises several child clocks. when
enable mcbsp_clk in omap_mcbsp_request(), the enable function of mcbsp_clk
will enable its child clocks, then the deadlock occurs.

The solution is to remove the virtual clock and enable these child clocks in
omap_mcbsp_request() directly.
Signed-off-by: NStanley.Miao <stanley.miao@windriver.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

When there are multiple L1-aliasing userland mappings of the same physical
page, we currently remap each of them uncached, to prevent VIVT cache
aliasing issues. (E.g. writes to one of the mappings not being immediately
visible via another mapping.)  However, when we do this remapping, there
could still be stale data in the L2 cache, and an uncached mapping might
bypass L2 and go straight to RAM.  This would cause reads from such
mappings to see old data (until the dirty L2 line is eventually evicted.)

This issue is solved by forcing a L2 cache flush whenever the shared page
is made L1 uncacheable.

Ideally, we would make L1 uncacheable and L2 cacheable as L2 is PIPT. But
Feroceon does not support that combination, and the TEX=5 C=0 B=0 encoding
for XSc3 doesn't appear to work in practice.
Signed-off-by: NNicolas Pitre <nico@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Aaro says:
> With spinlock debugs enabled I get might_sleep() warnings when using
> ptrace.

tracked down to a missing enable_irq before calling do_undefinstr().
Reported-by: NAaro Koskinen <aaro.koskinen@nokia.com>
Tested-by: NAaro Koskinen <aaro.koskinen@nokia.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

arch/arm/mach-msm/board-halibut.c:45: error: implicit declaration of function 'MSM_GPIO_TO_INT'
arch/arm/mach-msm/board-halibut.c:45: error: initializer element is not constant
arch/arm/mach-msm/board-halibut.c:45: error: (near initialization for 'smc91x_resources[1].start')
arch/arm/mach-msm/board-halibut.c:46: error: initializer element is not constant
arch/arm/mach-msm/board-halibut.c:46: error: (near initialization for 'smc91x_resources[1].end')
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The DaVinci code had an implementation of the OTG transceiver glue
too; make it use the new-standard one.
Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net>
Acked-by: NFelipe Balbi <felipe.balbi@nokia.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

Now that all EEPROM drivers live in the same place, let's harmonize
their symbol names.

Also fix eeprom's dependencies, it definitely needs sysfs, and is no
longer experimental after many years in the kernel tree.
Signed-off-by: NJean Delvare <khali@linux-fr.org>
Acked-by: NWolfram Sang <w.sang@pengutronix.de>
Cc: David Brownell <dbrownell@users.sourceforge.net>

The EH message for NODEV_HINT path was describing the opposite
condition.  Fix it.
Signed-off-by: NTejun Heo <tj@kernel.org>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

Tomi Valkeinen reports:
  Running with latest linux-omap kernel on OMAP3 SDP board, I have
  problem with iounmap(). It looks like iounmap() does not properly
  free large areas. Below is a test which fails for me in 6-7 loops.

	for (i = 0; i < 200; ++i) {
		vaddr = ioremap(paddr, size);
		if (!vaddr) {
			printk("couldn't ioremap\n");
			break;
		}
		iounmap(vaddr);
	}

The changes to vmalloc.c weren't reflected in the ARM ioremap
implementation.  Turns out the fix is rather simple.
Tested-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>
Tested-by: NMatt Gerassimoff <mgeras@gmail.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

... for devices.  Doing so is a bug, plain and simple, and drives
GregKH round the bend.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The old matching algorithm was too fuzzy, causing false positives.
For example, when asked for device D connection C1 and we only find
device D connection C2, we return that as a valid match despite the
connection names being different.

Change the algorithm such that:
  An entry with a NULL ID is assumed to be a wildcard.
  If an entry has a device ID, it must match
  If an entry has a connection ID, it must match

However, we maintain the order of precidence while still only doing
a single pass over all entries: dev+con > dev only > con only.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

From: David Brownell <dbrownell@users.sourceforge.net>
Subject: ARM/mach-davinci/usb.c buildfix

  CC      arch/arm/mach-davinci/usb.o
arch/arm/mach-davinci/usb.c:60: error: 'IRQ_USBINT' undeclared here (not in a function)
make[1]: *** [arch/arm/mach-davinci/usb.o] Error 1
Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Which had the 'from' and 'to' pages reversed.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This is a framebuffer driver for i.MX31 SoCs. It only supports synchronous
displays, vertical panning supported, no overlay support.
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NGuennadi Liakhovetski <lg@denx.de>
Signed-off-by: NDan Williams <dan.j.williams@intel.com>

Some broken bootloaders will leave the DMA channel state unclean, which
we should really initialize correctly here.
Signed-off-by: NEric Miao <eric.miao@marvell.com>

i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.

IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NGuennadi Liakhovetski <lg@denx.de>
Signed-off-by: NDan Williams <dan.j.williams@intel.com>

The only exclusive definitions are SSCR0_SCR and SSCR0_SerClkDiv(), loosen
that exclusive #ifdef .. #else .. #endif to allow other definitions to be
visible when slected multiple processors. This helps to pass the building
of pxa-ssp.c.
Signed-off-by: NEric Miao <eric.miao@marvell.com>

This currently happens for 'drivers/input/touch/mainstone-wm97xx.c'.
Signed-off-by: NEric Miao <eric.miao@marvell.com>

After commit 8c3abc7d
("[ARM] pxa: convert to clkdev and match clocks by struct device where possible")
get_clk in pxa3xx_nand fails with -ENOENT.
Apparently, clk_get in pxamci will also fail for MCI2 on PXA310.

The 'clk_find' and therefore 'clk_get' require driver to supply
both 'dev_id' and 'con_id' if they are not NULL in the 'strcut clk_lookup',
but neither pxa3xx_nand nor pxamci supply 'con_id'.

This patch sets 'con_id' to NULL in NAND clock and MCI2 clock registration.
Signed-off-by: NMike Rapoport <mike@compulab.co.il>
Signed-off-by: NEric Miao <eric.miao@marvell.com>

Fix compile for h3 MMC
Signed-off-by: NTony Lindgren <tony@atomide.com>

This patch removes old platform devices. Alsa should now
be using the ASoC driver. For boards not yet using ASoC,
please see sound/soc/omap/osk5912.c.

Add dummy aic23_power_up and aic23_power_down functions for 770
to keep things compiling.

Remove references to omap_gpio_switch, and unused h2_nand_dev_ready
function.

This patch is based on an earlier patch by Arun KS.

Cc: Jarkko Nikula <jarkko.nikula@nokia.com>
Signed-off-by: NArun KS <arunks@mistralsolutions.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This patch enables writing to McBSP Transmit Configuration Control
Register (XCCR) and Receive Configuration Control Register (RCCR)
for 2430/34xx platforms. It also adds XCCR, RCCR entries in McBSP
register configuration structure and bit definitions for both
registers.

If we enable the writing to CCR registers for 2430/34xx and don't
set the default values (setting 0 as a consequence) in ASoC driver,
the Transmit/Receive DMA mode gets disabled and the the
transmission/reception doesn't happen, ending with a
"write error: Input/Output error" when playing with 'aplay'.

Also define dummy CCR registers for omap1.

Cc: Jarkko Nikula <jarkko.nikula@nokia.com>
Signed-off-by: NMisael Lopez Cruz <x0052729@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Adding I2C board info is required for tlvaic23 i2c chip driver.

Cc: Jarkko Nikula <jarkko.nikula@nokia.com>
Signed-off-by: NArun KS <arunks@mistralsolutions.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Removed duplicated #include's in arch/arm/mach-omap1/board-voiceblue.c
Signed-off-by: NHuang Weiyi <weiyi.huang@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Bug in existing code causes synchro control to be set +32 if request
line greater than 63 is used.

Also clean up the function a bit by removing extra parens and
clearing the bits at before write.

Reported by Wenbiao Wang.
Signed-off-by: NAnand Gadiyar <gadiyar@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

There are no wakeup registers on 15xx, and suspend_wakeup
does not exist in the struct gpio_bank.

Without this fix we'll get "arch/arm/plat-omap/gpio.c:1792:
error: 'struct gpio_bank' has no member named 'suspend_wakeup'"
as noted by Russell King.

Note that the ifdefs will be cleaned up once the omap gpio
code gets split into omap1 and omap2 specific parts.
Signed-off-by: NTony Lindgren <tony@atomide.com>