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  1. 03 8月, 2006 1 次提交
  3. 04 7月, 2006 1 次提交
  5. 01 7月, 2006 1 次提交
  7. 28 6月, 2006 1 次提交
  9. 27 6月, 2006 4 次提交
  11. 31 5月, 2006 1 次提交
  13. 10 4月, 2006 2 次提交
  15. 26 3月, 2006 1 次提交
  17. 15 3月, 2006 1 次提交
  19. 13 3月, 2006 1 次提交
    • A
      [PATCH] x86-64: Fix up handling of non canonical user RIPs · c33d4568
      由 Andi Kleen 提交于 
      EM64T CPUs have somewhat weird error reporting for non canonical RIPs in
SYSRET.

We can't handle any exceptions there because the exception handler would
end up running on the user stack which is unsafe.

To avoid problems any code that might end up with a user touched pt_regs
should return using int_ret_from_syscall.  int_ret_from_syscall ends up
using IRET, which allows safe exceptions.

Cc: Ernie Petrides <petrides@redhat.com>
Signed-off-by: NAndi Kleen <ak@suse.de>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      c33d4568
  21. 18 2月, 2006 1 次提交
  23. 05 2月, 2006 2 次提交
  25. 17 1月, 2006 1 次提交
  27. 12 1月, 2006 5 次提交
  29. 15 11月, 2005 1 次提交
    • J
      [PATCH] x86_64: Support for AMD specific MCE Threshold. · 89b831ef
      由 Jacob Shin 提交于 
      MC4_MISC - DRAM Errors Threshold Register realized under AMD K8 Rev F.
This register is used to count correctable and uncorrectable ECC errors that occur during DRAM read operations.
The user may interface through sysfs files in order to change the threshold configuration.

bank%d/error_count - reads current error count, write to clear.
bank%d/interrupt_enable - set/clear interrupt enable.
bank%d/threshold_limit - read/write the threshold limit.

APIC vector 0xF9 in hw_irq.h.
5 software defined bank ids in mce.h.
new apic.c function to setup threshold apic lvt.
defaults to interrupt off, count enabled, and threshold limit max.
sysfs interface created on /sys/devices/system/threshold.

AK: added some ifdefs to make it compile on UP
Signed-off-by: NJacob Shin <jacob.shin@amd.com>
Signed-off-by: NAndi Kleen <ak@suse.de>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      89b831ef
  31. 13 9月, 2005 2 次提交
    • J
      [PATCH] x86-64: Fix CFI information · 7effaa88
      由 Jan Beulich 提交于 
      Being the foundation for reliable stack unwinding, this fixes CFI unwind
annotations in many low-level x86_64 routines, plus a config option
(available to all architectures, and also present in the previously sent
patch adding such annotations to i386 code) to enable them separatly
rather than only along with adding full debug information.
Signed-off-by: NJan Beulich <jbeulich@novell.com>
Signed-off-by: NAndi Kleen <ak@suse.de>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      7effaa88
    • A
      [PATCH] x86-64: Make remote TLB flush more scalable · e5bc8b6b
      由 Andi Kleen 提交于 
      Instead of using a global spinlock to protect the state
of the remote TLB flush use a lock and state for each sending CPU.

To tell the receiver where to look for the state use 8 different
call vectors.  Each CPU uses a specific vector to trigger flushes on other
CPUs. Depending on the received vector the target CPUs look into
the right per cpu variable for the flush data.

When the system has more than 8 CPUs they are hashed to the 8 available
vectors. The limited global vector space forces us to this right now.
In future when interrupts are split into per CPU domains this could be
fixed, at the cost of needing more IPIs in flat mode.

Also some minor cleanup in the smp flush code and remove some outdated
debug code.

Requires patch to move cpu_possible_map setup earlier.
Signed-off-by: NAndi Kleen <ak@suse.de>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      e5bc8b6b
  33. 10 9月, 2005 1 次提交
  35. 08 9月, 2005 1 次提交
  37. 29 7月, 2005 2 次提交
  39. 17 5月, 2005 1 次提交
  41. 01 5月, 2005 1 次提交
  43. 17 4月, 2005 6 次提交