1. 14 4月, 2016 5 次提交
  2. 11 4月, 2016 1 次提交
    • K
      ARM: DRA7: clockdomain: Implement timer workaround for errata i874 · 1cbabcb9
      Keerthy 提交于
      Errata Title:
      i874: TIMER5/6/7/8 interrupts not propagated
      
      Description:
      When TIMER5, TIMER6, TIMER7, or TIMER8 clocks are enabled
      (CM_IPU_TIMER5/6/7/8_CLKCTRL[0:1]MODULEMODE=0x2:ENABLE) and the CD-IPU
      is in HW_AUTO mode (CM_IPU_CLKSTCTRL[0:1]CLKTRCTRL=0x3:HW_AUTO) the
      corresponding TIMER will continue counting, but enabled interrupts
      will not be propagated to the destinations (MPU, DSP, etc) in the
      SoC until the TIMER registers are accessed from the CPUs (MPU, DSP
      etc.). This can result in missed timer interrupts.
      
      Workaround:
      In order for TIMER5/6/7/8 interrupts to be propagated and serviced
      correctly the CD_IPU domain should be set to SW_WKUP mode
      (CM_IPU_CLKSTCTRL[0:1]CLKTRCTRL=0x2:SW_WKUP).
      
      The above workaround is achieved by switching the IPU clockdomain
      flags from HWSUP_SWSUP to SWSUP only.
      Signed-off-by: NKeerthy <j-keerthy@ti.com>
      Signed-off-by: NSuman Anna <s-anna@ti.com>
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      1cbabcb9
  3. 09 4月, 2016 3 次提交
  4. 08 4月, 2016 2 次提交
    • N
      ARM: OMAP: DRA7: Provide proper class to omap2_set_globals_tap · ec490f6f
      Nishanth Menon 提交于
      When commit 06c2d368 ("ARM: OMAP: DRA7: Make use of omap_revision
      information for soc_is* calls") introduced SoC check using
      omap_revision, it missed providing DRA7 as class for initializing
      the omap_version variable. Without doing this, soc_is_dra7xx() will
      fail and as a result, omap4_pm_init_early never initializes the dra7
      erratum for CPU power state. This causes the suspend path to fail
      on DRA7 devices.
      
      Fixes: 06c2d368 ("ARM: OMAP: DRA7: Make use of omap_revision information for soc_is* calls")
      Signed-off-by: NNishanth Menon <nm@ti.com>
      Tested-by: NKeerthy <j-keerthy@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      ec490f6f
    • N
      ARM: OMAP: DRA7: wakeupgen: Skip SAR save for wakeupgen · c783e6fd
      Nishanth Menon 提交于
      DRA7 has no SAR region for automated save and restore of wakeupgen,
      which does not make real since the SoC really does not do legacy OFF
      mode anymore. Further wakeupgen should never loose context in CSWR
      retention mode for MPU domain on DRA7 since that is the deepest state
      we will enter.
      
      So, just skip, instead of oopsing as follows while attemptint to enter
      suspend on BeagleBoard-X15.
      [   55.589771] Unable to handle kernel paging request at virtual address 00002684
      [   55.589771] pgd = ec69c000
      [...]
      [   55.589771] [<c0123cc8>] (irq_notifier) from [<c015ad70>] (notifier_call_chain+0x4c/0x8c)
      [   55.589771] [<c015ad70>] (notifier_call_chain) from [<c021469c>] (cpu_cluster_pm_enter+0x2c/0x78)
      [   55.589771] [<c021469c>] (cpu_cluster_pm_enter) from [<c0514508>] (syscore_suspend+0xb8/0x31c)
      [   55.589771] [<c0514508>] (syscore_suspend) from [<c0197d24>] (suspend_devices_and_enter+0x308/0x9e4)
      [   55.589771] [<c0197d24>] (suspend_devices_and_enter) from [<c0198a40>] (pm_suspend+0x640/0x75c)
      [   55.589771] [<c0198a40>] (pm_suspend) from [<c0196bcc>] (state_store+0x64/0xb8)
      [   55.589771] [<c0196bcc>] (state_store) from [<c0307914>] (kernfs_fop_write+0xc0/0x1bc)
      [   55.589771] [<c0307914>] (kernfs_fop_write) from [<c028ac80>] (__vfs_write+0x1c/0xd8)
      [   55.589771] [<c028ac80>] (__vfs_write) from [<c028bb70>] (vfs_write+0x90/0x16c)
      [   55.589771] [<c028bb70>] (vfs_write) from [<c028c890>] (SyS_write+0x44/0x9c)
      [   55.589771] [<c028c890>] (SyS_write) from [<c0107840>] (ret_fast_syscall+0x0/0x1c)
      [...]
      Signed-off-by: NNishanth Menon <nm@ti.com>
      Tested-by: NKeerthy <j-keerthy@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      c783e6fd
  5. 03 4月, 2016 9 次提交
  6. 02 4月, 2016 20 次提交