Add a new field to provide the mode supported by the module.
The mode will control the way mandatory clocks are managed by the PRCM.

  0 : Module is temporarily disabled by SW. OCP access to module are stalled.
      Can be used to change timing parameter of GPMC module.
  1 : Module is managed automatically by HW according to clock domain
      transition. A clock domain sleep transition put module into idle.
      A wakeup domain transition put it back into function.
      If CLKTRCTRL=3, any OCP access to module is always granted.
      Module clocks may be gated according to the clock domain state.
  2 : Module is explicitly enabled. Interface clock (if not used for
      functions) may be gated according to the clock domain state.
      Functional clocks are guarantied to stay present. As long as
      in this configuration, power domain sleep transition cannot happen.

Some modules will have a modulemode initialized at 1 (HWCTRL) by default.
This is the case for interconnect and simple module like GPIO, WDT, MAILBOX.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Add a 'context_offs' entry in the prcm.omap4 structure to all
IPs when applicable.
The offset will be used to retrieve the per module context lost
information now available on OMAP4.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The new prminst_xxx accessors based on partition and offset
is now used, so removed all the previous prcm_xxx accessors.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: remove fn prototypes also]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The warm reset function was still using the obsolete API.
Replace it by the new one and move the file to the proper c file.

Change the function names to stick to the file convention as
suggested by Paul Walmsley <paul@pwsan.com>:
prm_xxx -> prminst_xxx
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The RSTCTRL register was accessed using an absolute address.
The usage of hardcoded macros to calculate virtual address from physical
one should be avoided as much as possible.
The usage of an offset will allow future improvement like migration from
the current architecture code toward a module driver.

Update prm_xxx accessors, move definition to the proper header file and
update copyrights.
Change the s16 register offset parameter to u16.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: use '_prminst_' in function names that are part of the
 prminst44xx.c file]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

It is mandatory to wait for a module to be in disabled state before
potentially disabling source clock or re-asserting a reset.

omap_hwmod_idle and omap_hwmod_shutdown does not wait for
the module to be fully idle.

Add a cm_xxx accessor to wait the clkctrl idle status to be disabled.
Fix hwmod_[idle|shutdown] to use this API.

Based on Rajendra's initial patch.

Please note that most interconnects hwmod will return one timeout because
it is impossible for them to be in idle since the processor is accessing
the registers though the interconnect.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Todd Poynor <toddpoynor@google.com>
[paul@pwsan.com: move cpu_is_*() tests to the top of _wait_target_disable();
 incorporate some feedback from Todd]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The CLKCTRL register was accessed using an absolute address.
The usage of hardcoded macros to calculate virtual address from physical
one should be avoided as much as possible.
The usage of a offset will allow future improvement like migration from
the current architecture code toward a module driver.

Update cm_xxx accessor, move definition to the proper header file and
update copyrights.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Todd Poynor <toddpoynor@google.com>
[paul@pwsan.com: renamed 'omap4_cm_' fns to 'omap4_cminst_'; removed empty
 fn prototype section from cm44xx.h; incorporated comments from Todd;
 documented some functions]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

At boot time, lookup the clkdm_name to get the clkdm
structure pointer for further usage.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

In OMAP PRCM terminology, the clock domain is defined as a group of IPs
that share some clocks and most of the time an interface clock.
Every IP does belong to a clockdomain.
For the moment the clock domain attribute is affected to a clock node.
The issue with that approach, is that a clock might or not belong to a
clock domain. Moreover during module transition, it is up to a module
to handle properly the clock domain state and not to a clock node.

Create a clkdm_name attribute to provide this information per hwmod.

Populate this attribute for every OMAP4 hwmod entries.

Future cleanup series with remove that information from the OMAP4 clock
when it is relevant.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: fix the mpuss_clkdm name]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Merge branches 'powerdomain_fixes_3.1', 'hardware_workarounds_3.1', 'hwmod_dss_fix_3.1' and 'i2c_fixes_3.1' into prcm-fixes-3.1

The sequence of _ocp_softreset doesn't work for i2c. The i2c module has a
special sequence to reset the module. The sequence is
 - Disable the I2C.
 - Write to SOFTRESET bit.
 - Enable the I2C.
 - Poll on the RESETDONE bit.
The sequence is implemented as a function and the i2c_class is updated with
the correct 'reset' pointer.  omap_hwmod_softreset function is implemented
which triggers the softreset by writing into sysconfig register. On following
this sequence, i2c module resets properly and timeouts are not seen.

Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Signed-off-by: NAvinash.H.M <avinashhm@ti.com>
[paul@pwsan.com: combined this patch with a patch to remove
 HWMOD_INIT_NO_RESET from the 44xx hwmod flags; change register
 offset conditional code to use the IP block revision; minor code
 cleanup]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

This adds the new functionality flags for omap i2c unit to all OMAP2
hwmod definitions

Cc: patches@linaro.org
Cc: Ben Dooks <ben-linux@fluff.org>
Reported-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NAndy Green <andy.green@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Since we cannot trust (or even reliably find) the OMAP I2C
peripheral unit's own revision register, we must inform the
OMAP i2c driver of which IP version it is running on.  We
do this by tagging the omap_hwmod_class for i2c on all the
OMAP2+ platform / cpu specific hwmod init and passing it up
to the driver (next patches).

Cc: patches@linaro.org
Cc: Ben Dooks <ben-linux@fluff.org>
Reported-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NAndy Green <andy.green@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

These represent the 8 kinds of implementation functionality
that up until now were inferred by the 16 remaining cpu_...()
tests in the omap i2c driver.

Changed to use BIT() as suggested by Balaji T Krishnamoorthy.

Cc: patches@linaro.org
Cc: Ben Dooks <ben-linux@fluff.org>
Reported-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NAndy Green <andy.green@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

These represent the two kinds of (incompatible) OMAP I2C
peripheral unit in use so far.

The constants are in linux/i2c-omap.h so the omap i2c driver can have
them too.

Cc: patches@linaro.org
Cc: Ben Dooks <ben-linux@fluff.org>
Reported-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NAndy Green <andy.green@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

As part of removing cpu_...() from the OMAP I2C driver, we need to
convert the CPU tests into functionality flags that are set by
hwmod class in the same way the IP revision is.

More flags are needed than will fit in the existing u8 flags
member of omap_i2c_dev_attr.

These flags can refer to options inside the IP block but they are
most needed for information about cpu implementation specific
options that are not part of the IP block itself.  For example,
how the CPU data bus is wired to the IP block databus differs
between OMAP cpus and affects how you must shift the address in
the IP block, but is not a feature of the IP block itself.

Cc: patches@linaro.org
Cc: Ben Dooks <ben-linux@fluff.org>
Reported-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NAndy Green <andy.green@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Peter Maydell noticed when running under QEMU he was getting
errors reporting 32-bit access to I2C peripheral unit registers
that are documented to be 8 or 16-bit only[1][2]

The I2C driver is blameless as it wraps its accesses in a
function using __raw_writew and __raw_readw, it turned out it
is the hwmod stuff.

However the hwmod code already has a flag to force a
perhipheral unit to only be accessed using 16-bit operations.

This patch applies the 16-bit only flag to the 2430,
OMAP3xxx and OMAP44xx hwmod structs.  2420 was already
correctly marked up as 16-bit.

The 2430 change will need testing by TI as arranged
in the comments to the previous patch version.

When the 16-bit flag is or-ed with other flags, it is placed
first as requested in comments.

[1] OMAP4430 Technical reference manual section 23.1.6.2
[2] OMAP3530 Techincal reference manual section 18.6

Cc: patches@linaro.org
Cc: Ben Dooks <ben-linux@fluff.org>
Reported-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NAndy Green <andy.green@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Currently using pm_runtime with DSS requires the DSS driver to enable
the DSS functional clock before calling pm_runtime_get(). That makes it
impossible to use pm_runtime in DSS as it is meant to be used, with
pm_runtime callbacks.

This patch changes the hwmod database for OMAP4 so that enabling the
hwmod via pm_runtime will also enable the DSS functional clock, allowing
us to use pm_runtime properly in DSS driver.

The DSS HWMOD side is not really correct, not before nor after this
patch, and getting DSS to retention will probably not work currently.
However, it is not supported in the mainline kernel anyway, so this
won't break anything.

So this patch allows us to write the pm_runtime adaptation for the DSS
driver the way it should be done, and the HWMOD/PM side can be fixed
later.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

On OMAP4430 devices, because of boot ROM code bug, MPU OFF state can't
be attempted independently. When coming out of MPU OFF state, ROM code
disables the clocks of IVAHD, TESLA which is not desirable. Hence the
MPU OFF state is not usable on OMAP4430 devices.

OMAP4460 onwards, MPU OFF state will be descoped completely because
the DDR firewall falls in MPU power domain. When the MPU hit OFF state,
DDR won't be accessible for other initiators. The deepest state supported
is open switch retention (OSWR) just like CORE and PER PD on OMAP4430.

So in summary MPU power domain OFF state is not supported on OMAP4
and onwards designs. Thanks to new PRCM design, device off mode can
still be achieved with power domains hitting OSWR state.
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
[b-cousson@ti.com: Fix changelog typos]
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

On OMAP4, CPU accesses on unmapped addresses are redirected to GPMC by
L3 interconnect. Because of CPU speculative nature, such accesses are
possible which can lead to indirect access to GPMC and if it's clock is
not running, it can result in hang/abort on the platform.

Above makes access to GPMC unpredictable during the execution, so it's
module mode needs to be kept under hardware control instead of software
control.
Since the auto gating is supported for GPMC, there isn't any power impact
because of this change.

The issue was un-covered with security middleware running along with HLOS.
In this case GPMC had a valid MMU descriptor on secure side where as HLOS
didn't map the GMPC because it isn't being used.
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
[b-cousson@ti.com: Update subject and fix typos in the changelog]
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Since ES2.0, the core ocmram does not support a different state
than the main power domain anymore during both ON and RET power
domain state.
Since PM is not supported at all in ES1.0, update the common
structure.

LOWPOWERSTATECHANGE is supported by the cefuse power domain but
the flag was missing.
Add the PWRDM_HAS_LOWPOWERSTATECHANGE in flags field.

Update the TI copyright date to 2011.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
[paul@pwsan.com: moved the indentation changes to a different patch set]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

sleep_switch which is initialised to 0 in omap_set_pwrdm_state
happens to be a valid sleep_switch type (FORCEWAKEUP_SWITCH)
which are defined as:

 #define FORCEWAKEUP_SWITCH      0
 #define LOWPOWERSTATE_SWITCH    1

This causes the function to wrongly program some clock domains
even when the Powerdomain is in ON state.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Acked-by: NKevin Hilman <khilman@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Add missing DSS optional clocks to HWMOD data for OMAP4xxx.

Add HWMOD_CONTROL_OPT_CLKS_IN_RESET flag for dispc to fix dispc reset.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
[b-cousson@ti.com: Remove a comment and update the subject]
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
[paul@pwsan.com: removed DSS "fck" role and some clkdev aliases at Tomi's
 request]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Merge branches 'dmtimer_precleanup_3.1', 'hwmod_core_cleanup_a_3.1', 'combine_common_hwmod_3.1', 'omap4_hwmod_data_cleanup_a_3.1', 'clock_cleanup_a_3.1', 'prcm_cleanup_a_3.1', 'omap_pm_cleanup_3.1' and 'omap_device_cleanup_3.1' into prcm-cleanup-3.1

UNIPRO was removed from OMAP4 devices from ES2.0 onwards.
Since this IP was anyway non-functional and not supported,
it is best to remove it completely.
Signed-off-by: NJon Hunter <jon-hunter@ti.com>
[b-cousson@ti.com: Update the changelog]
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
[paul@pwsan.com: split PRCM header file changes into a separate patch]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

McASP2, 3 and MMC6 modules are not present in the OMAP4 family.
Remove the fclk and the clksel related to these nodes.
Rename the references that were potentially re-used in order nodes.

Remove related macros in prcm header files.

Update TI copyright date.
Signed-off-by: NJon Hunter <jon-hunter@ti.com>
[b-cousson@ti.com: Update the patch according to autogen output]
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
[paul@pwsan.com: split PRCM data changes into a separate patch]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The current code base is not linking with the OMAP_PM_NONE
option set.
Since the option OMAP_PM_NOOP provides a no-op/debug layer,
OMAP_PM_NONE can be removed.
OMAP_PM_NOOP is enabled by default by Kconfig.
Signed-off-by: NJean Pihet <j-pihet@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The omap_device layer currently has two ways of getting an omap_device
pointer from a platform_device pointer.

Replace current usage of _find_by_pdev() with to_omap_device() since
to_omap_device() is more familiar to the existing to_platform_device()
used when getting a platform_device pointer from a struct device pointer.

Cc: Felipe Balbi <balbi@ti.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>
Reviewed-by: NFelipe Balbi <balbi@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

MPUSS was renamed MPU and L3_D2D D2D.
The rename will slightly change the order of the structure
and thus generate some structures moves.

Add a comment and remove a comma.

Update Copyright for TI and Nokia and add back Paul
in the author list.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Some maros were not well aligned. Re-align them.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The restore part of the CM is an alias of some regular registers
used only during the SAR restore to facilate the dma to write
a contiguous set of registers.
The registers should never be used by the SW, only the original
register have to be used.

Remove them from cmX_44xx.h files to avoid anybody to use them by
mistake.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Indent flags to be aligned with other fields.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
[paul@pwsan.com: split this patch from an earlier patch by Benoît;
 edited commit message]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The following commit introduced new macros to define an offset
per clock domain in an instance.

commit e4156ee5

    OMAP4: CM instances: add clockdomain register offsets

The PRM contains only two clock controls management entities:
EMU and WKUP.
Remove the other ones.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

A couple of macros were wrongly changed during the _MOD to _INST
rename done in the following commit:

  OMAP4: PRCM: rename _MOD macros to _INST
  cdb54c44

Fix them to their original name.

Some CM and PRM instances were not well aligned. Align them.

Remove one blank line in cm2_44xx.h to align the output with
the other (cm1_44xx.h, prm44xx.h) files.

Update header copyright date.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The DPLL USB can generate higher speed (x2) than the regular ones.
The max multiplication value is then twice the previous value.

Fix both max_mult and max_div with that correct values.

Change the max_div variable type to u16 to allow storing up to 256.

Replace as well the define with the value to avoid
unneeded indirection and provide a better readability.

Remove the defines that become useless.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

A couple of fieds were edited manually and thus do not stick
to the template used by the generator and by other structures.

Move them to the correct location.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
[paul@pwsan.com: dropped the UNIPRO changes since those will be removed
 in a later patch]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

usb_host_fs_fck does have a clkdev mapping with "usbhs-omap.0"
and "fs_fck" alias used by the driver.
The entry with NULL dev is thus not needed anymore.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Felipe Balbi <balbi@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The USB DPLL is a J-Type DPLL with the sddiv extra parameter.  Add it
in USB DPLL.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
[paul@pwsan.com: dropped UNIPRO change since it is removed in a later patch]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The interconnect modules were using a slightly different layout than
the regular modules.
Align the layout for better consitency.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Fix .prcm alignement and usb_otg_hs class and hwmod structures.

Add a couple of more potential hwmods in the comment.
Remove hsi, since it is already included in the data.

Remove one blank line.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>