- 24 4月, 2013 2 次提交
-
-
由 Christian König 提交于
Not needed and seems to cause some problems. Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Christian König 提交于
v2: not only raise the clocks on VCPU boot, but also on IB test. v3: agd5f: fix r600_uvd_init return value. fixes: https://bugs.freedesktop.org/show_bug.cgi?id=63730Signed-off-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 09 4月, 2013 4 次提交
-
-
由 Alex Deucher 提交于
Updated to the preferred programming sequence. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Alex Deucher 提交于
Avoid confusion with the *REG32_P mask macro. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Christian König 提交于
Just everything needed to decode videos using UVD. v6: just all the bugfixes and support for R7xx-SI merged in one patch v7: UVD_CGC_GATE is a write only register, lockup detection fix v8: split out VRAM fallback changes, remove support for RV770, add support for HEMLOCK, add buffer sizes checks Signed-off-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Alex Deucher 提交于
Add a per-asic MC (memory controller) mask which holds the mak address mask the asic is capable of. Use this when calculating the vram and gtt locations rather using asic specific functions or limiting everything to 32 bits. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 08 3月, 2013 1 次提交
-
-
由 Alex Deucher 提交于
The MC is mostly likely busy (e.g., display requests), not hung so no need to reset it. Doing an MC reset is tricky and not particularly reliable. Fixes hangs in certain cases. Reported-by: NJosh Boyer <jwboyer@gmail.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 20 2月, 2013 2 次提交
-
-
由 Alex Deucher 提交于
Cleans up the code for future asics v2: rebase, fix some missing radeon_asic updates Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Alex Deucher 提交于
This is required to get the reference clock used by the gfx engine for things like timestamps. Fixes support for GL extensions the use timestamps on certain boards. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 01 2月, 2013 6 次提交
-
-
由 Alex Deucher 提交于
The MC isn't part of the GPU per se. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Alex Deucher 提交于
fetch the reset mask and check if the relevant ring flags are set to determine whether the ring is hung or not. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Alex Deucher 提交于
It's better to halt the engines before we disable the MC. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Alex Deucher 提交于
When we attempt the reset the GPU, look at the status registers to determine what blocks need to be reset. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Alex Deucher 提交于
Update the code to better match the recommended programming sequence for soft reset. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Alex Deucher 提交于
Used by all asic families from r600+. Flag for the vbios and later instances of the driver that the GPU is hung. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 31 1月, 2013 1 次提交
-
-
由 Mikko Tiihonen 提交于
Make sure at least one RB is enabled in r6xx_remap_render_backend() to avoid an division by zero in some corner cases. See: https://bugzilla.redhat.com/show_bug.cgi?id=892233Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
-
- 25 1月, 2013 1 次提交
-
-
由 Michel Dänzer 提交于
Fixes GPU hang during DMA ring IB test. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59672Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 15 1月, 2013 1 次提交
-
-
由 Alex Deucher 提交于
Fixes a hard lock in the gpu reset code after the rework for DMA support (0ecebb9e "drm/radeon: switch to a finer grained reset for evergreen") due to not bailing before the MC shutdown if the relevant engines are idle. Discussion: http://lists.freedesktop.org/archives/dri-devel/2013-January/032985.htmlReported-by: NEldad Zack <eldad@fogrefinery.com> Tested-by: NEldad Zack <eldad@fogrefinery.com> Acked-by: NPaul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 04 1月, 2013 5 次提交
-
-
由 Alex Deucher 提交于
- r6xx actually uses a slightly different packet format, although both formats seem to work ok. - r7xx doesn't have the count multiple of 2 limitation. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Alex Deucher 提交于
No change in functionality as we currently set all the reset flags. Reviewed-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Jerome Glisse 提交于
This try to reset the dma engine when performing gpu reset. Hopefully bringing back the gpu dma engine in sane state. v2: agd5f: fix dma reset on cayman/TN, add support for SI Signed-off-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Jerome Glisse 提交于
To help debug dma related lockup. v2: agd5f: update SI as well Signed-off-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Alex Deucher 提交于
count must be a multiple of 2. Fixes crashes on R6xx chips reported by a number of people. Cc: Borislav Petkov <bp@alien8.de> Cc: Markus Trippelsdorf <markus@trippelsdorf.de> Reviewed-by: NJerome Glisse <jglisse@redhat.com> Tested-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 13 12月, 2012 1 次提交
-
-
由 Jerome Glisse 提交于
The dma ring can't write to register thus have to write to memory its fence value. This ensure that it doesn't try to use scratch register for dma ring fence driver. Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=58166Signed-off-by: NJerome Glisse <jglisse@redhat.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 11 12月, 2012 1 次提交
-
-
由 Alex Deucher 提交于
Uses the new multi-ring infrastucture. 6xx/7xx has a single async DMA ring. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 20 11月, 2012 1 次提交
-
-
由 Akinobu Mita 提交于
Use hweight32 instead of counting for each bit Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com> Cc: David Airlie <airlied@linux.ie> Cc: dri-devel@lists.freedesktop.org Signed-off-by: NDave Airlie <airlied@redhat.com>
-
- 16 10月, 2012 1 次提交
-
-
由 Alex Deucher 提交于
If so, skip enabling it to save time. v2: coding style fixes Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 03 10月, 2012 1 次提交
-
-
由 David Howells 提交于
Convert #include "..." to #include <path/...> in drivers/gpu/. Signed-off-by: NDavid Howells <dhowells@redhat.com> Acked-by: NDave Airlie <airlied@redhat.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NThomas Gleixner <tglx@linutronix.de> Acked-by: NPaul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by: NDave Jones <davej@redhat.com>
-
- 27 9月, 2012 1 次提交
-
-
由 Michel Dänzer 提交于
Restructure the code to jump out via labels instead of directly returning early. Also make error reporting consistent across all hardware generations. Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com> Reviewed-by: NSimon Kitching <skitching@vonos.net> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 21 9月, 2012 3 次提交
-
-
由 Lauri Kasanen 提交于
Let's allow GCC to optimize better. This exposed some five unused functions, but this patch doesn't remove them. Signed-off-by: NLauri Kasanen <cand@gmx.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Christian König 提交于
Store a reference to the VM into the IB structure, that makes calculating the IBs address a bit less complicated. Signed-off-by: NChristian König <deathsimple@vodafone.de> Reviewed-by: NJerome Glisse <jglisse@redhat.com>
-
由 Alex Deucher 提交于
It was only used for dynpm, but has been replaced with a better implementation using fences. Remove it. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 13 8月, 2012 1 次提交
-
-
由 Marek Olšák 提交于
Returns a snapshot of the GPU clock counter. Needed for certain OpenGL extensions. v2: agd5f - address Jerome's comments - add function documentation Signed-off-by: NMarek Olšák <maraeo@gmail.com> Reviewed-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 20 7月, 2012 2 次提交
-
-
由 Dave Airlie 提交于
This check the root ports supported link speeds and enables GEN2 mode if the 5.0 GT link speed is available. The first 3.0 cards are SI so they will probably need more investigation. Signed-off-by: NDave Airlie <airlied@redhat.com>
-
由 Jerome Glisse 提交于
Print various CP register that have valuable informations regarding GPU lockup. Signed-off-by: NJerome Glisse <jglisse@redhat.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
-
- 18 7月, 2012 3 次提交
-
-
由 Alex Deucher 提交于
Add support for using memory buffers rather than scratch registers. Some rings may not be able to write to scratch registers. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com>
-
由 Alex Deucher 提交于
Just store the index in the ring structure. Idea taken from one of Jerome's wip rptr patches. Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com>
-
由 Christian König 提交于
Const IBs are executed on the CE not the CP, so we can't fence them in the normal way. So submit them directly before the IB instead, just as the documentation says. v2: keep the extra documentation Signed-off-by: NChristian König <deathsimple@vodafone.de> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 17 7月, 2012 2 次提交
-
-
由 Christian König 提交于
Before emitting any indirect buffer, emit the offset of the next valid ring content if any. This allow code that want to resume ring to resume ring right after ib that caused GPU lockup. v2: use scratch registers instead of storing it into memory v3: skip over the surface sync for ni and si as well v4: use SET_CONFIG_REG instead of PACKET0 Signed-off-by: NJerome Glisse <jglisse@redhat.com> Signed-off-by: NChristian König <deathsimple@vodafone.de> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Christian König 提交于
Making it easier to control when it is executed. Signed-off-by: NChristian König <deathsimple@vodafone.de> Reviewed-by: NMichel Dänzer <michel.daenzer@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
-