ARM: sunxi: add PLL4 support

This commit adds the PLL4 definition to the sun4i, sun5i and sun7i
device trees. PLL4 is compatible with PLL1.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

arch/arm/boot/dts/sun4i-a10.dtsi

@@ -66,6 +66,13 @@ pll1: pll1@01c20000 {
 			clocks = <&osc24M>;
 		};
 
+		pll4: pll4@01c20018 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-pll1-clk";
+			reg = <0x01c20018 0x4>;
+			clocks = <&osc24M>;
+		};
+
 		/* dummy is 200M */
 		cpu: cpu@01c20054 {
 			#clock-cells = <0>;

arch/arm/boot/dts/sun5i-a10s.dtsi

@@ -63,6 +63,13 @@ pll1: pll1@01c20000 {
 			clocks = <&osc24M>;
 		};
 
+		pll4: pll4@01c20018 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-pll1-clk";
+			reg = <0x01c20018 0x4>;
+			clocks = <&osc24M>;
+		};
+
 		/* dummy is 200M */
 		cpu: cpu@01c20054 {
 			#clock-cells = <0>;

arch/arm/boot/dts/sun5i-a13.dtsi

@@ -67,6 +67,13 @@ pll1: pll1@01c20000 {
 			clocks = <&osc24M>;
 		};
 
+		pll4: pll4@01c20018 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-pll1-clk";
+			reg = <0x01c20018 0x4>;
+			clocks = <&osc24M>;
+		};
+
 		/* dummy is 200M */
 		cpu: cpu@01c20054 {
 			#clock-cells = <0>;

arch/arm/boot/dts/sun7i-a20.dtsi

@@ -62,6 +62,13 @@ pll1: pll1@01c20000 {
 			clocks = <&osc24M>;
 		};
 
+		pll4: pll4@01c20018 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-pll1-clk";
+			reg = <0x01c20018 0x4>;
+			clocks = <&osc24M>;
+		};
+
 		/*
 		 * This is a dummy clock, to be used as placeholder on
 		 * other mux clocks when a specific parent clock is not