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提交 aa2d58c3 编写于 作者: B Ben Skeggs
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drm/gf100-/gr: unhardcode bundle cb config 

Should be the same values as before, except:

GF117 has smaller buffer allocated, as per register setup.
GK20A now uses values from Tegra driver, not GK104's.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
上级 694c6caf
隐藏空白更改
内联 并排
Showing with 100 addition and 41 deletion
drivers/gpu/drm/nouveau/core/engine/graph/ctxgk110b.c
浏览文件 @ aa2d58c3
...@@ -91,4 +91,8 @@ gk110b_grctx_oclass = &(struct nvc0_grctx_oclass) { ...@@ -91,4 +91,8 @@ gk110b_grctx_oclass = &(struct nvc0_grctx_oclass) {
.ppc = nvf0_grctx_pack_ppc, .ppc = nvf0_grctx_pack_ppc,
.icmd = nvf0_grctx_pack_icmd, .icmd = nvf0_grctx_pack_icmd,
.mthd = nvf0_grctx_pack_mthd, .mthd = nvf0_grctx_pack_mthd,
.bundle = nve4_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x600,
}.base; }.base;
drivers/gpu/drm/nouveau/core/engine/graph/ctxgk20a.c
浏览文件 @ aa2d58c3
...@@ -50,4 +50,8 @@ gk20a_grctx_oclass = &(struct nvc0_grctx_oclass) { ...@@ -50,4 +50,8 @@ gk20a_grctx_oclass = &(struct nvc0_grctx_oclass) {
.ppc = nve4_grctx_pack_ppc, .ppc = nve4_grctx_pack_ppc,
.icmd = nve4_grctx_pack_icmd, .icmd = nve4_grctx_pack_icmd,
.mthd = gk20a_grctx_pack_mthd, .mthd = gk20a_grctx_pack_mthd,
.bundle = nve4_grctx_generate_bundle,
.bundle_size = 0x1800,
.bundle_min_gpm_fifo_depth = 0x62,
.bundle_token_limit = 0x100,
}.base; }.base;
drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c
浏览文件 @ aa2d58c3
...@@ -858,10 +858,26 @@ gm107_grctx_pack_ppc[] = { ...@@ -858,10 +858,26 @@ gm107_grctx_pack_ppc[] = {
* PGRAPH context implementation * PGRAPH context implementation
******************************************************************************/ ******************************************************************************/
static void
gm107_grctx_generate_bundle(struct nvc0_grctx *info)
{
const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth,
impl->bundle_size / 0x20);
const u32 token_limit = impl->bundle_token_limit;
const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
const int s = 8;
const int b = mmio_vram(info, impl->bundle_size, (1 << s), access);
mmio_refn(info, 0x408004, 0x00000000, s, b);
mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b);
mmio_refn(info, 0x418e24, 0x00000000, s, b);
mmio_refn(info, 0x418e28, 0x80000000 | (impl->bundle_size >> s), 0, b);
mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit);
}
static void static void
gm107_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) gm107_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
{ {
mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x200000, 0x1000, NV_MEM_ACCESS_RW); mmio_data(0x200000, 0x1000, NV_MEM_ACCESS_RW);
...@@ -872,13 +888,6 @@ gm107_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) ...@@ -872,13 +888,6 @@ gm107_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
mmio_list(0x4064cc, 0x80000000, 0, 0); mmio_list(0x4064cc, 0x80000000, 0, 0);
mmio_list(0x418e30, 0x80000000, 0, 0); mmio_list(0x418e30, 0x80000000, 0, 0);
mmio_list(0x408004, 0x00000000, 8, 0);
mmio_list(0x408008, 0x80000030, 0, 0);
mmio_list(0x418e24, 0x00000000, 8, 0);
mmio_list(0x418e28, 0x80000030, 0, 0);
mmio_list(0x4064c8, 0x018002c0, 0, 0);
mmio_list(0x418810, 0x80000000, 12, 2); mmio_list(0x418810, 0x80000000, 12, 2);
mmio_list(0x419848, 0x10000000, 12, 2); mmio_list(0x419848, 0x10000000, 12, 2);
mmio_list(0x419c2c, 0x10000000, 12, 2); mmio_list(0x419c2c, 0x10000000, 12, 2);
...@@ -934,6 +943,7 @@ gm107_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) ...@@ -934,6 +943,7 @@ gm107_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
nv_wr32(priv, 0x404154, 0x00000000); nv_wr32(priv, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->mods(priv, info); oclass->mods(priv, info);
oclass->unkn(priv); oclass->unkn(priv);
...@@ -988,4 +998,8 @@ gm107_grctx_oclass = &(struct nvc0_grctx_oclass) { ...@@ -988,4 +998,8 @@ gm107_grctx_oclass = &(struct nvc0_grctx_oclass) {
.ppc = gm107_grctx_pack_ppc, .ppc = gm107_grctx_pack_ppc,
.icmd = gm107_grctx_pack_icmd, .icmd = gm107_grctx_pack_icmd,
.mthd = gm107_grctx_pack_mthd, .mthd = gm107_grctx_pack_mthd,
.bundle = gm107_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x2c0,
}.base; }.base;
drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c
浏览文件 @ aa2d58c3
...@@ -538,7 +538,6 @@ nv108_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) ...@@ -538,7 +538,6 @@ nv108_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
u32 offset; u32 offset;
int gpc; int gpc;
mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW); mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
mmio_list(0x40800c, 0x00000000, 8, 1); mmio_list(0x40800c, 0x00000000, 8, 1);
...@@ -546,11 +545,6 @@ nv108_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) ...@@ -546,11 +545,6 @@ nv108_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
mmio_list(0x419004, 0x00000000, 8, 1); mmio_list(0x419004, 0x00000000, 8, 1);
mmio_list(0x419008, 0x00000000, 0, 0); mmio_list(0x419008, 0x00000000, 0, 0);
mmio_list(0x4064cc, 0x80000000, 0, 0); mmio_list(0x4064cc, 0x80000000, 0, 0);
mmio_list(0x408004, 0x00000000, 8, 0);
mmio_list(0x408008, 0x80000030, 0, 0);
mmio_list(0x418808, 0x00000000, 8, 0);
mmio_list(0x41880c, 0x80000030, 0, 0);
mmio_list(0x4064c8, 0x00c20200, 0, 0);
mmio_list(0x418810, 0x80000000, 12, 2); mmio_list(0x418810, 0x80000000, 12, 2);
mmio_list(0x419848, 0x10000000, 12, 2); mmio_list(0x419848, 0x10000000, 12, 2);
...@@ -596,4 +590,8 @@ nv108_grctx_oclass = &(struct nvc0_grctx_oclass) { ...@@ -596,4 +590,8 @@ nv108_grctx_oclass = &(struct nvc0_grctx_oclass) {
.ppc = nv108_grctx_pack_ppc, .ppc = nv108_grctx_pack_ppc,
.icmd = nv108_grctx_pack_icmd, .icmd = nv108_grctx_pack_icmd,
.mthd = nvf0_grctx_pack_mthd, .mthd = nvf0_grctx_pack_mthd,
.bundle = nve4_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0xc2,
.bundle_token_limit = 0x200,
}.base; }.base;
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
浏览文件 @ aa2d58c3
...@@ -1020,26 +1020,34 @@ nvc0_grctx_mmio_item(struct nvc0_grctx *info, u32 addr, u32 data, ...@@ -1020,26 +1020,34 @@ nvc0_grctx_mmio_item(struct nvc0_grctx *info, u32 addr, u32 data,
nv_wr32(info->priv, addr, data); nv_wr32(info->priv, addr, data);
} }
void
nvc0_grctx_generate_bundle(struct nvc0_grctx *info)
{
const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
const int s = 8;
const int b = mmio_vram(info, impl->bundle_size, (1 << s), access);
mmio_refn(info, 0x408004, 0x00000000, s, b);
mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b);
mmio_refn(info, 0x418808, 0x00000000, s, b);
mmio_refn(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s), 0, b);
}
void void
nvc0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) nvc0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
{ {
int gpc, tpc; int gpc, tpc;
u32 offset; u32 offset;
mmio_data(0x002000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW); mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
mmio_list(0x408004, 0x00000000, 8, 0);
mmio_list(0x408008, 0x80000018, 0, 0);
mmio_list(0x40800c, 0x00000000, 8, 1); mmio_list(0x40800c, 0x00000000, 8, 1);
mmio_list(0x408010, 0x80000000, 0, 0); mmio_list(0x408010, 0x80000000, 0, 0);
mmio_list(0x418810, 0x80000000, 12, 2); mmio_list(0x418810, 0x80000000, 12, 2);
mmio_list(0x419848, 0x10000000, 12, 2); mmio_list(0x419848, 0x10000000, 12, 2);
mmio_list(0x419004, 0x00000000, 8, 1); mmio_list(0x419004, 0x00000000, 8, 1);
mmio_list(0x419008, 0x00000000, 0, 0); mmio_list(0x419008, 0x00000000, 0, 0);
mmio_list(0x418808, 0x00000000, 8, 0);
mmio_list(0x41880c, 0x80000018, 0, 0);
mmio_list(0x405830, 0x02180000, 0, 0); mmio_list(0x405830, 0x02180000, 0, 0);
...@@ -1218,6 +1226,7 @@ nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) ...@@ -1218,6 +1226,7 @@ nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
nv_wr32(priv, 0x404154, 0x00000000); nv_wr32(priv, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->mods(priv, info); oclass->mods(priv, info);
oclass->unkn(priv); oclass->unkn(priv);
...@@ -1354,4 +1363,6 @@ nvc0_grctx_oclass = &(struct nvc0_grctx_oclass) { ...@@ -1354,4 +1363,6 @@ nvc0_grctx_oclass = &(struct nvc0_grctx_oclass) {
.tpc = nvc0_grctx_pack_tpc, .tpc = nvc0_grctx_pack_tpc,
.icmd = nvc0_grctx_pack_icmd, .icmd = nvc0_grctx_pack_icmd,
.mthd = nvc0_grctx_pack_mthd, .mthd = nvc0_grctx_pack_mthd,
.bundle = nvc0_grctx_generate_bundle,
.bundle_size = 0x1800,
}.base; }.base;
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h
浏览文件 @ aa2d58c3
...@@ -39,11 +39,23 @@ struct nvc0_grctx_oclass { ...@@ -39,11 +39,23 @@ struct nvc0_grctx_oclass {
/* indirect context data, generated with icmds/mthds */ /* indirect context data, generated with icmds/mthds */
const struct nvc0_graph_pack *icmd; const struct nvc0_graph_pack *icmd;
const struct nvc0_graph_pack *mthd; const struct nvc0_graph_pack *mthd;
/* bundle circular buffer */
void (*bundle)(struct nvc0_grctx *);
u32 bundle_size;
u32 bundle_min_gpm_fifo_depth;
u32 bundle_token_limit;
}; };
static inline const struct nvc0_grctx_oclass *
nvc0_grctx_impl(struct nvc0_graph_priv *priv)
{
return (void *)nv_engine(priv)->cclass;
}
extern struct nouveau_oclass *nvc0_grctx_oclass; extern struct nouveau_oclass *nvc0_grctx_oclass;
int nvc0_grctx_generate(struct nvc0_graph_priv *); int nvc0_grctx_generate(struct nvc0_graph_priv *);
void nvc0_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *); void nvc0_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nvc0_grctx_generate_bundle(struct nvc0_grctx *);
void nvc0_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *); void nvc0_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nvc0_grctx_generate_unkn(struct nvc0_graph_priv *); void nvc0_grctx_generate_unkn(struct nvc0_graph_priv *);
void nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *); void nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *);
...@@ -64,6 +76,7 @@ extern struct nouveau_oclass *nvd9_grctx_oclass; ...@@ -64,6 +76,7 @@ extern struct nouveau_oclass *nvd9_grctx_oclass;
extern struct nouveau_oclass *nve4_grctx_oclass; extern struct nouveau_oclass *nve4_grctx_oclass;
extern struct nouveau_oclass *gk20a_grctx_oclass; extern struct nouveau_oclass *gk20a_grctx_oclass;
void nve4_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *); void nve4_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nve4_grctx_generate_bundle(struct nvc0_grctx *);
void nve4_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *); void nve4_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nve4_grctx_generate_unkn(struct nvc0_graph_priv *); void nve4_grctx_generate_unkn(struct nvc0_graph_priv *);
void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *); void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *);
......
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c
浏览文件 @ aa2d58c3
...@@ -732,19 +732,14 @@ nvc1_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) ...@@ -732,19 +732,14 @@ nvc1_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
int gpc, tpc; int gpc, tpc;
u32 offset; u32 offset;
mmio_data(0x002000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW); mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
mmio_list(0x408004, 0x00000000, 8, 0);
mmio_list(0x408008, 0x80000018, 0, 0);
mmio_list(0x40800c, 0x00000000, 8, 1); mmio_list(0x40800c, 0x00000000, 8, 1);
mmio_list(0x408010, 0x80000000, 0, 0); mmio_list(0x408010, 0x80000000, 0, 0);
mmio_list(0x418810, 0x80000000, 12, 2); mmio_list(0x418810, 0x80000000, 12, 2);
mmio_list(0x419848, 0x10000000, 12, 2); mmio_list(0x419848, 0x10000000, 12, 2);
mmio_list(0x419004, 0x00000000, 8, 1); mmio_list(0x419004, 0x00000000, 8, 1);
mmio_list(0x419008, 0x00000000, 0, 0); mmio_list(0x419008, 0x00000000, 0, 0);
mmio_list(0x418808, 0x00000000, 8, 0);
mmio_list(0x41880c, 0x80000018, 0, 0);
mmio_list(0x405830, 0x02180218, 0, 0); mmio_list(0x405830, 0x02180218, 0, 0);
mmio_list(0x4064c4, 0x0086ffff, 0, 0); mmio_list(0x4064c4, 0x0086ffff, 0, 0);
...@@ -794,4 +789,6 @@ nvc1_grctx_oclass = &(struct nvc0_grctx_oclass) { ...@@ -794,4 +789,6 @@ nvc1_grctx_oclass = &(struct nvc0_grctx_oclass) {
.tpc = nvc1_grctx_pack_tpc, .tpc = nvc1_grctx_pack_tpc,
.icmd = nvc1_grctx_pack_icmd, .icmd = nvc1_grctx_pack_icmd,
.mthd = nvc1_grctx_pack_mthd, .mthd = nvc1_grctx_pack_mthd,
.bundle = nvc0_grctx_generate_bundle,
.bundle_size = 0x1800,
}.base; }.base;
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc4.c
浏览文件 @ aa2d58c3
...@@ -100,4 +100,6 @@ nvc4_grctx_oclass = &(struct nvc0_grctx_oclass) { ...@@ -100,4 +100,6 @@ nvc4_grctx_oclass = &(struct nvc0_grctx_oclass) {
.tpc = nvc4_grctx_pack_tpc, .tpc = nvc4_grctx_pack_tpc,
.icmd = nvc0_grctx_pack_icmd, .icmd = nvc0_grctx_pack_icmd,
.mthd = nvc0_grctx_pack_mthd, .mthd = nvc0_grctx_pack_mthd,
.bundle = nvc0_grctx_generate_bundle,
.bundle_size = 0x1800,
}.base; }.base;
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c
浏览文件 @ aa2d58c3
...@@ -351,4 +351,6 @@ nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) { ...@@ -351,4 +351,6 @@ nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) {
.tpc = nvc0_grctx_pack_tpc, .tpc = nvc0_grctx_pack_tpc,
.icmd = nvc8_grctx_pack_icmd, .icmd = nvc8_grctx_pack_icmd,
.mthd = nvc8_grctx_pack_mthd, .mthd = nvc8_grctx_pack_mthd,
.bundle = nvc0_grctx_generate_bundle,
.bundle_size = 0x1800,
}.base; }.base;
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c
浏览文件 @ aa2d58c3
...@@ -184,17 +184,12 @@ nvd7_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) ...@@ -184,17 +184,12 @@ nvd7_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
u32 offset; u32 offset;
int gpc; int gpc;
mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW); mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
mmio_list(0x40800c, 0x00000000, 8, 1); mmio_list(0x40800c, 0x00000000, 8, 1);
mmio_list(0x408010, 0x80000000, 0, 0); mmio_list(0x408010, 0x80000000, 0, 0);
mmio_list(0x419004, 0x00000000, 8, 1); mmio_list(0x419004, 0x00000000, 8, 1);
mmio_list(0x419008, 0x00000000, 0, 0); mmio_list(0x419008, 0x00000000, 0, 0);
mmio_list(0x408004, 0x00000000, 8, 0);
mmio_list(0x408008, 0x80000018, 0, 0);
mmio_list(0x418808, 0x00000000, 8, 0);
mmio_list(0x41880c, 0x80000018, 0, 0);
mmio_list(0x418810, 0x80000000, 12, 2); mmio_list(0x418810, 0x80000000, 12, 2);
mmio_list(0x419848, 0x10000000, 12, 2); mmio_list(0x419848, 0x10000000, 12, 2);
...@@ -233,6 +228,7 @@ nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) ...@@ -233,6 +228,7 @@ nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
nv_wr32(priv, 0x404154, 0x00000000); nv_wr32(priv, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->mods(priv, info); oclass->mods(priv, info);
oclass->unkn(priv); oclass->unkn(priv);
...@@ -272,4 +268,6 @@ nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) { ...@@ -272,4 +268,6 @@ nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) {
.ppc = nvd7_grctx_pack_ppc, .ppc = nvd7_grctx_pack_ppc,
.icmd = nvd9_grctx_pack_icmd, .icmd = nvd9_grctx_pack_icmd,
.mthd = nvd9_grctx_pack_mthd, .mthd = nvd9_grctx_pack_mthd,
.bundle = nvc0_grctx_generate_bundle,
.bundle_size = 0x1800,
}.base; }.base;
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c
浏览文件 @ aa2d58c3
...@@ -519,4 +519,6 @@ nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) { ...@@ -519,4 +519,6 @@ nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) {
.tpc = nvd9_grctx_pack_tpc, .tpc = nvd9_grctx_pack_tpc,
.icmd = nvd9_grctx_pack_icmd, .icmd = nvd9_grctx_pack_icmd,
.mthd = nvd9_grctx_pack_mthd, .mthd = nvd9_grctx_pack_mthd,
.bundle = nvc0_grctx_generate_bundle,
.bundle_size = 0x1800,
}.base; }.base;
drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
浏览文件 @ aa2d58c3
...@@ -838,6 +838,23 @@ nve4_grctx_pack_ppc[] = { ...@@ -838,6 +838,23 @@ nve4_grctx_pack_ppc[] = {
* PGRAPH context implementation * PGRAPH context implementation
******************************************************************************/ ******************************************************************************/
void
nve4_grctx_generate_bundle(struct nvc0_grctx *info)
{
const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth,
impl->bundle_size / 0x20);
const u32 token_limit = impl->bundle_token_limit;
const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
const int s = 8;
const int b = mmio_vram(info, impl->bundle_size, (1 << s), access);
mmio_refn(info, 0x408004, 0x00000000, s, b);
mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b);
mmio_refn(info, 0x418808, 0x00000000, s, b);
mmio_refn(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s), 0, b);
mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit);
}
void void
nve4_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) nve4_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
{ {
...@@ -845,7 +862,6 @@ nve4_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) ...@@ -845,7 +862,6 @@ nve4_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
u32 offset; u32 offset;
int gpc; int gpc;
mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW); mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
mmio_list(0x40800c, 0x00000000, 8, 1); mmio_list(0x40800c, 0x00000000, 8, 1);
...@@ -853,11 +869,6 @@ nve4_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) ...@@ -853,11 +869,6 @@ nve4_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
mmio_list(0x419004, 0x00000000, 8, 1); mmio_list(0x419004, 0x00000000, 8, 1);
mmio_list(0x419008, 0x00000000, 0, 0); mmio_list(0x419008, 0x00000000, 0, 0);
mmio_list(0x4064cc, 0x80000000, 0, 0); mmio_list(0x4064cc, 0x80000000, 0, 0);
mmio_list(0x408004, 0x00000000, 8, 0);
mmio_list(0x408008, 0x80000030, 0, 0);
mmio_list(0x418808, 0x00000000, 8, 0);
mmio_list(0x41880c, 0x80000030, 0, 0);
mmio_list(0x4064c8, 0x01800600, 0, 0);
mmio_list(0x418810, 0x80000000, 12, 2); mmio_list(0x418810, 0x80000000, 12, 2);
mmio_list(0x419848, 0x10000000, 12, 2); mmio_list(0x419848, 0x10000000, 12, 2);
...@@ -967,6 +978,7 @@ nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) ...@@ -967,6 +978,7 @@ nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
nv_wr32(priv, 0x404154, 0x00000000); nv_wr32(priv, 0x404154, 0x00000000);
oclass->bundle(info);
oclass->mods(priv, info); oclass->mods(priv, info);
oclass->unkn(priv); oclass->unkn(priv);
...@@ -1018,4 +1030,8 @@ nve4_grctx_oclass = &(struct nvc0_grctx_oclass) { ...@@ -1018,4 +1030,8 @@ nve4_grctx_oclass = &(struct nvc0_grctx_oclass) {
.ppc = nve4_grctx_pack_ppc, .ppc = nve4_grctx_pack_ppc,
.icmd = nve4_grctx_pack_icmd, .icmd = nve4_grctx_pack_icmd,
.mthd = nve4_grctx_pack_mthd, .mthd = nve4_grctx_pack_mthd,
.bundle = nve4_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x600,
}.base; }.base;
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c
浏览文件 @ aa2d58c3
...@@ -816,7 +816,6 @@ nvf0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) ...@@ -816,7 +816,6 @@ nvf0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
u32 offset; u32 offset;
int gpc; int gpc;
mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW); mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
mmio_list(0x40800c, 0x00000000, 8, 1); mmio_list(0x40800c, 0x00000000, 8, 1);
...@@ -824,11 +823,6 @@ nvf0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) ...@@ -824,11 +823,6 @@ nvf0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
mmio_list(0x419004, 0x00000000, 8, 1); mmio_list(0x419004, 0x00000000, 8, 1);
mmio_list(0x419008, 0x00000000, 0, 0); mmio_list(0x419008, 0x00000000, 0, 0);
mmio_list(0x4064cc, 0x80000000, 0, 0); mmio_list(0x4064cc, 0x80000000, 0, 0);
mmio_list(0x408004, 0x00000000, 8, 0);
mmio_list(0x408008, 0x80000030, 0, 0);
mmio_list(0x418808, 0x00000000, 8, 0);
mmio_list(0x41880c, 0x80000030, 0, 0);
mmio_list(0x4064c8, 0x01800600, 0, 0);
mmio_list(0x418810, 0x80000000, 12, 2); mmio_list(0x418810, 0x80000000, 12, 2);
mmio_list(0x419848, 0x10000000, 12, 2); mmio_list(0x419848, 0x10000000, 12, 2);
...@@ -882,4 +876,8 @@ nvf0_grctx_oclass = &(struct nvc0_grctx_oclass) { ...@@ -882,4 +876,8 @@ nvf0_grctx_oclass = &(struct nvc0_grctx_oclass) {
.ppc = nvf0_grctx_pack_ppc, .ppc = nvf0_grctx_pack_ppc,
.icmd = nvf0_grctx_pack_icmd, .icmd = nvf0_grctx_pack_icmd,
.mthd = nvf0_grctx_pack_mthd, .mthd = nvf0_grctx_pack_mthd,
.bundle = nve4_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x7c0,
}.base; }.base;
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