提交 6a488979 编写于 作者: L Linus Torvalds

Merge tag 'arm-soc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

ARM: fixes for ARM platforms

Some fallout from the 3.3. merge window as well as a couple bug fixes
for older preexisting bugs that seem valid to include at this time:

* sched_clock changes broke picoxcell, fix included
* BSYM bugs causing issues with thumb2-built kernels on SMP
* Missing module.h include on msm.
* A collection of bugfixes for samsung platforms that didn't make it into
  the first pull requests.

* tag 'arm-soc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: make BSYM macro assembly only
  ARM: highbank: remove incorrect BSYM usage
  ARM: imx: remove incorrect BSYM usage
  ARM: exynos: remove incorrect BSYM usage
  ARM: ux500: add missing ENDPROC to headsmp.S
  ARM: msm: Add missing ENDPROC to headsmp.S
  ARM: versatile: Add missing ENDPROC to headsmp.S
  ARM: EXYNOS: Invert VCLK polarity for framebuffer on ORIGEN
  ARM: S3C64XX: Fix interrupt configuration for PCA935x on Cragganmore
  ARM: S3C64XX: Fix the memory mapped GPIOs on Cragganmore
  ARM: S3C64XX: Remove hsmmc1 from Cragganmore
  ARM: S3C64XX: Remove unconditional power domain disables
  ARM: SAMSUNG: Declare struct platform_device in plat/s3c64xx-spi.h
  ARM: SAMSUNG: dma-ops.h needs mach/dma.h
  ARM: SAMSUNG: Guard against multiple inclusion of plat/dma.h
  ARM: picoxcell: fix sched_clock() cleanup fallout
  ARM: msm: vreg is a module and so needs module.h
......@@ -37,8 +37,8 @@
#define THUMB(x...) x
#ifdef __ASSEMBLY__
#define W(instr) instr.w
#endif
#define BSYM(sym) sym + 1
#endif
#else /* !CONFIG_THUMB2_KERNEL */
......@@ -49,8 +49,8 @@
#define THUMB(x...)
#ifdef __ASSEMBLY__
#define W(instr) instr
#endif
#define BSYM(sym) sym
#endif
#endif /* CONFIG_THUMB2_KERNEL */
......
......@@ -36,6 +36,8 @@ pen: ldr r7, [r6]
* should now contain the SVC stack for this core
*/
b secondary_startup
ENDPROC(exynos4_secondary_startup)
.align 2
1: .long .
.long pen_release
......@@ -597,7 +597,8 @@ static struct s3c_fb_pd_win origen_fb_win0 = {
static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
.win[0] = &origen_fb_win0,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
VIDCON1_INV_VCLK,
.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
};
......
......@@ -24,7 +24,6 @@
#include <asm/cacheflush.h>
#include <asm/hardware/gic.h>
#include <asm/smp_scu.h>
#include <asm/unified.h>
#include <mach/hardware.h>
#include <mach/regs-clock.h>
......@@ -137,7 +136,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
while (time_before(jiffies, timeout)) {
smp_rmb();
__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
__raw_writel(virt_to_phys(exynos4_secondary_startup),
CPU1_BOOT_REG);
gic_raise_softirq(cpumask_of(cpu), 1);
......@@ -192,6 +191,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
__raw_writel(virt_to_phys(exynos4_secondary_startup),
CPU1_BOOT_REG);
}
......@@ -25,7 +25,6 @@
#include <linux/smp.h>
#include <asm/cacheflush.h>
#include <asm/unified.h>
#include <asm/smp_scu.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/timer-sp.h>
......@@ -76,7 +75,7 @@ void highbank_set_cpu_jump(int cpu, void *jump_addr)
#ifdef CONFIG_SMP
cpu = cpu_logical_map(cpu);
#endif
writel(BSYM(virt_to_phys(jump_addr)), HB_JUMP_TABLE_VIRT(cpu));
writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu));
__cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
HB_JUMP_TABLE_PHYS(cpu) + 15);
......
......@@ -15,7 +15,6 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/smp.h>
#include <asm/unified.h>
#define SRC_SCR 0x000
#define SRC_GPR1 0x020
......@@ -43,7 +42,7 @@ void imx_enable_cpu(int cpu, bool enable)
void imx_set_cpu_jump(int cpu, void *jump_addr)
{
cpu = cpu_logical_map(cpu);
writel_relaxed(BSYM(virt_to_phys(jump_addr)),
writel_relaxed(virt_to_phys(jump_addr),
src_base + SRC_GPR1 + cpu * 8);
}
......
......@@ -34,6 +34,7 @@ pen: ldr r7, [r6]
* should now contain the SVC stack for this core
*/
b secondary_startup
ENDPROC(msm_secondary_startup)
.align
1: .long .
......
......@@ -19,6 +19,7 @@
#include <linux/device.h>
#include <linux/init.h>
#include <linux/debugfs.h>
#include <linux/module.h>
#include <linux/string.h>
#include <mach/vreg.h>
......
......@@ -67,7 +67,7 @@ static void picoxcell_add_clocksource(struct device_node *source_timer)
static void __iomem *sched_io_base;
unsigned u32 notrace picoxcell_read_sched_clock(void)
static u32 picoxcell_read_sched_clock(void)
{
return __raw_readl(sched_io_base);
}
......
......@@ -17,7 +17,6 @@
#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <asm/smp_scu.h>
#include <asm/unified.h>
#include <mach/board-eb.h>
#include <mach/board-pb11mp.h>
......@@ -75,6 +74,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
__raw_writel(BSYM(virt_to_phys(versatile_secondary_startup)),
__raw_writel(virt_to_phys(versatile_secondary_startup),
__io_address(REALVIEW_SYS_FLAGSSET));
}
......@@ -21,5 +21,6 @@
#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8)
#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 32)
#define BANFF_PMIC_GPIO_BASE (GPIO_BOARD_START + 64)
#define MMGPIO_GPIO_BASE (GPIO_BOARD_START + 96)
#endif
......@@ -260,6 +260,7 @@ static struct platform_device crag6410_dm9k_device = {
static struct resource crag6410_mmgpio_resource[] = {
[0] = {
.name = "dat",
.start = S3C64XX_PA_XM0CSN4 + 1,
.end = S3C64XX_PA_XM0CSN4 + 1,
.flags = IORESOURCE_MEM,
......@@ -272,7 +273,7 @@ static struct platform_device crag6410_mmgpio = {
.resource = crag6410_mmgpio_resource,
.num_resources = ARRAY_SIZE(crag6410_mmgpio_resource),
.dev.platform_data = &(struct bgpio_pdata) {
.base = -1,
.base = MMGPIO_GPIO_BASE,
},
};
......@@ -328,7 +329,6 @@ static struct platform_device wallvdd_device = {
static struct platform_device *crag6410_devices[] __initdata = {
&s3c_device_hsmmc0,
&s3c_device_hsmmc1,
&s3c_device_hsmmc2,
&s3c_device_i2c0,
&s3c_device_i2c1,
......@@ -355,7 +355,7 @@ static struct platform_device *crag6410_devices[] __initdata = {
static struct pca953x_platform_data crag6410_pca_data = {
.gpio_base = PCA935X_GPIO_BASE,
.irq_base = 0,
.irq_base = -1,
};
/* VDDARM is controlled by DVS1 connected to GPK(0) */
......@@ -683,12 +683,6 @@ static struct s3c_sdhci_platdata crag6410_hsmmc2_pdata = {
.cd_type = S3C_SDHCI_CD_PERMANENT,
};
static struct s3c_sdhci_platdata crag6410_hsmmc1_pdata = {
.max_width = 4,
.cd_type = S3C_SDHCI_CD_GPIO,
.ext_cd_gpio = S3C64XX_GPF(11),
};
static void crag6410_cfg_sdhci0(struct platform_device *dev, int width)
{
/* Set all the necessary GPG pins to special-function 2 */
......@@ -723,7 +717,6 @@ static void __init crag6410_machine_init(void)
gpio_direction_output(S3C64XX_GPF(10), 1);
s3c_sdhci0_set_platdata(&crag6410_hsmmc0_pdata);
s3c_sdhci1_set_platdata(&crag6410_hsmmc1_pdata);
s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata);
s3c_i2c0_set_platdata(&i2c0_pdata);
......
......@@ -346,23 +346,10 @@ int __init s3c64xx_pm_init(void)
static __init int s3c64xx_pm_initcall(void)
{
u32 val;
pm_cpu_prep = s3c64xx_pm_prepare;
pm_cpu_sleep = s3c64xx_cpu_suspend;
pm_uart_udivslot = 1;
/*
* Unconditionally disable power domains that contain only
* blocks which have no mainline driver support.
*/
val = __raw_readl(S3C64XX_NORMAL_CFG);
val &= ~(S3C64XX_NORMALCFG_DOMAIN_G_ON |
S3C64XX_NORMALCFG_DOMAIN_V_ON |
S3C64XX_NORMALCFG_DOMAIN_I_ON |
S3C64XX_NORMALCFG_DOMAIN_P_ON);
__raw_writel(val, S3C64XX_NORMAL_CFG);
#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
gpio_request(S3C64XX_GPN(13), "DEBUG_LED1");
......
......@@ -32,6 +32,8 @@ pen: ldr r7, [r6]
* should now contain the SVC stack for this core
*/
b secondary_startup
ENDPROC(u8500_secondary_startup)
.align 2
1: .long .
.long pen_release
......@@ -13,8 +13,6 @@
#include <linux/smp.h>
#include <linux/io.h>
#include <asm/unified.h>
#include <mach/motherboard.h>
#define V2M_PA_CS7 0x10000000
......@@ -46,6 +44,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* secondary CPU branches to this address.
*/
writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
writel(BSYM(virt_to_phys(versatile_secondary_startup)),
writel(virt_to_phys(versatile_secondary_startup),
MMIO_P2V(V2M_SYS_FLAGSSET));
}
......@@ -14,6 +14,7 @@
#define __SAMSUNG_DMA_OPS_H_ __FILE__
#include <linux/dmaengine.h>
#include <mach/dma.h>
struct samsung_dma_prep_info {
enum dma_transaction_type cap;
......
......@@ -10,6 +10,9 @@
* published by the Free Software Foundation.
*/
#ifndef __PLAT_DMA_H
#define __PLAT_DMA_H
#include <linux/dma-mapping.h>
enum s3c2410_dma_buffresult {
......@@ -122,5 +125,6 @@ extern int s3c2410_dma_getposition(enum dma_ch channel,
extern int s3c2410_dma_set_opfn(enum dma_ch, s3c2410_dma_opfn_t rtn);
extern int s3c2410_dma_set_buffdone_fn(enum dma_ch, s3c2410_dma_cbfn_t rtn);
#include <plat/dma-ops.h>
#endif
......@@ -11,6 +11,8 @@
#ifndef __S3C64XX_PLAT_SPI_H
#define __S3C64XX_PLAT_SPI_H
struct platform_device;
/**
* struct s3c64xx_spi_csinfo - ChipSelect description
* @fb_delay: Slave specific feedback delay.
......
......@@ -38,3 +38,4 @@ pen: ldr r7, [r6]
.align
1: .long .
.long pen_release
ENDPROC(versatile_secondary_startup)
Markdown is supported
0% .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑!
想要评论请 注册