omap: mux: Add 36xx CBP package support

Add 36xx CBP package support

Cc: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

arch/arm/mach-omap2/Kconfig

@@ -33,6 +33,9 @@ config OMAP_PACKAGE_CBB
 config OMAP_PACKAGE_CUS
        bool
 
+config OMAP_PACKAGE_CBP
+       bool
+
 comment "OMAP Board Type"
 	depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4
 
@@ -121,6 +124,7 @@ config MACH_OMAP_ZOOM2
 config MACH_OMAP_ZOOM3
 	bool "OMAP3630 Zoom3 board"
 	depends on ARCH_OMAP3 && ARCH_OMAP34XX
+	select OMAP_PACKAGE_CBP
 
 config MACH_CM_T35
 	bool "CompuLab CM-T35 module"
@@ -135,6 +139,7 @@ config MACH_IGEP0020
 config MACH_OMAP_3630SDP
 	bool "OMAP3630 SDP board"
 	depends on ARCH_OMAP3 && ARCH_OMAP34XX
+	select OMAP_PACKAGE_CBP
 
 config MACH_OMAP_4430SDP
 	bool "OMAP 4430 SDP board"

arch/arm/mach-omap2/board-3630sdp.c

@@ -85,8 +85,17 @@ static void __init omap_sdp_init_irq(void)
 	omap_gpio_init();
 }
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+	{ .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux	NULL
+#endif
+
 static void __init omap_sdp_init(void)
 {
+	omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
 	zoom_peripherals_init();
 	board_smc91x_init();
 	enable_board_wakeup_source();

arch/arm/mach-omap2/board-zoom3.c

@@ -21,6 +21,7 @@
 #include <plat/common.h>
 #include <plat/board.h>
 
+#include "mux.h"
 #include "sdram-hynix-h8mbx00u0mer-0em.h"
 
 static void __init omap_zoom_map_io(void)
@@ -42,8 +43,17 @@ static void __init omap_zoom_init_irq(void)
 	omap_gpio_init();
 }
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+	{ .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux	NULL
+#endif
+
 static void __init omap_zoom_init(void)
 {
+	omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
 	zoom_peripherals_init();
 	zoom_debugboard_init();
 }

arch/arm/mach-omap2/mux.h

@@ -56,6 +56,7 @@
 
 /* Flags for omap_mux_init */
 #define OMAP_PACKAGE_MASK		0xffff
+#define OMAP_PACKAGE_CBP		4		/* 515-pin 0.40 0.50 */
 #define OMAP_PACKAGE_CUS		3		/* 423-pin 0.65 */
 #define OMAP_PACKAGE_CBB		2		/* 515-pin 0.40 0.50 */
 #define OMAP_PACKAGE_CBC		1		/* 515-pin 0.50 0.65 */

arch/arm/mach-omap2/mux34xx.h

@@ -170,10 +170,13 @@
 #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET		0x11a
 #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET		0x11c
 #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET		0x11e
+
+/* SDMMC1_DAT4 - DAT7 are SIM_IO SIM_CLK SIM_PWRCTRL and SIM_RST on 36xx */
 #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT4_OFFSET		0x120
 #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT5_OFFSET		0x122
 #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT6_OFFSET		0x124
 #define OMAP3_CONTROL_PADCONF_SDMMC1_DAT7_OFFSET		0x126
+
 #define OMAP3_CONTROL_PADCONF_SDMMC2_CLK_OFFSET			0x128
 #define OMAP3_CONTROL_PADCONF_SDMMC2_CMD_OFFSET			0x12a
 #define OMAP3_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET		0x12c
@@ -281,6 +284,7 @@
 #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD34_OFFSET		0x1f8
 #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD35_OFFSET		0x1fa
 #define OMAP3_CONTROL_PADCONF_SAD2D_MCAD36_OFFSET		0x1fc
+
 /* Note that 34xx TRM has SAD2D instead of CHASSIS for these */
 #define OMAP3_CONTROL_PADCONF_CHASSIS_CLK26MI_OFFSET		0x1fe
 #define OMAP3_CONTROL_PADCONF_CHASSIS_NRESPWRON_OFFSET		0x200
@@ -302,6 +306,7 @@
 #define OMAP3_CONTROL_PADCONF_CHASSIS_MSTDBY_OFFSET		0x220
 #define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEREQ_OFFSET		0x222
 #define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEACK_OFFSET		0x224
+
 #define OMAP3_CONTROL_PADCONF_SAD2D_MWRITE_OFFSET		0x226
 #define OMAP3_CONTROL_PADCONF_SAD2D_SWRITE_OFFSET		0x228
 #define OMAP3_CONTROL_PADCONF_SAD2D_MREAD_OFFSET		0x22a
@@ -310,6 +315,43 @@
 #define OMAP3_CONTROL_PADCONF_SAD2D_SBUSFLAG_OFFSET		0x230
 #define OMAP3_CONTROL_PADCONF_SDRC_CKE0_OFFSET			0x232
 #define OMAP3_CONTROL_PADCONF_SDRC_CKE1_OFFSET			0x234
+
+/* 36xx only */
+#define OMAP3_CONTROL_PADCONF_GPMC_A11_OFFSET			0x236
+#define OMAP3_CONTROL_PADCONF_SDRC_BA0_OFFSET			0x570
+#define OMAP3_CONTROL_PADCONF_SDRC_BA1_OFFSET			0x572
+#define OMAP3_CONTROL_PADCONF_SDRC_A0_OFFSET			0x574
+#define OMAP3_CONTROL_PADCONF_SDRC_A1_OFFSET			0x576
+#define OMAP3_CONTROL_PADCONF_SDRC_A2_OFFSET			0x578
+#define OMAP3_CONTROL_PADCONF_SDRC_A3_OFFSET			0x57a
+#define OMAP3_CONTROL_PADCONF_SDRC_A4_OFFSET			0x57c
+#define OMAP3_CONTROL_PADCONF_SDRC_A5_OFFSET			0x57e
+#define OMAP3_CONTROL_PADCONF_SDRC_A6_OFFSET			0x580
+#define OMAP3_CONTROL_PADCONF_SDRC_A7_OFFSET			0x582
+#define OMAP3_CONTROL_PADCONF_SDRC_A8_OFFSET			0x584
+#define OMAP3_CONTROL_PADCONF_SDRC_A9_OFFSET			0x586
+#define OMAP3_CONTROL_PADCONF_SDRC_A10_OFFSET			0x588
+#define OMAP3_CONTROL_PADCONF_SDRC_A11_OFFSET			0x58a
+#define OMAP3_CONTROL_PADCONF_SDRC_A12_OFFSET			0x58c
+#define OMAP3_CONTROL_PADCONF_SDRC_A13_OFFSET			0x58e
+#define OMAP3_CONTROL_PADCONF_SDRC_A14_OFFSET			0x590
+#define OMAP3_CONTROL_PADCONF_SDRC_NCS0_OFFSET			0x592
+#define OMAP3_CONTROL_PADCONF_SDRC_NCS1_OFFSET			0x594
+#define OMAP3_CONTROL_PADCONF_SDRC_NCLK_OFFSET			0x596
+#define OMAP3_CONTROL_PADCONF_SDRC_NRAS_OFFSET			0x598
+#define OMAP3_CONTROL_PADCONF_SDRC_NCAS_OFFSET			0x59a
+#define OMAP3_CONTROL_PADCONF_SDRC_NWE_OFFSET			0x59c
+#define OMAP3_CONTROL_PADCONF_SDRC_DM0_OFFSET			0x59e
+#define OMAP3_CONTROL_PADCONF_SDRC_DM1_OFFSET			0x5a0
+#define OMAP3_CONTROL_PADCONF_SDRC_DM2_OFFSET			0x5a2
+#define OMAP3_CONTROL_PADCONF_SDRC_DM3_OFFSET			0x5a4
+
+/* 36xx only, these are SDMMC1_DAT4 - DAT7 on 34xx */
+#define OMAP3_CONTROL_PADCONF_SIM_IO_OFFSET			0x120
+#define OMAP3_CONTROL_PADCONF_SIM_CLK_OFFSET			0x122
+#define OMAP3_CONTROL_PADCONF_SIM_PWRCTRL_OFFSET		0x124
+#define OMAP3_CONTROL_PADCONF_SIM_RST_OFFSET			0x126
+
 #define OMAP3_CONTROL_PADCONF_ETK_CLK_OFFSET			0x5a8
 #define OMAP3_CONTROL_PADCONF_ETK_CTL_OFFSET			0x5aa
 #define OMAP3_CONTROL_PADCONF_ETK_D0_OFFSET			0x5ac