提交 5bf3df3f 编写于 作者: E Eric Miao

[ARM] pxa: separate definitions from pxa-regs.h and remove it finally

The remaining registers are separated into:

   - <mach/regs-ost.h>
   - <mach/regs-rtc.h>
   - <mach/regs-intc.h>

and then we can remove pxa-regs.h completely. Instead of #include this
file, let's:

1. include the specific <mach/regs-*.h> with care (if that's absolutely
   necessary)

2. define the registers in the driver, make cleanly defined API to expose
   the register access to external with sufficient reason
Signed-off-by: NEric Miao <eric.miao@marvell.com>
上级 b74d1969
......@@ -29,8 +29,8 @@
#include <mach/hardware.h>
#include <asm/irq.h>
#include <mach/pm.h>
#include <mach/pxa-regs.h>
#include <mach/pxa2xx-regs.h>
#include <mach/regs-rtc.h>
#include <mach/sharpsl.h>
#include <asm/hardware/sharpsl_pm.h>
......
......@@ -22,7 +22,6 @@
#include <linux/string.h>
#include <mach/corgi.h>
#include <mach/hardware.h>
#include <mach/pxa-regs.h>
#include <mach/sharpsl.h>
#include <mach/spitz.h>
#include <asm/hardware/scoop.h>
......
......@@ -20,7 +20,6 @@
#include <asm/mach-types.h>
#include <mach/ssp.h>
#include <mach/pxa-regs.h>
#include <mach/pxa2xx-gpio.h>
#include <mach/regs-ssp.h>
#include "sharpsl.h"
......
......@@ -15,8 +15,8 @@
#ifndef __ARCH_PXA_MTD_XIP_H__
#define __ARCH_PXA_MTD_XIP_H__
#include <mach/hardware.h>
#include <mach/pxa-regs.h>
#include <mach/regs-ost.h>
#include <mach/regs-intc.h>
#define xip_irqpending() (ICIP & ICMR)
......
......@@ -14,7 +14,7 @@
#ifndef __PXA2XX_REGS_H
#define __PXA2XX_REGS_H
#include <mach/pxa-regs.h>
#include <mach/hardware.h>
/*
* PXA Chip selects
......
#ifndef __ASM_MACH_REGS_INTC_H
#define __ASM_MACH_REGS_INTC_H
#include <mach/hardware.h>
/*
* Interrupt Controller
*/
#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
#endif /* __ASM_MACH_REGS_INTC_H */
/*
* arch/arm/mach-pxa/include/mach/pxa-regs.h
*
* Author: Nicolas Pitre
* Created: Jun 15, 2001
* Copyright: MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PXA_REGS_H
#define __PXA_REGS_H
#ifndef __ASM_MACH_REGS_OST_H
#define __ASM_MACH_REGS_OST_H
#include <mach/hardware.h>
/*
* Real Time Clock
*/
#define RCNR __REG(0x40900000) /* RTC Count Register */
#define RTAR __REG(0x40900004) /* RTC Alarm Register */
#define RTSR __REG(0x40900008) /* RTC Status Register */
#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
#define RTSR_AL (1 << 0) /* RTC alarm detected */
/*
* OS Timer & Match Registers
*/
......@@ -61,22 +31,4 @@
#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
/*
* Interrupt Controller
*/
#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
#endif
#endif /* __ASM_MACH_REGS_OST_H */
#ifndef __ASM_MACH_REGS_RTC_H
#define __ASM_MACH_REGS_RTC_H
#include <mach/hardware.h>
/*
* Real Time Clock
*/
#define RCNR __REG(0x40900000) /* RTC Count Register */
#define RTAR __REG(0x40900004) /* RTC Alarm Register */
#define RTSR __REG(0x40900008) /* RTC Status Register */
#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
#define RTSR_AL (1 << 0) /* RTC alarm detected */
#endif /* __ASM_MACH_REGS_RTC_H */
......@@ -13,7 +13,6 @@
#include <asm/proc-fns.h>
#include "hardware.h"
#include "pxa2xx-regs.h"
#include "pxa-regs.h"
static inline void arch_idle(void)
{
......
......@@ -20,8 +20,8 @@
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <mach/pxa-regs.h>
#include <mach/gpio.h>
#include <mach/regs-intc.h>
#include "generic.h"
......
......@@ -41,6 +41,7 @@
#include <asm/mach/arch.h>
#include <mach/pxa27x.h>
#include <mach/regs-rtc.h>
#include <mach/pxa27x_keypad.h>
#include <mach/pxafb.h>
#include <mach/mmc.h>
......
......@@ -10,7 +10,7 @@
#include <linux/io.h>
#include <asm/proc-fns.h>
#include <mach/pxa-regs.h>
#include <mach/regs-ost.h>
#include <mach/reset.h>
unsigned int reset_status;
......
......@@ -25,7 +25,6 @@
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <mach/pm.h>
#include <mach/pxa-regs.h>
#include <mach/pxa2xx-gpio.h>
#include <mach/sharpsl.h>
#include "sharpsl.h"
......
......@@ -15,7 +15,6 @@
#include <asm/assembler.h>
#include <mach/hardware.h>
#include <mach/pxa-regs.h>
#include <mach/pxa2xx-regs.h>
#define MDREFR_KDIV 0x200a4000 // all banks
......
......@@ -24,7 +24,6 @@
#include <mach/sharpsl.h>
#include <mach/spitz.h>
#include <mach/pxa-regs.h>
#include <mach/pxa2xx-regs.h>
#include <mach/pxa2xx-gpio.h>
#include "sharpsl.h"
......
......@@ -13,7 +13,6 @@
#include <asm/assembler.h>
#include <mach/hardware.h>
#include <mach/pxa-regs.h>
#include <mach/pxa2xx-regs.h>
.text
......
......@@ -22,8 +22,7 @@
#include <asm/div64.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <mach/hardware.h>
#include <mach/pxa-regs.h>
#include <mach/regs-ost.h>
/*
* This is PXA's sched_clock implementation. This has a resolution
......
......@@ -21,7 +21,6 @@
#include <mach/sharpsl.h>
#include <mach/hardware.h>
#include <mach/pxa-regs.h>
#include <mach/pxa2xx-gpio.h>
......
......@@ -24,9 +24,8 @@
#include <mach/dma.h>
#include <mach/irda.h>
#include <mach/hardware.h>
#include <mach/pxa-regs.h>
#include <mach/regs-uart.h>
#include <mach/regs-ost.h>
#define FICP __REG(0x40800000) /* Start of FICP area */
#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
......
......@@ -35,7 +35,8 @@
#include <asm/irq.h>
#ifdef CONFIG_ARCH_PXA
#include <mach/pxa-regs.h>
#include <mach/regs-rtc.h>
#include <mach/regs-ost.h>
#endif
#define RTC_DEF_DIVIDER 32768 - 1
......
......@@ -30,7 +30,7 @@
#include <linux/timex.h>
#ifdef CONFIG_ARCH_PXA
#include <mach/pxa-regs.h>
#include <mach/regs-ost.h>
#endif
#include <mach/reset.h>
......
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