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提交 24ed45aa 编写于 作者: T Tony Lindgren
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Merge branch 'for_2_6_33' of git://git.pwsan.com/linux-2.6 into omap-for-linus

上级 aa2cf420 911bd739
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Showing with 14301 addition and 5742 deletion
arch/arm/mach-omap1/Makefile
浏览文件 @ 24ed45aa
......@@ -3,7 +3,8 @@
#
# Common support
obj-y := io.o id.o sram.o clock.o irq.o mux.o serial.o devices.o
obj-y := io.o id.o sram.o irq.o mux.o serial.o devices.o
obj-y += clock.o clock_data.o opp_data.o
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
......
arch/arm/mach-omap1/clock.c
浏览文件 @ 24ed45aa
此差异已折叠。
arch/arm/mach-omap1/clock.h
浏览文件 @ 24ed45aa
/*
* linux/arch/arm/mach-omap1/clock.h
*
* Copyright (C) 2004 - 2005 Nokia corporation
* Copyright (C) 2004 - 2005, 2009 Nokia corporation
* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
*
......@@ -13,30 +13,36 @@
#ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
#define __ARCH_ARM_MACH_OMAP1_CLOCK_H
static unsigned long omap1_ckctl_recalc(struct clk *clk);
static unsigned long omap1_watchdog_recalc(struct clk *clk);
static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
static unsigned long omap1_sossi_recalc(struct clk *clk);
static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
static unsigned long omap1_uart_recalc(struct clk *clk);
static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
static void omap1_init_ext_clk(struct clk * clk);
static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
struct mpu_rate {
unsigned long rate;
unsigned long xtal;
unsigned long pll_rate;
__u16 ckctl_val;
__u16 dpllctl_val;
};
#include <linux/clk.h>
#include <plat/clock.h>
extern int __init omap1_clk_init(void);
extern int omap1_clk_enable(struct clk *clk);
extern void omap1_clk_disable(struct clk *clk);
extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate);
extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate);
extern unsigned long omap1_ckctl_recalc(struct clk *clk);
extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
extern unsigned long omap1_sossi_recalc(struct clk *clk);
extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate);
extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate);
extern unsigned long omap1_uart_recalc(struct clk *clk);
extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate);
extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate);
extern void omap1_init_ext_clk(struct clk *clk);
extern int omap1_select_table_rate(struct clk *clk, unsigned long rate);
extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate);
extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
extern unsigned long omap1_watchdog_recalc(struct clk *clk);
#ifdef CONFIG_OMAP_RESET_CLOCKS
extern void __init omap1_clk_disable_unused(struct clk *clk);
#else
#define omap1_clk_disable_unused NULL
#endif
struct uart_clk {
struct clk clk;
......@@ -96,596 +102,12 @@ struct arm_idlect1_clk {
#define SOFT_REQ_REG 0xfffe0834
#define SOFT_REQ_REG2 0xfffe0880
/*-------------------------------------------------------------------------
* Omap1 MPU rate table
*-------------------------------------------------------------------------*/
static struct mpu_rate rate_table[] = {
/* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
* NOTE: Comment order here is different from bits in CKCTL value:
* armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
*/
#if defined(CONFIG_OMAP_ARM_216MHZ)
{ 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
#endif
#if defined(CONFIG_OMAP_ARM_195MHZ)
{ 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
#endif
#if defined(CONFIG_OMAP_ARM_192MHZ)
{ 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
{ 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
{ 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
{ 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
{ 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
#endif
#if defined(CONFIG_OMAP_ARM_182MHZ)
{ 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
#endif
#if defined(CONFIG_OMAP_ARM_168MHZ)
{ 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
#endif
#if defined(CONFIG_OMAP_ARM_150MHZ)
{ 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
#endif
#if defined(CONFIG_OMAP_ARM_120MHZ)
{ 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
#endif
#if defined(CONFIG_OMAP_ARM_96MHZ)
{ 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
#endif
#if defined(CONFIG_OMAP_ARM_60MHZ)
{ 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
#endif
#if defined(CONFIG_OMAP_ARM_30MHZ)
{ 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
#endif
{ 0, 0, 0, 0, 0 },
};
/*-------------------------------------------------------------------------
* Omap1 clocks
*-------------------------------------------------------------------------*/
static struct clk ck_ref = {
.name = "ck_ref",
.ops = &clkops_null,
.rate = 12000000,
};
static struct clk ck_dpll1 = {
.name = "ck_dpll1",
.ops = &clkops_null,
.parent = &ck_ref,
};
static struct arm_idlect1_clk ck_dpll1out = {
.clk = {
.name = "ck_dpll1out",
.ops = &clkops_generic,
.parent = &ck_dpll1,
.flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_CKOUT_ARM,
.recalc = &followparent_recalc,
},
.idlect_shift = 12,
};
static struct clk sossi_ck = {
.name = "ck_sossi",
.ops = &clkops_generic,
.parent = &ck_dpll1out.clk,
.flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
.enable_bit = 16,
.recalc = &omap1_sossi_recalc,
.set_rate = &omap1_set_sossi_rate,
};
static struct clk arm_ck = {
.name = "arm_ck",
.ops = &clkops_null,
.parent = &ck_dpll1,
.rate_offset = CKCTL_ARMDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
.round_rate = omap1_clk_round_rate_ckctl_arm,
.set_rate = omap1_clk_set_rate_ckctl_arm,
};
static struct arm_idlect1_clk armper_ck = {
.clk = {
.name = "armper_ck",
.ops = &clkops_generic,
.parent = &ck_dpll1,
.flags = CLOCK_IDLE_CONTROL,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_PERCK,
.rate_offset = CKCTL_PERDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
.round_rate = omap1_clk_round_rate_ckctl_arm,
.set_rate = omap1_clk_set_rate_ckctl_arm,
},
.idlect_shift = 2,
};
static struct clk arm_gpio_ck = {
.name = "arm_gpio_ck",
.ops = &clkops_generic,
.parent = &ck_dpll1,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_GPIOCK,
.recalc = &followparent_recalc,
};
static struct arm_idlect1_clk armxor_ck = {
.clk = {
.name = "armxor_ck",
.ops = &clkops_generic,
.parent = &ck_ref,
.flags = CLOCK_IDLE_CONTROL,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_XORPCK,
.recalc = &followparent_recalc,
},
.idlect_shift = 1,
};
static struct arm_idlect1_clk armtim_ck = {
.clk = {
.name = "armtim_ck",
.ops = &clkops_generic,
.parent = &ck_ref,
.flags = CLOCK_IDLE_CONTROL,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_TIMCK,
.recalc = &followparent_recalc,
},
.idlect_shift = 9,
};
static struct arm_idlect1_clk armwdt_ck = {
.clk = {
.name = "armwdt_ck",
.ops = &clkops_generic,
.parent = &ck_ref,
.flags = CLOCK_IDLE_CONTROL,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_WDTCK,
.recalc = &omap1_watchdog_recalc,
},
.idlect_shift = 0,
};
static struct clk arminth_ck16xx = {
.name = "arminth_ck",
.ops = &clkops_null,
.parent = &arm_ck,
.recalc = &followparent_recalc,
/* Note: On 16xx the frequency can be divided by 2 by programming
* ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
*
* 1510 version is in TC clocks.
*/
};
static struct clk dsp_ck = {
.name = "dsp_ck",
.ops = &clkops_generic,
.parent = &ck_dpll1,
.enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
.enable_bit = EN_DSPCK,
.rate_offset = CKCTL_DSPDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
.round_rate = omap1_clk_round_rate_ckctl_arm,
.set_rate = omap1_clk_set_rate_ckctl_arm,
};
static struct clk dspmmu_ck = {
.name = "dspmmu_ck",
.ops = &clkops_null,
.parent = &ck_dpll1,
.rate_offset = CKCTL_DSPMMUDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
.round_rate = omap1_clk_round_rate_ckctl_arm,
.set_rate = omap1_clk_set_rate_ckctl_arm,
};
static struct clk dspper_ck = {
.name = "dspper_ck",
.ops = &clkops_dspck,
.parent = &ck_dpll1,
.enable_reg = DSP_IDLECT2,
.enable_bit = EN_PERCK,
.rate_offset = CKCTL_PERDIV_OFFSET,
.recalc = &omap1_ckctl_recalc_dsp_domain,
.round_rate = omap1_clk_round_rate_ckctl_arm,
.set_rate = &omap1_clk_set_rate_dsp_domain,
};
static struct clk dspxor_ck = {
.name = "dspxor_ck",
.ops = &clkops_dspck,
.parent = &ck_ref,
.enable_reg = DSP_IDLECT2,
.enable_bit = EN_XORPCK,
.recalc = &followparent_recalc,
};
static struct clk dsptim_ck = {
.name = "dsptim_ck",
.ops = &clkops_dspck,
.parent = &ck_ref,
.enable_reg = DSP_IDLECT2,
.enable_bit = EN_DSPTIMCK,
.recalc = &followparent_recalc,
};
/* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
static struct arm_idlect1_clk tc_ck = {
.clk = {
.name = "tc_ck",
.ops = &clkops_null,
.parent = &ck_dpll1,
.flags = CLOCK_IDLE_CONTROL,
.rate_offset = CKCTL_TCDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
.round_rate = omap1_clk_round_rate_ckctl_arm,
.set_rate = omap1_clk_set_rate_ckctl_arm,
},
.idlect_shift = 6,
};
static struct clk arminth_ck1510 = {
.name = "arminth_ck",
.ops = &clkops_null,
.parent = &tc_ck.clk,
.recalc = &followparent_recalc,
/* Note: On 1510 the frequency follows TC_CK
*
* 16xx version is in MPU clocks.
*/
};
static struct clk tipb_ck = {
/* No-idle controlled by "tc_ck" */
.name = "tipb_ck",
.ops = &clkops_null,
.parent = &tc_ck.clk,
.recalc = &followparent_recalc,
};
static struct clk l3_ocpi_ck = {
/* No-idle controlled by "tc_ck" */
.name = "l3_ocpi_ck",
.ops = &clkops_generic,
.parent = &tc_ck.clk,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
.enable_bit = EN_OCPI_CK,
.recalc = &followparent_recalc,
};
static struct clk tc1_ck = {
.name = "tc1_ck",
.ops = &clkops_generic,
.parent = &tc_ck.clk,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
.enable_bit = EN_TC1_CK,
.recalc = &followparent_recalc,
};
extern __u32 arm_idlect1_mask;
extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
static struct clk tc2_ck = {
.name = "tc2_ck",
.ops = &clkops_generic,
.parent = &tc_ck.clk,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
.enable_bit = EN_TC2_CK,
.recalc = &followparent_recalc,
};
static struct clk dma_ck = {
/* No-idle controlled by "tc_ck" */
.name = "dma_ck",
.ops = &clkops_null,
.parent = &tc_ck.clk,
.recalc = &followparent_recalc,
};
static struct clk dma_lcdfree_ck = {
.name = "dma_lcdfree_ck",
.ops = &clkops_null,
.parent = &tc_ck.clk,
.recalc = &followparent_recalc,
};
static struct arm_idlect1_clk api_ck = {
.clk = {
.name = "api_ck",
.ops = &clkops_generic,
.parent = &tc_ck.clk,
.flags = CLOCK_IDLE_CONTROL,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_APICK,
.recalc = &followparent_recalc,
},
.idlect_shift = 8,
};
static struct arm_idlect1_clk lb_ck = {
.clk = {
.name = "lb_ck",
.ops = &clkops_generic,
.parent = &tc_ck.clk,
.flags = CLOCK_IDLE_CONTROL,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_LBCK,
.recalc = &followparent_recalc,
},
.idlect_shift = 4,
};
static struct clk rhea1_ck = {
.name = "rhea1_ck",
.ops = &clkops_null,
.parent = &tc_ck.clk,
.recalc = &followparent_recalc,
};
static struct clk rhea2_ck = {
.name = "rhea2_ck",
.ops = &clkops_null,
.parent = &tc_ck.clk,
.recalc = &followparent_recalc,
};
static struct clk lcd_ck_16xx = {
.name = "lcd_ck",
.ops = &clkops_generic,
.parent = &ck_dpll1,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_LCDCK,
.rate_offset = CKCTL_LCDDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
.round_rate = omap1_clk_round_rate_ckctl_arm,
.set_rate = omap1_clk_set_rate_ckctl_arm,
};
static struct arm_idlect1_clk lcd_ck_1510 = {
.clk = {
.name = "lcd_ck",
.ops = &clkops_generic,
.parent = &ck_dpll1,
.flags = CLOCK_IDLE_CONTROL,
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
.enable_bit = EN_LCDCK,
.rate_offset = CKCTL_LCDDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
.round_rate = omap1_clk_round_rate_ckctl_arm,
.set_rate = omap1_clk_set_rate_ckctl_arm,
},
.idlect_shift = 3,
};
static struct clk uart1_1510 = {
.name = "uart1_ck",
.ops = &clkops_null,
/* Direct from ULPD, no real parent */
.parent = &armper_ck.clk,
.rate = 12000000,
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = 29, /* Chooses between 12MHz and 48MHz */
.set_rate = &omap1_set_uart_rate,
.recalc = &omap1_uart_recalc,
};
static struct uart_clk uart1_16xx = {
.clk = {
.name = "uart1_ck",
.ops = &clkops_uart,
/* Direct from ULPD, no real parent */
.parent = &armper_ck.clk,
.rate = 48000000,
.flags = RATE_FIXED | ENABLE_REG_32BIT |
CLOCK_NO_IDLE_PARENT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = 29,
},
.sysc_addr = 0xfffb0054,
};
static struct clk uart2_ck = {
.name = "uart2_ck",
.ops = &clkops_null,
/* Direct from ULPD, no real parent */
.parent = &armper_ck.clk,
.rate = 12000000,
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = 30, /* Chooses between 12MHz and 48MHz */
.set_rate = &omap1_set_uart_rate,
.recalc = &omap1_uart_recalc,
};
static struct clk uart3_1510 = {
.name = "uart3_ck",
.ops = &clkops_null,
/* Direct from ULPD, no real parent */
.parent = &armper_ck.clk,
.rate = 12000000,
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = 31, /* Chooses between 12MHz and 48MHz */
.set_rate = &omap1_set_uart_rate,
.recalc = &omap1_uart_recalc,
};
static struct uart_clk uart3_16xx = {
.clk = {
.name = "uart3_ck",
.ops = &clkops_uart,
/* Direct from ULPD, no real parent */
.parent = &armper_ck.clk,
.rate = 48000000,
.flags = RATE_FIXED | ENABLE_REG_32BIT |
CLOCK_NO_IDLE_PARENT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = 31,
},
.sysc_addr = 0xfffb9854,
};
static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
.name = "usb_clko",
.ops = &clkops_generic,
/* Direct from ULPD, no parent */
.rate = 6000000,
.flags = RATE_FIXED | ENABLE_REG_32BIT,
.enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
.enable_bit = USB_MCLK_EN_BIT,
};
static struct clk usb_hhc_ck1510 = {
.name = "usb_hhc_ck",
.ops = &clkops_generic,
/* Direct from ULPD, no parent */
.rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
.flags = RATE_FIXED | ENABLE_REG_32BIT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = USB_HOST_HHC_UHOST_EN,
};
static struct clk usb_hhc_ck16xx = {
.name = "usb_hhc_ck",
.ops = &clkops_generic,
/* Direct from ULPD, no parent */
.rate = 48000000,
/* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
.flags = RATE_FIXED | ENABLE_REG_32BIT,
.enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
.enable_bit = 8 /* UHOST_EN */,
};
static struct clk usb_dc_ck = {
.name = "usb_dc_ck",
.ops = &clkops_generic,
/* Direct from ULPD, no parent */
.rate = 48000000,
.flags = RATE_FIXED,
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
.enable_bit = 4,
};
static struct clk usb_dc_ck7xx = {
.name = "usb_dc_ck",
.ops = &clkops_generic,
/* Direct from ULPD, no parent */
.rate = 48000000,
.flags = RATE_FIXED,
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
.enable_bit = 8,
};
static struct clk mclk_1510 = {
.name = "mclk",
.ops = &clkops_generic,
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
.rate = 12000000,
.flags = RATE_FIXED,
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
.enable_bit = 6,
};
static struct clk mclk_16xx = {
.name = "mclk",
.ops = &clkops_generic,
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
.enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
.enable_bit = COM_ULPD_PLL_CLK_REQ,
.set_rate = &omap1_set_ext_clk_rate,
.round_rate = &omap1_round_ext_clk_rate,
.init = &omap1_init_ext_clk,
};
static struct clk bclk_1510 = {
.name = "bclk",
.ops = &clkops_generic,
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
.rate = 12000000,
.flags = RATE_FIXED,
};
static struct clk bclk_16xx = {
.name = "bclk",
.ops = &clkops_generic,
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
.enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
.enable_bit = SWD_ULPD_PLL_CLK_REQ,
.set_rate = &omap1_set_ext_clk_rate,
.round_rate = &omap1_round_ext_clk_rate,
.init = &omap1_init_ext_clk,
};
static struct clk mmc1_ck = {
.name = "mmc_ck",
.ops = &clkops_generic,
/* Functional clock is direct from ULPD, interface clock is ARMPER */
.parent = &armper_ck.clk,
.rate = 48000000,
.flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = 23,
};
static struct clk mmc2_ck = {
.name = "mmc_ck",
.id = 1,
.ops = &clkops_generic,
/* Functional clock is direct from ULPD, interface clock is ARMPER */
.parent = &armper_ck.clk,
.rate = 48000000,
.flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
.enable_bit = 20,
};
static struct clk mmc3_ck = {
.name = "mmc_ck",
.id = 2,
.ops = &clkops_generic,
/* Functional clock is direct from ULPD, interface clock is ARMPER */
.parent = &armper_ck.clk,
.rate = 48000000,
.flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
.enable_bit = 12,
};
static struct clk virtual_ck_mpu = {
.name = "mpu",
.ops = &clkops_null,
.parent = &arm_ck, /* Is smarter alias for */
.recalc = &followparent_recalc,
.set_rate = &omap1_select_table_rate,
.round_rate = &omap1_round_to_table_rate,
};
/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
remains active during MPU idle whenever this is enabled */
static struct clk i2c_fck = {
.name = "i2c_fck",
.id = 1,
.ops = &clkops_null,
.flags = CLOCK_NO_IDLE_PARENT,
.parent = &armxor_ck.clk,
.recalc = &followparent_recalc,
};
static struct clk i2c_ick = {
.name = "i2c_ick",
.id = 1,
.ops = &clkops_null,
.flags = CLOCK_NO_IDLE_PARENT,
.parent = &armper_ck.clk,
.recalc = &followparent_recalc,
};
extern const struct clkops clkops_dspck;
extern const struct clkops clkops_dummy;
extern const struct clkops clkops_uart;
extern const struct clkops clkops_generic;
#endif
arch/arm/mach-omap1/clock_data.c 0 → 100644
浏览文件 @ 24ed45aa
此差异已折叠。
arch/arm/mach-omap1/io.c
浏览文件 @ 24ed45aa
......@@ -18,7 +18,8 @@
#include <plat/mux.h>
#include <plat/tc.h>
extern int omap1_clk_init(void);
#include "clock.h"
extern void omap_check_revision(void);
extern void omap_sram_init(void);
extern void omapfb_reserve_sdram(void);
......
arch/arm/mach-omap1/opp.h 0 → 100644
浏览文件 @ 24ed45aa
/*
* linux/arch/arm/mach-omap1/opp.h
*
* Copyright (C) 2004 - 2005 Nokia corporation
* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP1_OPP_H
#define __ARCH_ARM_MACH_OMAP1_OPP_H
#include <linux/types.h>
struct mpu_rate {
unsigned long rate;
unsigned long xtal;
unsigned long pll_rate;
__u16 ckctl_val;
__u16 dpllctl_val;
};
extern struct mpu_rate omap1_rate_table[];
#endif
arch/arm/mach-omap1/opp_data.c 0 → 100644
浏览文件 @ 24ed45aa
/*
* linux/arch/arm/mach-omap1/opp_data.c
*
* Copyright (C) 2004 - 2005 Nokia corporation
* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "opp.h"
/*-------------------------------------------------------------------------
* Omap1 MPU rate table
*-------------------------------------------------------------------------*/
struct mpu_rate omap1_rate_table[] = {
/* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
* NOTE: Comment order here is different from bits in CKCTL value:
* armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
*/
#if defined(CONFIG_OMAP_ARM_216MHZ)
{ 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
#endif
#if defined(CONFIG_OMAP_ARM_195MHZ)
{ 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
#endif
#if defined(CONFIG_OMAP_ARM_192MHZ)
{ 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
{ 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
{ 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
{ 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
{ 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
#endif
#if defined(CONFIG_OMAP_ARM_182MHZ)
{ 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
#endif
#if defined(CONFIG_OMAP_ARM_168MHZ)
{ 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
#endif
#if defined(CONFIG_OMAP_ARM_150MHZ)
{ 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
#endif
#if defined(CONFIG_OMAP_ARM_120MHZ)
{ 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
#endif
#if defined(CONFIG_OMAP_ARM_96MHZ)
{ 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
#endif
#if defined(CONFIG_OMAP_ARM_60MHZ)
{ 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
#endif
#if defined(CONFIG_OMAP_ARM_30MHZ)
{ 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
#endif
{ 0, 0, 0, 0, 0 },
};
arch/arm/mach-omap2/Kconfig
浏览文件 @ 24ed45aa
......@@ -128,3 +128,15 @@ config OMAP3_EMU
help
Say Y here to enable debugging hardware of omap3
config OMAP3_SDRC_AC_TIMING
bool "Enable SDRC AC timing register changes"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
default n
help
If you know that none of your system initiators will attempt to
access SDRAM during CORE DVFS, select Y here. This should boost
SDRAM performance at lower CORE OPPs. There are relatively few
users who will wish to say yes at this point - almost everyone will
wish to say no. Selecting yes without understanding what is
going on could result in system crashes;
arch/arm/mach-omap2/Makefile
浏览文件 @ 24ed45aa
......@@ -6,11 +6,14 @@
obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o
omap-2-3-common = irq.o sdrc.o omap_hwmod.o
omap-3-4-common = dpll.o
prcm-common = prcm.o powerdomain.o
clock-common = clock.o clockdomain.o
clock-common = clock.o clock_common_data.o clockdomain.o
obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common)
obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common)
obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \
$(omap-3-4-common)
obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) prcm.o clock.o
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
......@@ -41,8 +44,11 @@ obj-$(CONFIG_ARCH_OMAP3) += cm.o
obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o
obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o
obj-$(CONFIG_ARCH_OMAP2) += clock2xxx.o clock2xxx_data.o
obj-$(CONFIG_ARCH_OMAP2420) += opp2420_data.o
obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clock34xx_data.o
obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o
obj-$(CONFIG_ARCH_OMAP4) += clock44xx.o clock44xx_data.o
# EMU peripherals
obj-$(CONFIG_OMAP3_EMU) += emu.o
......
arch/arm/mach-omap2/clock.c
浏览文件 @ 24ed45aa
......@@ -70,9 +70,41 @@
u8 cpu_mask;
/*-------------------------------------------------------------------------
* OMAP2/3 specific clock functions
* OMAP2/3/4 specific clock functions
*-------------------------------------------------------------------------*/
void omap2_init_dpll_parent(struct clk *clk)
{
u32 v;
struct dpll_data *dd;
dd = clk->dpll_data;
if (!dd)
return;
/* Return bypass rate if DPLL is bypassed */
v = __raw_readl(dd->control_reg);
v &= dd->enable_mask;
v >>= __ffs(dd->enable_mask);
/* Reparent in case the dpll is in bypass */
if (cpu_is_omap24xx()) {
if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
v == OMAP2XXX_EN_DPLL_FRBYPASS)
clk_reparent(clk, dd->clk_bypass);
} else if (cpu_is_omap34xx()) {
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
v == OMAP3XXX_EN_DPLL_FRBYPASS)
clk_reparent(clk, dd->clk_bypass);
} else if (cpu_is_omap44xx()) {
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
clk_reparent(clk, dd->clk_bypass);
}
return;
}
/**
* _omap2xxx_clk_commit - commit clock parent/rate changes in hardware
* @clk: struct clk *
......@@ -149,6 +181,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
* clockdomain pointer, and save it into the struct clk. Intended to be
* called during clk_register(). No return value.
*/
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
void omap2_init_clk_clkdm(struct clk *clk)
{
struct clockdomain *clkdm;
......@@ -166,6 +199,7 @@ void omap2_init_clk_clkdm(struct clk *clk)
"clkdm %s\n", clk->name, clk->clkdm_name);
}
}
#endif
/**
* omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
......@@ -247,6 +281,11 @@ u32 omap2_get_dpll_rate(struct clk *clk)
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
v == OMAP3XXX_EN_DPLL_FRBYPASS)
return dd->clk_bypass->rate;
} else if (cpu_is_omap44xx()) {
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
return dd->clk_bypass->rate;
}
v = __raw_readl(dd->mult_div1_reg);
......@@ -437,8 +476,10 @@ void omap2_clk_disable(struct clk *clk)
_omap2_clk_disable(clk);
if (clk->parent)
omap2_clk_disable(clk->parent);
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
if (clk->clkdm)
omap2_clkdm_clk_disable(clk->clkdm, clk);
#endif
}
}
......@@ -448,8 +489,10 @@ int omap2_clk_enable(struct clk *clk)
int ret = 0;
if (clk->usecount++ == 0) {
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
if (clk->clkdm)
omap2_clkdm_clk_enable(clk->clkdm, clk);
#endif
if (clk->parent) {
ret = omap2_clk_enable(clk->parent);
......@@ -468,8 +511,10 @@ int omap2_clk_enable(struct clk *clk)
return ret;
err:
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
if (clk->clkdm)
omap2_clkdm_clk_disable(clk->clkdm, clk);
#endif
clk->usecount--;
return ret;
}
......
arch/arm/mach-omap2/clock.h
浏览文件 @ 24ed45aa
/*
* linux/arch/arm/mach-omap2/clock.h
*
* Copyright (C) 2005-2008 Texas Instruments, Inc.
* Copyright (C) 2004-2008 Nokia Corporation
* Copyright (C) 2005-2009 Texas Instruments, Inc.
* Copyright (C) 2004-2009 Nokia Corporation
*
* Contacts:
* Richard Woodruff <r-woodruff2@ti.com>
......@@ -36,6 +36,17 @@
#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
#define OMAP3XXX_EN_DPLL_LOCKED 0x7
/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
#define OMAP4XXX_EN_DPLL_LOCKED 0x7
/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
#define DPLL_LOW_POWER_STOP 0x1
#define DPLL_LOW_POWER_BYPASS 0x5
#define DPLL_LOCKED 0x7
int omap2_clk_init(void);
int omap2_clk_enable(struct clk *clk);
void omap2_clk_disable(struct clk *clk);
......@@ -44,6 +55,14 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
unsigned long omap3_dpll_recalc(struct clk *clk);
unsigned long omap3_clkoutx2_recalc(struct clk *clk);
void omap3_dpll_allow_idle(struct clk *clk);
void omap3_dpll_deny_idle(struct clk *clk);
u32 omap3_dpll_autoidle_read(struct clk *clk);
int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
int omap3_noncore_dpll_enable(struct clk *clk);
void omap3_noncore_dpll_disable(struct clk *clk);
#ifdef CONFIG_OMAP_RESET_CLOCKS
void omap2_clk_disable_unused(struct clk *clk);
......@@ -63,6 +82,7 @@ unsigned long omap2_fixed_divisor_recalc(struct clk *clk);
long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
u32 omap2_get_dpll_rate(struct clk *clk);
void omap2_init_dpll_parent(struct clk *clk);
int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
void omap2_clk_prepare_for_reboot(void);
int omap2_dflt_clk_enable(struct clk *clk);
......@@ -72,29 +92,17 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
u8 *idlest_bit);
extern u8 cpu_mask;
extern const struct clkops clkops_omap2_dflt_wait;
extern const struct clkops clkops_omap2_dflt;
extern u8 cpu_mask;
extern struct clk_functions omap2_clk_functions;
extern struct clk *vclk, *sclk;
/* clksel_rate data common to 24xx/343x */
static const struct clksel_rate gpt_32k_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
{ .div = 0 }
};
static const struct clksel_rate gpt_sys_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
{ .div = 0 }
};
static const struct clksel_rate gfx_l3_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
{ .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
{ .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
{ .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
{ .div = 0 }
};
extern const struct clksel_rate gpt_32k_rates[];
extern const struct clksel_rate gpt_sys_rates[];
extern const struct clksel_rate gfx_l3_rates[];
#endif
arch/arm/mach-omap2/clock24xx.c → arch/arm/mach-omap2/clock2xxx.c
浏览文件 @ 24ed45aa
......@@ -31,205 +31,19 @@
#include <plat/clock.h>
#include <plat/sram.h>
#include <plat/prcm.h>
#include <plat/clkdev_omap.h>
#include <asm/div64.h>
#include <asm/clkdev.h>
#include <plat/sdrc.h>
#include "clock.h"
#include "clock2xxx.h"
#include "opp2xxx.h"
#include "prm.h"
#include "prm-regbits-24xx.h"
#include "cm.h"
#include "cm-regbits-24xx.h"
static const struct clkops clkops_oscck;
static const struct clkops clkops_fixed;
static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
void __iomem **idlest_reg,
u8 *idlest_bit);
/* 2430 I2CHS has non-standard IDLEST register */
static const struct clkops clkops_omap2430_i2chs_wait = {
.enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable,
.find_idlest = omap2430_clk_i2chs_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
};
#include "clock24xx.h"
struct omap_clk {
u32 cpu;
struct clk_lookup lk;
};
#define CLK(dev, con, ck, cp) \
{ \
.cpu = cp, \
.lk = { \
.dev_id = dev, \
.con_id = con, \
.clk = ck, \
}, \
}
#define CK_243X RATE_IN_243X
#define CK_242X RATE_IN_242X
static struct omap_clk omap24xx_clks[] = {
/* external root sources */
CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X),
CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X),
CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X),
CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X),
CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X),
/* internal analog sources */
CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X),
CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X),
CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X),
/* internal prcm root sources */
CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X),
CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X),
CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X),
CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X),
CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X),
CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X),
CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X),
CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X),
CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
CLK(NULL, "emul_ck", &emul_ck, CK_242X),
/* mpu domain clocks */
CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X),
/* dsp domain clocks */
CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X),
CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X),
CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
/* GFX domain clocks */
CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X),
CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X),
CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X),
/* Modem domain clocks */
CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
/* DSS domain clocks */
CLK("omapdss", "ick", &dss_ick, CK_243X | CK_242X),
CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X | CK_242X),
CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X | CK_242X),
CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X | CK_242X),
/* L3 domain clocks */
CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X),
CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X),
CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X),
/* L4 domain clocks */
CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X),
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X | CK_242X),
/* virtual meta-group clock */
CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
/* general l4 interface ck, multi-parent functional clk */
CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X),
CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X),
CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X),
CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X),
CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X),
CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X),
CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X),
CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X),
CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X),
CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X),
CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X),
CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X),
CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X),
CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X),
CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X),
CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X),
CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X),
CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X),
CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X),
CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X),
CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X),
CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X),
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X),
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X),
CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X),
CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X),
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X),
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X),
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X),
CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X),
CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X),
CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X),
CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X),
CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X),
CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X),
CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X),
CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X),
CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X),
CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X),
CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X),
CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X),
CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X),
CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X),
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X),
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X),
CLK(NULL, "icr_ick", &icr_ick, CK_243X),
CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X),
CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X),
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X),
CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X),
CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X),
CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X),
CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X),
CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X),
CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X),
CLK(NULL, "eac_ick", &eac_ick, CK_242X),
CLK(NULL, "eac_fck", &eac_fck, CK_242X),
CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X),
CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X),
CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X),
CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X),
CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X),
CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X),
CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X),
CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X),
CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X),
CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X),
CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X),
CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X),
CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X),
CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X),
CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X),
CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X),
CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X),
CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X),
CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X),
CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X),
CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X),
CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
};
/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
#define EN_APLL_STOPPED 0
......@@ -242,11 +56,12 @@ static struct omap_clk omap24xx_clks[] = {
/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
static struct prcm_config *curr_prcm_set;
static struct clk *vclk;
static struct clk *sclk;
const struct prcm_config *curr_prcm_set;
const struct prcm_config *rate_table;
static void __iomem *prcm_clksrc_ctrl;
struct clk *vclk, *sclk, *dclk;
void __iomem *prcm_clksrc_ctrl;
/*-------------------------------------------------------------------------
* Omap24xx specific clock functions
......@@ -271,6 +86,13 @@ static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
*idlest_bit = clk->enable_bit;
}
/* 2430 I2CHS has non-standard IDLEST register */
const struct clkops clkops_omap2430_i2chs_wait = {
.enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable,
.find_idlest = omap2430_clk_i2chs_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
};
/**
* omap2xxx_clk_get_core_rate - return the CORE_CLK rate
......@@ -282,7 +104,7 @@ static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
* struct clk *dpll_ck, which is a composite clock of dpll_ck and
* core_ck.
*/
static unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
{
long long core_clk;
u32 v;
......@@ -320,14 +142,14 @@ static void omap2_disable_osc_ck(struct clk *clk)
__raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
}
static const struct clkops clkops_oscck = {
.enable = &omap2_enable_osc_ck,
.disable = &omap2_disable_osc_ck,
const struct clkops clkops_oscck = {
.enable = omap2_enable_osc_ck,
.disable = omap2_disable_osc_ck,
};
#ifdef OLD_CK
/* Recalculate SYST_CLK */
static void omap2_sys_clk_recalc(struct clk * clk)
static void omap2_sys_clk_recalc(struct clk *clk)
{
u32 div = PRCM_CLKSRC_CTRL;
div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */
......@@ -338,7 +160,7 @@ static void omap2_sys_clk_recalc(struct clk * clk)
#endif /* OLD_CK */
/* Enable an APLL if off */
static int omap2_clk_fixed_enable(struct clk *clk)
static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
{
u32 cval, apll_mask;
......@@ -353,12 +175,7 @@ static int omap2_clk_fixed_enable(struct clk *clk)
cval |= apll_mask;
cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
if (clk == &apll96_ck)
cval = OMAP24XX_ST_96M_APLL;
else if (clk == &apll54_ck)
cval = OMAP24XX_ST_54M_APLL;
omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), status_mask,
clk->name);
/*
......@@ -368,8 +185,18 @@ static int omap2_clk_fixed_enable(struct clk *clk)
return 0;
}
static int omap2_clk_apll96_enable(struct clk *clk)
{
return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL);
}
static int omap2_clk_apll54_enable(struct clk *clk)
{
return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL);
}
/* Stop APLL */
static void omap2_clk_fixed_disable(struct clk *clk)
static void omap2_clk_apll_disable(struct clk *clk)
{
u32 cval;
......@@ -378,16 +205,21 @@ static void omap2_clk_fixed_disable(struct clk *clk)
cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
}
static const struct clkops clkops_fixed = {
.enable = &omap2_clk_fixed_enable,
.disable = &omap2_clk_fixed_disable,
const struct clkops clkops_apll96 = {
.enable = omap2_clk_apll96_enable,
.disable = omap2_clk_apll_disable,
};
const struct clkops clkops_apll54 = {
.enable = omap2_clk_apll54_enable,
.disable = omap2_clk_apll_disable,
};
/*
* Uses the current prcm set to tell if a rate is valid.
* You can go slower, but not faster within a given rate set.
*/
static long omap2_dpllcore_round_rate(unsigned long target_rate)
long omap2_dpllcore_round_rate(unsigned long target_rate)
{
u32 high, low, core_clk_src;
......@@ -416,19 +248,19 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate)
}
static unsigned long omap2_dpllcore_recalc(struct clk *clk)
unsigned long omap2_dpllcore_recalc(struct clk *clk)
{
return omap2xxx_clk_get_core_rate(clk);
}
static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
{
u32 cur_rate, low, mult, div, valid_rate, done_rate;
u32 bypass = 0;
struct prcm_config tmpset;
const struct dpll_data *dd;
cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
cur_rate = omap2xxx_clk_get_core_rate(dclk);
mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
mult &= OMAP24XX_CORE_CLK_SRC_MASK;
......@@ -495,7 +327,7 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
*
* Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
*/
static unsigned long omap2_table_mpu_recalc(struct clk *clk)
unsigned long omap2_table_mpu_recalc(struct clk *clk)
{
return curr_prcm_set->mpu_speed;
}
......@@ -507,20 +339,20 @@ static unsigned long omap2_table_mpu_recalc(struct clk *clk)
* Some might argue L3-DDR, others ARM, others IVA. This code is simple and
* just uses the ARM rates.
*/
static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
{
struct prcm_config *ptr;
const struct prcm_config *ptr;
long highest_rate;
long sys_ck_rate;
if (clk != &virt_prcm_set)
return -EINVAL;
sys_ck_rate = clk_get_rate(sclk);
highest_rate = -EINVAL;
for (ptr = rate_table; ptr->mpu_speed; ptr++) {
if (!(ptr->flags & cpu_mask))
continue;
if (ptr->xtal_speed != sys_ck.rate)
if (ptr->xtal_speed != sys_ck_rate)
continue;
highest_rate = ptr->mpu_speed;
......@@ -533,21 +365,21 @@ static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
}
/* Sets basic clocks based on the specified rate */
static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
int omap2_select_table_rate(struct clk *clk, unsigned long rate)
{
u32 cur_rate, done_rate, bypass = 0, tmp;
struct prcm_config *prcm;
const struct prcm_config *prcm;
unsigned long found_speed = 0;
unsigned long flags;
long sys_ck_rate;
if (clk != &virt_prcm_set)
return -EINVAL;
sys_ck_rate = clk_get_rate(sclk);
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
if (!(prcm->flags & cpu_mask))
continue;
if (prcm->xtal_speed != sys_ck.rate)
if (prcm->xtal_speed != sys_ck_rate)
continue;
if (prcm->mpu_speed <= rate) {
......@@ -563,7 +395,7 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
}
curr_prcm_set = prcm;
cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
cur_rate = omap2xxx_clk_get_core_rate(dclk);
if (prcm->dpll_speed == cur_rate / 2) {
omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
......@@ -653,7 +485,7 @@ void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
}
#endif
static struct clk_functions omap2_clk_functions = {
struct clk_functions omap2_clk_functions = {
.clk_enable = omap2_clk_enable,
.clk_disable = omap2_clk_disable,
.clk_round_rate = omap2_clk_round_rate,
......@@ -694,12 +526,12 @@ static u32 omap2_get_sysclkdiv(void)
return div;
}
static unsigned long omap2_osc_clk_recalc(struct clk *clk)
unsigned long omap2_osc_clk_recalc(struct clk *clk)
{
return omap2_get_apll_clkin() * omap2_get_sysclkdiv();
}
static unsigned long omap2_sys_clk_recalc(struct clk *clk)
unsigned long omap2_sys_clk_recalc(struct clk *clk)
{
return clk->parent->rate / omap2_get_sysclkdiv();
}
......@@ -724,82 +556,32 @@ void omap2_clk_prepare_for_reboot(void)
*/
static int __init omap2_clk_arch_init(void)
{
struct clk *virt_prcm_set, *sys_ck, *dpll_ck, *mpu_ck;
unsigned long sys_ck_rate;
if (!mpurate)
return -EINVAL;
if (clk_set_rate(&virt_prcm_set, mpurate))
virt_prcm_set = clk_get(NULL, "virt_prcm_set");
sys_ck = clk_get(NULL, "sys_ck");
dpll_ck = clk_get(NULL, "dpll_ck");
mpu_ck = clk_get(NULL, "mpu_ck");
if (clk_set_rate(virt_prcm_set, mpurate))
printk(KERN_ERR "Could not find matching MPU rate\n");
recalculate_root_clocks();
printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
"%ld.%01ld/%ld/%ld MHz\n",
(sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
(dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
sys_ck_rate = clk_get_rate(sys_ck);
pr_info("Switched to new clocking rate (Crystal/DPLL/MPU): "
"%ld.%01ld/%ld/%ld MHz\n",
(sys_ck_rate / 1000000), (sys_ck_rate / 100000) % 10,
(clk_get_rate(dpll_ck) / 1000000),
(clk_get_rate(mpu_ck) / 1000000));
return 0;
}
arch_initcall(omap2_clk_arch_init);
int __init omap2_clk_init(void)
{
struct prcm_config *prcm;
struct omap_clk *c;
u32 clkrate;
if (cpu_is_omap242x()) {
prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
cpu_mask = RATE_IN_242X;
} else if (cpu_is_omap2430()) {
prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
cpu_mask = RATE_IN_243X;
}
clk_init(&omap2_clk_functions);
for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
clk_preinit(c->lk.clk);
osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
propagate_rate(&osc_ck);
sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);
propagate_rate(&sys_ck);
for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
if (c->cpu & cpu_mask) {
clkdev_add(&c->lk);
clk_register(c->lk.clk);
omap2_init_clk_clkdm(c->lk.clk);
}
/* Check the MPU rate set by bootloader */
clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
if (!(prcm->flags & cpu_mask))
continue;
if (prcm->xtal_speed != sys_ck.rate)
continue;
if (prcm->dpll_speed <= clkrate)
break;
}
curr_prcm_set = prcm;
recalculate_root_clocks();
printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
"%ld.%01ld/%ld/%ld MHz\n",
(sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
(dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
/*
* Only enable those clocks we will need, let the drivers
* enable other clocks as necessary
*/
clk_enable_init_clocks();
/* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
vclk = clk_get(NULL, "virt_prcm_set");
sclk = clk_get(NULL, "sys_ck");
return 0;
}
arch/arm/mach-omap2/clock2xxx.h 0 → 100644
浏览文件 @ 24ed45aa
/*
* OMAP2 clock function prototypes and macros
*
* Copyright (C) 2005-2009 Texas Instruments, Inc.
* Copyright (C) 2004-2009 Nokia Corporation
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_24XX_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK_24XX_H
unsigned long omap2_table_mpu_recalc(struct clk *clk);
int omap2_select_table_rate(struct clk *clk, unsigned long rate);
long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
unsigned long omap2_sys_clk_recalc(struct clk *clk);
unsigned long omap2_osc_clk_recalc(struct clk *clk);
unsigned long omap2_sys_clk_recalc(struct clk *clk);
unsigned long omap2_dpllcore_recalc(struct clk *clk);
int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
unsigned long omap2xxx_clk_get_core_rate(struct clk *clk);
/* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */
#ifdef CONFIG_ARCH_OMAP2420
#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2420_PRCM_CLKOUT_CTRL
#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2420_PRCM_CLKEMUL_CTRL
#else
#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2430_PRCM_CLKOUT_CTRL
#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2430_PRCM_CLKEMUL_CTRL
#endif
extern void __iomem *prcm_clksrc_ctrl;
extern struct clk *dclk;
extern const struct clkops clkops_omap2430_i2chs_wait;
extern const struct clkops clkops_oscck;
extern const struct clkops clkops_apll96;
extern const struct clkops clkops_apll54;
#endif
arch/arm/mach-omap2/clock34xx.c
浏览文件 @ 24ed45aa
此差异已折叠。
arch/arm/mach-omap2/clock34xx.h
浏览文件 @ 24ed45aa
此差异已折叠。
arch/arm/mach-omap2/clock34xx_data.c 0 → 100644
浏览文件 @ 24ed45aa
此差异已折叠。
arch/arm/mach-omap2/clock44xx.c 0 → 100644
浏览文件 @ 24ed45aa
/*
* OMAP4-specific clock framework functions
*
* Copyright (C) 2009 Texas Instruments, Inc.
*
* Rajendra Nayak (rnayak@ti.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/errno.h>
#include "clock.h"
struct clk_functions omap2_clk_functions = {
.clk_enable = omap2_clk_enable,
.clk_disable = omap2_clk_disable,
.clk_round_rate = omap2_clk_round_rate,
.clk_set_rate = omap2_clk_set_rate,
.clk_set_parent = omap2_clk_set_parent,
.clk_disable_unused = omap2_clk_disable_unused,
};
const struct clkops clkops_noncore_dpll_ops = {
.enable = &omap3_noncore_dpll_enable,
.disable = &omap3_noncore_dpll_disable,
};
void omap2_clk_prepare_for_reboot(void)
{
return;
}
arch/arm/mach-omap2/clock44xx.h 0 → 100644
浏览文件 @ 24ed45aa
/*
* OMAP4 clock function prototypes and macros
*
* Copyright (C) 2009 Texas Instruments, Inc.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H
#define OMAP4430_MAX_DPLL_MULT 2048
#define OMAP4430_MAX_DPLL_DIV 128
extern const struct clkops clkops_noncore_dpll_ops;
#endif
arch/arm/mach-omap2/clock44xx_data.c 0 → 100644
浏览文件 @ 24ed45aa
此差异已折叠。
arch/arm/mach-omap2/clock_common_data.c 0 → 100644
浏览文件 @ 24ed45aa
/*
* linux/arch/arm/mach-omap2/clock_common_data.c
*
* Copyright (C) 2005-2009 Texas Instruments, Inc.
* Copyright (C) 2004-2009 Nokia Corporation
*
* Contacts:
* Richard Woodruff <r-woodruff2@ti.com>
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This file contains clock data that is common to both the OMAP2xxx and
* OMAP3xxx clock definition files.
*/
#include "clock.h"
/* clksel_rate data common to 24xx/343x */
const struct clksel_rate gpt_32k_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
{ .div = 0 }
};
const struct clksel_rate gpt_sys_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
{ .div = 0 }
};
const struct clksel_rate gfx_l3_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
{ .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
{ .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
{ .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
{ .div = 0 }
};
arch/arm/mach-omap2/clockdomain.c
浏览文件 @ 24ed45aa
......@@ -2,7 +2,7 @@
* OMAP2/3 clockdomain framework functions
*
* Copyright (C) 2008 Texas Instruments, Inc.
* Copyright (C) 2008 Nokia Corporation
* Copyright (C) 2008-2009 Nokia Corporation
*
* Written by Paul Walmsley and Jouni Högander
*
......@@ -10,9 +10,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifdef CONFIG_OMAP_DEBUG_CLOCKDOMAIN
# define DEBUG
#endif
#undef DEBUG
#include <linux/module.h>
#include <linux/kernel.h>
......
arch/arm/mach-omap2/cm-regbits-44xx.h 0 → 100644
浏览文件 @ 24ed45aa
此差异已折叠。
arch/arm/mach-omap2/cm.c
浏览文件 @ 24ed45aa
......@@ -21,6 +21,8 @@
#include <asm/atomic.h>
#include <plat/common.h>
#include "cm.h"
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
......@@ -61,9 +63,8 @@ int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
mask = 1 << idlest_shift;
/* XXX should be OMAP2 CM */
while (((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) != ena) &&
(i++ < MAX_MODULE_READY_TIME))
udelay(1);
omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
MAX_MODULE_READY_TIME, i);
return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
}
......
arch/arm/mach-omap2/cm.h
浏览文件 @ 24ed45aa
......@@ -4,8 +4,8 @@
/*
* OMAP2/3 Clock Management (CM) register definitions
*
* Copyright (C) 2007-2008 Texas Instruments, Inc.
* Copyright (C) 2007-2008 Nokia Corporation
* Copyright (C) 2007-2009 Texas Instruments, Inc.
* Copyright (C) 2007-2009 Nokia Corporation
*
* Written by Paul Walmsley
*
......@@ -22,6 +22,12 @@
OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
#define OMAP34XX_CM_REGADDR(module, reg) \
OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
#define OMAP44XX_CM1_REGADDR(module, reg) \
OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg))
#define OMAP44XX_CM2_REGADDR(module, reg) \
OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg))
#include "cm44xx.h"
/*
* Architecture-specific global CM registers
......@@ -89,6 +95,11 @@
#define OMAP3430_CM_CLKSEL2_EMU 0x0050
#define OMAP3430_CM_CLKSEL3_EMU 0x0054
/* CM2.CEFUSE_CM2 register offsets */
/* OMAP4 modulemode control */
#define OMAP4430_MODULEMODE_HWCTRL 0
#define OMAP4430_MODULEMODE_SWCTRL 1
/* Clock management domain register get/set */
......
arch/arm/mach-omap2/cm44xx.h 0 → 100644
浏览文件 @ 24ed45aa
此差异已折叠。
arch/arm/mach-omap2/dpll.c 0 → 100644
浏览文件 @ 24ed45aa
此差异已折叠。
arch/arm/mach-omap2/gpmc.c
浏览文件 @ 24ed45aa
......@@ -517,7 +517,7 @@ void __init gpmc_init(void)
ck = "gpmc_fck";
l = OMAP34XX_GPMC_BASE;
} else if (cpu_is_omap44xx()) {
ck = "gpmc_fck";
ck = "gpmc_ck";
l = OMAP44XX_GPMC_BASE;
}
......
arch/arm/mach-omap2/io.c
浏览文件 @ 24ed45aa
......@@ -35,7 +35,6 @@
#include <plat/serial.h>
#include <plat/vram.h>
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdev is ready */
#include "clock.h"
#include <plat/omap-pm.h>
......@@ -44,7 +43,6 @@
#include <plat/clockdomain.h>
#include "clockdomains.h"
#endif
#include <plat/omap_hwmod.h>
#include "omap_hwmod_2420.h"
#include "omap_hwmod_2430.h"
......@@ -321,8 +319,8 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
pwrdm_init(powerdomains_omap);
clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
omap2_clk_init();
#endif
omap2_clk_init();
omap_serial_early_init();
#ifndef CONFIG_ARCH_OMAP4
omap_hwmod_late_init();
......
arch/arm/mach-omap2/omap_hwmod.c
浏览文件 @ 24ed45aa
......@@ -45,6 +45,7 @@
#include <linux/mutex.h>
#include <linux/bootmem.h>
#include <plat/common.h>
#include <plat/cpu.h>
#include <plat/clockdomain.h>
#include <plat/powerdomain.h>
......@@ -209,6 +210,32 @@ static int _set_softreset(struct omap_hwmod *oh, u32 *v)
return 0;
}
/**
* _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v
* @oh: struct omap_hwmod *
* @autoidle: desired AUTOIDLE bitfield value (0 or 1)
* @v: pointer to register contents to modify
*
* Update the module autoidle bit in @v to be @autoidle for the @oh
* hwmod. The autoidle bit controls whether the module can gate
* internal clocks automatically when it isn't doing anything; the
* exact function of this bit varies on a per-module basis. This
* function does not write to the hardware. Returns -EINVAL upon
* error or 0 upon success.
*/
static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
u32 *v)
{
if (!oh->sysconfig ||
!(oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE))
return -EINVAL;
*v &= ~SYSC_AUTOIDLE_MASK;
*v |= autoidle << SYSC_AUTOIDLE_SHIFT;
return 0;
}
/**
* _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
* @oh: struct omap_hwmod *
......@@ -326,6 +353,9 @@ static int _init_main_clk(struct omap_hwmod *oh)
ret = -EINVAL;
oh->_clk = c;
WARN(!c->clkdm, "omap_hwmod: %s: missing clockdomain for %s.\n",
oh->clkdev_con_id, c->name);
return ret;
}
......@@ -557,8 +587,19 @@ static void _sysc_enable(struct omap_hwmod *oh)
_set_master_standbymode(oh, idlemode, &v);
}
/* XXX OCP AUTOIDLE bit? */
if (oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE) {
idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ?
0 : 1;
_set_module_autoidle(oh, idlemode, &v);
}
/* XXX OCP ENAWAKEUP bit? */
/*
* XXX The clock framework should handle this, by
* calling into this code. But this must wait until the
* clock structures are tagged with omap_hwmod entries
*/
if (oh->flags & HWMOD_SET_DEFAULT_CLOCKACT &&
oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY)
_set_clockactivity(oh, oh->sysconfig->clockact, &v);
......@@ -622,7 +663,8 @@ static void _sysc_shutdown(struct omap_hwmod *oh)
if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE)
_set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v);
/* XXX clear OCP AUTOIDLE bit? */
if (oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE)
_set_module_autoidle(oh, 1, &v);
_write_sysconfig(v, oh);
}
......@@ -736,7 +778,7 @@ static int _wait_target_ready(struct omap_hwmod *oh)
static int _reset(struct omap_hwmod *oh)
{
u32 r, v;
int c;
int c = 0;
if (!oh->sysconfig ||
!(oh->sysconfig->sysc_flags & SYSC_HAS_SOFTRESET) ||
......@@ -758,13 +800,9 @@ static int _reset(struct omap_hwmod *oh)
return r;
_write_sysconfig(v, oh);
c = 0;
while (c < MAX_MODULE_RESET_WAIT &&
!(omap_hwmod_readl(oh, oh->sysconfig->syss_offs) &
SYSS_RESETDONE_MASK)) {
udelay(1);
c++;
}
omap_test_timeout((omap_hwmod_readl(oh, oh->sysconfig->syss_offs) &
SYSS_RESETDONE_MASK),
MAX_MODULE_RESET_WAIT, c);
if (c == MAX_MODULE_RESET_WAIT)
WARN(1, "omap_hwmod: %s: failed to reset in %d usec\n",
......@@ -883,33 +921,6 @@ static int _shutdown(struct omap_hwmod *oh)
return 0;
}
/**
* _write_clockact_lock - set the module's clockactivity bits
* @oh: struct omap_hwmod *
* @clockact: CLOCKACTIVITY field bits
*
* Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
* OCP_SYSCONFIG register. Returns -EINVAL if the hwmod is in the
* wrong state or returns 0.
*/
static int _write_clockact_lock(struct omap_hwmod *oh, u8 clockact)
{
u32 v;
if (!oh->sysconfig ||
!(oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY))
return -EINVAL;
mutex_lock(&omap_hwmod_mutex);
v = oh->_sysc_cache;
_set_clockactivity(oh, clockact, &v);
_write_sysconfig(v, oh);
mutex_unlock(&omap_hwmod_mutex);
return 0;
}
/**
* _setup - do initial configuration of omap_hwmod
* @oh: struct omap_hwmod *
......@@ -948,11 +959,19 @@ static int _setup(struct omap_hwmod *oh)
_enable(oh);
if (!(oh->flags & HWMOD_INIT_NO_RESET))
_reset(oh);
/* XXX OCP AUTOIDLE bit? */
/* XXX OCP ENAWAKEUP bit? */
if (!(oh->flags & HWMOD_INIT_NO_RESET)) {
/*
* XXX Do the OCP_SYSCONFIG bits need to be
* reprogrammed after a reset? If not, then this can
* be removed. If they do, then probably the
* _enable() function should be split to avoid the
* rewrite of the OCP_SYSCONFIG register.
*/
if (oh->sysconfig) {
_update_sysc_cache(oh);
_sysc_enable(oh);
}
}
if (!(oh->flags & HWMOD_INIT_NO_IDLE))
_idle(oh);
......@@ -1348,8 +1367,9 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
/* For each IRQ, DMA, memory area, fill in array.*/
for (i = 0; i < oh->mpu_irqs_cnt; i++) {
(res + r)->start = *(oh->mpu_irqs + i);
(res + r)->end = *(oh->mpu_irqs + i);
(res + r)->name = (oh->mpu_irqs + i)->name;
(res + r)->start = (oh->mpu_irqs + i)->irq;
(res + r)->end = (oh->mpu_irqs + i)->irq;
(res + r)->flags = IORESOURCE_IRQ;
r++;
}
......@@ -1453,62 +1473,6 @@ int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
return _del_initiator_dep(oh, init_oh);
}
/**
* omap_hwmod_set_clockact_none - set clockactivity test to BOTH
* @oh: struct omap_hwmod *
*
* On some modules, this function can affect the wakeup latency vs.
* power consumption balance. Intended to be called by the
* omap_device layer. Passes along the return value from
* _write_clockact_lock().
*/
int omap_hwmod_set_clockact_both(struct omap_hwmod *oh)
{
return _write_clockact_lock(oh, CLOCKACT_TEST_BOTH);
}
/**
* omap_hwmod_set_clockact_none - set clockactivity test to MAIN
* @oh: struct omap_hwmod *
*
* On some modules, this function can affect the wakeup latency vs.
* power consumption balance. Intended to be called by the
* omap_device layer. Passes along the return value from
* _write_clockact_lock().
*/
int omap_hwmod_set_clockact_main(struct omap_hwmod *oh)
{
return _write_clockact_lock(oh, CLOCKACT_TEST_MAIN);
}
/**
* omap_hwmod_set_clockact_none - set clockactivity test to ICLK
* @oh: struct omap_hwmod *
*
* On some modules, this function can affect the wakeup latency vs.
* power consumption balance. Intended to be called by the
* omap_device layer. Passes along the return value from
* _write_clockact_lock().
*/
int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh)
{
return _write_clockact_lock(oh, CLOCKACT_TEST_ICLK);
}
/**
* omap_hwmod_set_clockact_none - set clockactivity test to NONE
* @oh: struct omap_hwmod *
*
* On some modules, this function can affect the wakeup latency vs.
* power consumption balance. Intended to be called by the
* omap_device layer. Passes along the return value from
* _write_clockact_lock().
*/
int omap_hwmod_set_clockact_none(struct omap_hwmod *oh)
{
return _write_clockact_lock(oh, CLOCKACT_TEST_NONE);
}
/**
* omap_hwmod_enable_wakeup - allow device to wake up the system
* @oh: struct omap_hwmod *
......
arch/arm/mach-omap2/opp2420_data.c 0 → 100644
浏览文件 @ 24ed45aa
/*
* opp2420_data.c - old-style "OPP" table for OMAP2420
*
* Copyright (C) 2005-2009 Texas Instruments, Inc.
* Copyright (C) 2004-2009 Nokia Corporation
*
* Richard Woodruff <r-woodruff2@ti.com>
*
* The OMAP2 processor can be run at several discrete 'PRCM configurations'.
* These configurations are characterized by voltage and speed for clocks.
* The device is only validated for certain combinations. One way to express
* these combinations is via the 'ratio's' which the clocks operate with
* respect to each other. These ratio sets are for a given voltage/DPLL
* setting. All configurations can be described by a DPLL setting and a ratio
* There are 3 ratio sets for the 2430 and X ratio sets for 2420.
*
* 2430 differs from 2420 in that there are no more phase synchronizers used.
* They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
* 2430 (iva2.1, NOdsp, mdm)
*
* XXX Missing voltage data.
*
* THe format described in this file is deprecated. Once a reasonable
* OPP API exists, the data in this file should be converted to use it.
*
* This is technically part of the OMAP2xxx clock code.
*/
#include "opp2xxx.h"
#include "sdrc.h"
#include "clock.h"
/*-------------------------------------------------------------------------
* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
* xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
* CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
* CM_CLKSEL2_PLL, CM_CLKSEL_MDM
*
* Filling in table based on H4 boards and 2430-SDPs variants available.
* There are quite a few more rates combinations which could be defined.
*
* When multiple values are defined the start up will try and choose the
* fastest one. If a 'fast' value is defined, then automatically, the /2
* one should be included as it can be used. Generally having more that
* one fast set does not make sense, as static timings need to be changed
* to change the set. The exception is the bypass setting which is
* availble for low power bypass.
*
* Note: This table needs to be sorted, fastest to slowest.
*-------------------------------------------------------------------------*/
const struct prcm_config omap2420_rate_table[] = {
/* PRCM I - FAST */
{S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
RATE_IN_242X},
/* PRCM II - FAST */
{S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
RATE_IN_242X},
{S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
RATE_IN_242X},
/* PRCM III - FAST */
{S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
RATE_IN_242X},
{S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
RATE_IN_242X},
/* PRCM II - SLOW */
{S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
RATE_IN_242X},
{S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
RATE_IN_242X},
/* PRCM III - SLOW */
{S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
RATE_IN_242X},
{S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
RATE_IN_242X},
/* PRCM-VII (boot-bypass) */
{S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
RATE_IN_242X},
/* PRCM-VII (boot-bypass) */
{S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
RATE_IN_242X},
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
};
arch/arm/mach-omap2/opp2430_data.c 0 → 100644
浏览文件 @ 24ed45aa
此差异已折叠。
arch/arm/mach-omap2/opp2xxx.h 0 → 100644
浏览文件 @ 24ed45aa
此差异已折叠。
arch/arm/mach-omap2/pm-debug.c
浏览文件 @ 24ed45aa
......@@ -326,7 +326,7 @@ int pm_dbg_regset_save(int reg_set)
return 0;
}
static const char pwrdm_state_names[][4] = {
static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = {
"OFF",
"RET",
"INA",
......@@ -381,7 +381,7 @@ static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user)
seq_printf(s, "%s (%s)", pwrdm->name,
pwrdm_state_names[pwrdm->state]);
for (i = 0; i < 4; i++)
for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
seq_printf(s, ",%s:%d", pwrdm_state_names[i],
pwrdm->state_counter[i]);
......
arch/arm/mach-omap2/powerdomain.c
浏览文件 @ 24ed45aa
此差异已折叠。
arch/arm/mach-omap2/powerdomains34xx.h
浏览文件 @ 24ed45aa
......@@ -190,6 +190,7 @@ static struct powerdomain mpu_34xx_pwrdm = {
.wkdep_srcs = mpu_34xx_wkdeps,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.flags = PWRDM_HAS_MPU_QUIRK,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET,
......
arch/arm/mach-omap2/prcm-common.h
浏览文件 @ 24ed45aa
......@@ -4,10 +4,12 @@
/*
* OMAP2/3 PRCM base and module definitions
*
* Copyright (C) 2007-2008 Texas Instruments, Inc.
* Copyright (C) 2007-2008 Nokia Corporation
* Copyright (C) 2007-2009 Texas Instruments, Inc.
* Copyright (C) 2007-2009 Nokia Corporation
*
* Written by Paul Walmsley
* OMAP4 defines in this file are automatically generated from the OMAP hardware
* databases.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......@@ -49,6 +51,73 @@
#define OMAP3430_NEON_MOD 0xb00
#define OMAP3430ES2_USBHOST_MOD 0xc00
#define BITS(n_bit) \
(((1 << n_bit) - 1) | (1 << n_bit))
#define BITFIELD(l_bit, u_bit) \
(BITS(u_bit) & ~((BITS(l_bit)) >> 1))
/* OMAP44XX specific module offsets */
/* CM1 instances */
#define OMAP4430_CM1_OCP_SOCKET_MOD 0x0000
#define OMAP4430_CM1_CKGEN_MOD 0x0100
#define OMAP4430_CM1_MPU_MOD 0x0300
#define OMAP4430_CM1_TESLA_MOD 0x0400
#define OMAP4430_CM1_ABE_MOD 0x0500
#define OMAP4430_CM1_RESTORE_MOD 0x0e00
#define OMAP4430_CM1_INSTR_MOD 0x0f00
/* CM2 instances */
#define OMAP4430_CM2_OCP_SOCKET_MOD 0x0000
#define OMAP4430_CM2_CKGEN_MOD 0x0100
#define OMAP4430_CM2_ALWAYS_ON_MOD 0x0600
#define OMAP4430_CM2_CORE_MOD 0x0700
#define OMAP4430_CM2_IVAHD_MOD 0x0f00
#define OMAP4430_CM2_CAM_MOD 0x1000
#define OMAP4430_CM2_DSS_MOD 0x1100
#define OMAP4430_CM2_GFX_MOD 0x1200
#define OMAP4430_CM2_L3INIT_MOD 0x1300
#define OMAP4430_CM2_L4PER_MOD 0x1400
#define OMAP4430_CM2_CEFUSE_MOD 0x1600
#define OMAP4430_CM2_RESTORE_MOD 0x1e00
#define OMAP4430_CM2_INSTR_MOD 0x1f00
/* PRM instances */
#define OMAP4430_PRM_OCP_SOCKET_MOD 0x0000
#define OMAP4430_PRM_CKGEN_MOD 0x0100
#define OMAP4430_PRM_MPU_MOD 0x0300
#define OMAP4430_PRM_TESLA_MOD 0x0400
#define OMAP4430_PRM_ABE_MOD 0x0500
#define OMAP4430_PRM_ALWAYS_ON_MOD 0x0600
#define OMAP4430_PRM_CORE_MOD 0x0700
#define OMAP4430_PRM_IVAHD_MOD 0x0f00
#define OMAP4430_PRM_CAM_MOD 0x1000
#define OMAP4430_PRM_DSS_MOD 0x1100
#define OMAP4430_PRM_GFX_MOD 0x1200
#define OMAP4430_PRM_L3INIT_MOD 0x1300
#define OMAP4430_PRM_L4PER_MOD 0x1400
#define OMAP4430_PRM_CEFUSE_MOD 0x1600
#define OMAP4430_PRM_WKUP_MOD 0x1700
#define OMAP4430_PRM_WKUP_CM_MOD 0x1800
#define OMAP4430_PRM_EMU_MOD 0x1900
#define OMAP4430_PRM_EMU_CM_MOD 0x1a00
#define OMAP4430_PRM_DEVICE_MOD 0x1b00
#define OMAP4430_PRM_INSTR_MOD 0x1f00
/* SCRM instances */
#define OMAP4430_SCRM_SCRM_MOD 0x0000
/* CHIRONSS instances */
#define OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD 0x0000
#define OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD 0x0200
#define OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD 0x0400
#define OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD 0x0800
/* 24XX register bits shared between CM & PRM registers */
......
arch/arm/mach-omap2/prcm.c
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arch/arm/mach-omap2/prm-regbits-44xx.h 0 → 100644
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arch/arm/mach-omap2/prm.h
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......@@ -4,8 +4,8 @@
/*
* OMAP2/3 Power/Reset Management (PRM) register definitions
*
* Copyright (C) 2007 Texas Instruments, Inc.
* Copyright (C) 2007 Nokia Corporation
* Copyright (C) 2007-2009 Texas Instruments, Inc.
* Copyright (C) 2009 Nokia Corporation
*
* Written by Paul Walmsley
*
......@@ -22,6 +22,10 @@
OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
#define OMAP34XX_PRM_REGADDR(module, reg) \
OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
#define OMAP44XX_PRM_REGADDR(module, reg) \
OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
#include "prm44xx.h"
/*
* Architecture-specific global PRM registers
......
arch/arm/mach-omap2/prm44xx.h 0 → 100644
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arch/arm/mach-omap2/sdrc.h
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arch/arm/mach-omap2/sram34xx.S
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arch/arm/plat-omap/Kconfig
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arch/arm/plat-omap/clock.c
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arch/arm/plat-omap/common.c
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arch/arm/plat-omap/include/plat/clkdev_omap.h 0 → 100644
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arch/arm/plat-omap/omap_device.c
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