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    MIPS: DECstation I/O ASIC DMA interrupt handling fix · 5359b938
    Maciej W. Rozycki 提交于
    This change complements commit d0da7c002f7b2a93582187a9e3f73891a01d8ee4
    and brings clear_ioasic_irq back, renaming it to clear_ioasic_dma_irq at
    the same time, to make I/O ASIC DMA interrupts functional.
    
    Unlike ordinary I/O ASIC interrupts DMA interrupts need to be deasserted
    by software by writing 0 to the respective bit in I/O ASIC's System
    Interrupt Register (SIR), similarly to how CP0.Cause.IP0 and CP0.Cause.IP1
    bits are handled in the CPU (the difference is SIR DMA interrupt bits are
    R/W0C so there's no need for an RMW cycle).  Otherwise the handler is
    reentered over and over again.
    
    The only current user is the DEC LANCE Ethernet driver and its extremely
    uncommon DMA memory error handler that does not care when exactly the
    interrupt is cleared.  Anticipating the use of DMA interrupts by the Zilog
    SCC driver this change however exports clear_ioasic_dma_irq for device
    drivers to choose the right application-specific sequence to clear the
    request explicitly rather than calling it implicitly in the .irq_eoi
    handler of `struct irq_chip'.  Previously these interrupts were cleared in
    the .end handler of the said structure, before it was removed.
    Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
    Cc: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/5826/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
    5359b938
declance.c 34.6 KB