add STM32L1 HAL DRIVER

修复 scons --target=eclipse 时，部分带值宏出错的问题

Fixed typos in Kconfig

Aarch64 cache api

fixed a typo

1. modify at32_msp default configuration 2. add hwtimer driver and fi…

[readme/update] readme architecture figures

1. modify at32_msp default configuration 2. add hwtimer driver and fix up some driver errors 3. update related files

update readme ：Fixed spelling mistakes

[Sensor] Support custom commands for rt_sensor_control

[skip ci] Update README.md

component: sdio: fix potential ricky clock setting

MM32L073PF ->  MM32L373PF

spi: support slave mode and master mode runtime config

Support msc mode automatic switching

Currently RTT mmc stack only support Highspeed mode or
blow, which means the max speed should be 52MHz according
to JEDEC spec. Two problems show here:

(1) max_data_rate = (unsigned int)-1. The value of unsigned int
depends on compilers/arch. Moreover, it makes no sense to assume
cpu addressing width with IP clock rate limit.
(1)hs_max_data_rate was set to 200MHz.

So what should BSP drivers do if 52MHz < max_data_rate < 200MHz?
Either it blindly sets a spec-violated clock rate to drive a Highspeed
card, or just adjust the clock rate internally. Both cases are
really bad for practice.

If the card claims to support Highspeed, we set the clock to not
to exceed 52MHz. Otherwise it should be set according to
card->max_data_rate parsed by ext_csd. This patch fixes it as-is,
and also simplify the code a lot.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>

Signed-off-by: NCliff Chen <cliff.chen@rock-chips.com>

support slave mode and master mode runtime config.

Change-Id: Iabadbade8997bb8e3adef8ce95f6c45f6bb35329
Signed-off-by: NYifeng Zhao <yifeng.zhao@rock-chips.com>

Fixed a hidden stack overflow bug

[bsp]Fixed a  stack overflow bug in drv_crypto.c

[bsp][stm32/pandora]增加对板载 AP6181 的支持

Added if null before used.

rt_malloc -> rt_calloc

Fix bug for synopsys_emac.c

update readme