[BSP] add i.MX 6UL BSP

bsp/imx6ul/KConfig

+mainmenu "RT-Thread Configuration"
+
+config $BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config $RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config $PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+config BOARD_IMX6UL
+    bool 
+    select ARCH_ARM_CORTEX_A7
+    default y
+
+source "$RTT_DIR/KConfig"
+source "$PKGS_DIR/KConfig"
+
+source "$BSP_DIR/drivers/Kconfig"

bsp/imx6ul/Makefile

+scons:=python ${SCONS}\scons.py
+
+all:
+	@$(scons)
+
+clean:
+	@$(scons) -c
+
+copy:
+	@$(scons) --copy -s

bsp/imx6ul/README.md

+# i.MX6 SoloX
+
+Freescale's Smart Application Blueprint for Rapid Engineering (SABRE) board for smart devices
+
+Rev.B
+
+CPU: MCIMX6X4EVM10AB
+
+* ARM Cortex-A9 @ 1GHz
+* ARM Cortex-M4 @ 200MHz
+
+* Freescale PF0200 PMIC
+* 1GB DDR3
+* 32 MB x2 QuadSPI Flash
+
+* Freescale MMA8451 3-Axis Accelerometer
+* Freescale MAG3110 3D Magnetometer

bsp/imx6ul/SConscript

+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/imx6ul/SConstruct

+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.join(os.getcwd(), '..', '..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-imx6.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+        CXX= rtconfig.CXX, CXXFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/imx6ul/applications/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/imx6ul/applications/application.c

+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2012, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-11-20     Bernard    the first version
+ */
+
+#include <rtthread.h>
+
+#include <sdk_version.h>
+#include <ccm_pll.h>
+
+void show_freq(void)
+{
+    rt_kprintf("CPU: %d MHz\n", get_main_clock(CPU_CLK)/1000000);
+    rt_kprintf("DDR: %d MHz\n", get_main_clock(MMDC_CH0_AXI_CLK)/1000000);
+    rt_kprintf("IPG: %d MHz\n", get_main_clock(IPG_CLK)/1000000);
+}
+
+void init_thread(void* parameter)
+{
+    rt_kprintf("Freescale i.MX6 Platform SDK %s\n", SDK_VERSION_STRING);
+    show_freq();
+
+    rt_components_init();
+}
+
+int rt_application_init()
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("init", init_thread, RT_NULL,
+        1024, RT_THREAD_PRIORITY_MAX/3, 10);
+    if (tid != RT_NULL) rt_thread_startup(tid);
+
+    return 0;
+}
+

bsp/imx6ul/applications/startup.c

+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-12-05     Bernard      the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <board.h>
+
+extern int  rt_application_init(void);
+extern void rt_hw_board_init(void);
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+    // platform_init();
+    // print_version();
+
+    /* initialzie hardware interrupt */
+    rt_hw_interrupt_init();
+
+    /* initialize board */
+    rt_hw_board_init();
+
+    /* show RT-Thread version */
+    rt_show_version();
+
+    /* initialize memory system */
+#ifdef RT_USING_HEAP
+    rt_system_heap_init(HEAP_BEGIN, HEAP_END);
+#endif
+
+    /* initialize scheduler system */
+    rt_system_scheduler_init();
+
+    /* initialize timer and soft timer thread */
+    rt_system_timer_init();
+    rt_system_timer_thread_init();
+
+    /* initialize application */
+    rt_application_init();
+
+    /* initialize idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+int main(void)
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+
+    /* invoke rtthread_startup */
+    rtthread_startup();
+
+    return 0;
+}

bsp/imx6ul/drivers/SConscript

+from building import *
+
+cwd = GetCurrentDir()
+src	= Glob('*.c') + Glob('iomux/*.c')
+
+CPPPATH = [cwd, cwd + '/iomux']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/imx6ul/drivers/board.c

+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2016, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-11-20     Bernard    the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+#include <registers/regsarmglobaltimer.h>
+#include <registers/regsepit.h>
+
+#include <imx_uart.h>
+#include <epit.h>
+#include <cortex_a.h>
+
+static void rt_hw_timer_isr(int vector, void *param)
+{
+    rt_tick_increase();
+    epit_get_compare_event(HW_EPIT1);
+}
+
+int rt_hw_timer_init(void)
+{
+    uint32_t freq;
+
+    // Make sure the timer is off.
+    HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 0;
+    
+    HW_ARMGLOBALTIMER_CONTROL.B.FCR0 =1;
+    
+    HW_ARMGLOBALTIMER_CONTROL.B.FCR1 =0;
+    
+    HW_ARMGLOBALTIMER_CONTROL.B.DBG_ENABLE =0;
+    
+    // Clear counter.
+    HW_ARMGLOBALTIMER_COUNTER_HI_WR(0);
+    HW_ARMGLOBALTIMER_COUNTER_LO_WR(0);
+    
+    // Now turn on the timer.
+    HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 1;
+
+    freq = get_main_clock(IPG_CLK);
+
+    epit_init(HW_EPIT1, CLKSRC_IPG_CLK, freq / 1000000,
+              SET_AND_FORGET, 10000, WAIT_MODE_EN | STOP_MODE_EN);
+
+    epit_counter_enable(HW_EPIT1, 10000, IRQ_MODE);
+
+    rt_hw_interrupt_install(IMX_INT_EPIT1, rt_hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_umask(IMX_INT_EPIT1);
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_timer_init);
+
+/**
+ * This function will initialize hardware board
+ */
+void rt_hw_board_init(void)
+{
+    enable_neon_fpu();
+    disable_strict_align_check();
+
+    rt_components_board_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+}
+
+/*@}*/

bsp/imx6ul/drivers/board.h

+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-06     Bernard    the first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <registers.h>
+#include <irq_numbers.h>
+
+#define CONFIG_MX6
+#define CONFIG_MX6UL
+
+#if defined(__CC_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN      ((void*)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif defined(__GNUC__)
+extern int __bss_end;
+#define HEAP_BEGIN      ((void*)&__bss_end)
+#endif
+
+#define HEAP_END        (void*)(0x80000000 + 32 * 1024 * 1024)
+
+void rt_hw_board_init(void);
+
+#endif

bsp/imx6ul/drivers/iomux/iomux_config.c

+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+
+// Function to configure iomux for i.MX6SL board MCIMX6SLEVK rev. B.
+void iomux_config(void)
+{
+    uart1_iomux_config();
+}

bsp/imx6ul/drivers/iomux/iomux_config.h

+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: iomux_config.h
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#ifndef _IOMUX_CONFIG_H_
+#define _IOMUX_CONFIG_H_
+
+// Board and Module IOMUXC configuration function prototypes.
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+// Board IOMUXC configuration function.
+void iomux_config(void);
+
+// Module IOMUXC configuration functions.
+void uart1_iomux_config(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // _IOMUX_CONFIG_H_

bsp/imx6ul/drivers/iomux/uart_iomux_config.c

+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: uart_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsuart.h"
+#include "iomux_register.h"
+#include "io.h"
+#include <assert.h>
+
+#define MX6UL_PAD_UART1_TX_DATA__UART1_TX1	(IOMUXC_BASE_ADDR+0x084)
+#define MX6UL_PAD_UART1_RX_DATA__UART1_RX1	(IOMUXC_BASE_ADDR+0x088)
+#define IOMUXC_UART1_UART_RXD_MUX_SELECT_INPUT1 (IOMUXC_BASE_ADDR+0x624)
+
+void uart1_iomux_config(void)
+{
+    /* UART1 TXD */
+    MX6UL_PAD_UART1_TX_DATA__UART1_TX(0x10b0);
+    /* UART1 RXD */
+    MX6UL_PAD_UART1_RX_DATA__UART1_RX(0x10b0);
+}
+
+void uart2_iomux_config(void)
+{
+}
+
+void uart3_iomux_config(void)
+{
+}
+
+void uart4_iomux_config(void)
+{
+}
+
+void uart5_iomux_config(void)
+{
+}
+
+void uart6_iomux_config(void)
+{
+}
+
+void uart7_iomux_config(void)
+{
+}
+
+void uart8_iomux_config(void)
+{
+}
+
+
+void uart_iomux_config(int instance)
+{
+    switch (instance)
+    {
+        case HW_UART1:
+            return uart1_iomux_config();
+
+        case HW_UART2:
+            return uart2_iomux_config();
+
+        case HW_UART3:
+            return uart3_iomux_config();
+
+        case HW_UART4:
+            return uart4_iomux_config();
+
+        case HW_UART5:
+            return uart5_iomux_config();
+
+        case HW_UART6:
+            return uart5_iomux_config();
+
+        case HW_UART7:
+            return uart5_iomux_config();       
+
+        case HW_UART8:
+            return uart5_iomux_config(); 
+                             
+        default:
+            assert(false);
+    }
+}
+

bsp/imx6ul/drivers/serial.c

+/*
+ *  serial.c UART driver
+ *
+ * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  This file is part of RT-Thread (http://www.rt-thread.org)
+ *  Maintainer: bernard.xiong <bernard.xiong at gmail.com>
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-03-30     Bernard      the first verion
+ */
+
+#include <rthw.h>
+#include <registers/regsuart.h>
+#include <imx_uart.h>
+
+#include <rtdevice.h>
+
+#include "serial.h"
+
+struct hw_uart_device
+{
+    uint32_t instance;
+    int irqno;
+};
+
+static void rt_hw_uart_isr(int irqno, void *param)
+{
+    struct rt_serial_device *serial = (struct rt_serial_device *)param;
+
+    rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+}
+
+static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct hw_uart_device *uart;
+    uint32_t baudrate;
+    uint8_t parity, stopbits, datasize, flowcontrol;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    baudrate = cfg->baud_rate;
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_8:
+        datasize = EIGHTBITS;
+        break;
+    case DATA_BITS_7:
+        datasize = SEVENBITS;
+        break;
+    }
+    if (cfg->stop_bits == STOP_BITS_1) stopbits = STOPBITS_ONE;
+    else if (cfg->stop_bits == STOP_BITS_2) stopbits = STOPBITS_TWO;
+
+    parity = PARITY_NONE;
+    flowcontrol = FLOWCTRL_OFF;
+
+    /* Initialize UART */
+    uart_init(uart->instance, baudrate, parity, stopbits, datasize, flowcontrol);
+
+    rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, serial, "uart");
+    rt_hw_interrupt_mask(uart->irqno);
+
+    /* Set the IRQ mode for the Rx FIFO */
+    uart_set_FIFO_mode(uart->instance, RX_FIFO, 1, IRQ_MODE);
+
+    return RT_EOK;
+}
+
+static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        rt_hw_interrupt_mask(uart->irqno);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        rt_hw_interrupt_umask(uart->irqno);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    uart_putchar(uart->instance, (uint8_t*)&c);
+
+    return 1;
+}
+
+static int uart_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    ch = uart_getchar(uart->instance);
+    if (ch == NONE_CHAR) ch = -1;
+
+    return ch;
+}
+
+static const struct rt_uart_ops _uart_ops =
+{
+    uart_configure,
+    uart_control,
+    uart_putc,
+    uart_getc,
+};
+
+#ifdef RT_USING_UART0
+/* UART device driver structure */
+static struct hw_uart_device _uart0_device =
+{
+    HW_UART0,
+    IMX_INT_UART0
+};
+static struct rt_serial_device _serial0;
+#endif
+
+#ifdef RT_USING_UART1
+/* UART1 device driver structure */
+static struct hw_uart_device _uart1_device =
+{
+    HW_UART1,
+    IMX_INT_UART1
+};
+static struct rt_serial_device _serial1;
+#endif
+
+int rt_hw_uart_init(void)
+{
+    struct hw_uart_device *uart;
+    struct serial_configure config;
+
+    config.baud_rate = BAUD_RATE_115200;
+    config.bit_order = BIT_ORDER_LSB;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+    config.invert    = NRZ_NORMAL;
+    config.bufsz     = RT_SERIAL_RB_BUFSZ;
+
+#ifdef RT_USING_UART0
+    uart = &_uart0_device;
+
+    _serial0.ops    = &_uart_ops;
+    _serial0.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&_serial0, "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif
+
+#ifdef RT_USING_UART1
+    uart = &_uart1_device;
+    _serial1.ops = &_uart_ops;
+    _serial1.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&_serial1, "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart);
+#endif
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_uart_init);

bsp/imx6ul/drivers/serial.h

+/*
+ *  UART driver
+ *
+ * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  This file is part of RT-Thread (http://www.rt-thread.org)
+ *  Maintainer: bernard.xiong <bernard.xiong at gmail.com>
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-03-30     Bernard      the first verion
+ */
+
+#ifndef __UART_H__
+#define __UART_H__
+
+#include <board.h>
+
+int rt_hw_uart_init(void);
+
+#endif
+
+

bsp/imx6ul/imx6.lds

+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+
+SECTIONS
+{
+    . = 0x80100000;
+
+    __text_start = .;
+    .text :
+    {
+        *(.vectors)
+        *(.text)
+        *(.text.*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+    } =0
+    __text_end = .;
+
+    __rodata_start = .;
+    .rodata   : { *(.rodata) *(.rodata.*) }
+    __rodata_end = .;
+
+    . = ALIGN(4);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+    }
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    }
+
+    . = ALIGN(16 * 1024);
+    .l1_page_table :
+    {
+        __l1_page_table_start = .;
+        . += 16K;
+    }
+
+    __data_start = .;
+    . = ALIGN(4);
+    .data :
+    {
+        *(.data)
+        *(.data.*)
+    }
+    __data_end = .;
+
+    . = ALIGN(4);
+    __bss_start = __data_end;
+    .bss       :
+    {
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    }
+    . = ALIGN(4);
+    __bss_end = .;
+
+    /* Stabs debugging sections.  */
+    .stab 0 : { *(.stab) }
+    .stabstr 0 : { *(.stabstr) }
+    .stab.excl 0 : { *(.stab.excl) }
+    .stab.exclstr 0 : { *(.stab.exclstr) }
+    .stab.index 0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment 0 : { *(.comment) }
+
+    _end = .;
+}

bsp/imx6ul/platform/SConscript

+from building import *
+
+cwd = GetCurrentDir()
+src = Split('''
+drivers/epit.c
+drivers/gpt.c
+drivers/imx_timer.c
+drivers/imx_i2c.c
+drivers/imx_uart.c
+cpu/armv7_cache.c
+cpu/gic.c
+cpu/ccm_pll2.c
+cpu/mmu.c
+cpu/cortex_a_gcc.S
+''')
+
+CPPPATH = [ cwd + '/cpu',
+cwd + '/include', 
+cwd + '/include/mx6ul',
+cwd + '/include/mx6ul/registers'
+]
+CPPDEFINES = ['CHIP_MX6UL']
+
+group = DefineGroup('Platform', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/imx6ul/platform/cpu/arm_cp_registers.h

+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+//! @addtogroup cortexa9
+//! @{
+
+/*!
+ * @file  arm_cp_registers.h
+ * @brief Definitions for ARM coprocessor registers.
+ */
+
+#ifndef __ARM_CP_REGISTERS_H__
+#define __ARM_CP_REGISTERS_H__
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @name ACTLR
+//@{
+#define BM_ACTLR_SMP (1 << 6)
+//@}
+
+//! @name DFSR
+//@{
+#define BM_DFSR_WNR (1 << 11)   //!< Write not Read bit. 0=read, 1=write.
+#define BM_DFSR_FS4 (0x400)      //!< Fault status bit 4..
+#define BP_DFSR_FS4 (10)        //!< Bit position for FS[4].
+#define BM_DFSR_FS (0xf)      //!< Fault status bits [3:0].
+//@}
+
+//! @name SCTLR
+//@{
+#define BM_SCTLR_TE (1 << 30)  //!< Thumb exception enable.
+#define BM_SCTLR_AFE (1 << 29) //!< Access flag enable.
+#define BM_SCTLR_TRE (1 << 28) //!< TEX remap enable.
+#define BM_SCTLR_NMFI (1 << 27)    //!< Non-maskable FIQ support.
+#define BM_SCTLR_EE (1 << 25)  //!< Exception endianess.
+#define BM_SCTLR_VE (1 << 24)  //!< Interrupt vectors enable.
+#define BM_SCTLR_FI (1 << 21)   //!< Fast interrupt configurable enable.
+#define BM_SCTLR_RR (1 << 14)  //!< Round Robin
+#define BM_SCTLR_V (1 << 13)   //!< Vectors
+#define BM_SCTLR_I (1 << 12)   //!< Instruction cache enable
+#define BM_SCTLR_Z (1 << 11)   //!< Branch prediction enable
+#define BM_SCTLR_SW (1 << 10)  //!< SWP and SWPB enable
+#define BM_SCTLR_CP15BEN (1 << 5)  //!< CP15 barrier enable
+#define BM_SCTLR_C (1 << 2)    //!< Data cache enable
+#define BM_SCTLR_A (1 << 1)    //!< Alignment check enable
+#define BM_SCTLR_M (1 << 0)    //!< MMU enable
+//@}
+
+//! @}
+
+#endif // __ARM_CP_REGISTERS_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////
+

bsp/imx6ul/platform/cpu/armv7_cache.c

+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "cortex_a.h"
+#include "arm_cp_registers.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Check if dcache is enabled or disabled
+int arm_dcache_state_query()
+{
+    uint32_t sctlr; // System Control Register 
+    
+    // read sctlr 
+    _ARM_MRC(15, 0, sctlr, 1, 0, 0);
+        
+    if (sctlr & BM_SCTLR_C)
+    {
+        return 1;
+    }
+
+    return 0;
+}
+
+void arm_dcache_enable()
+{
+    uint32_t sctlr; // System Control Register 
+    
+    // read sctlr 
+    _ARM_MRC(15, 0, sctlr, 1, 0, 0);
+        
+    if (!(sctlr & BM_SCTLR_C))
+    {
+        // set  C bit (data caching enable) 
+        sctlr |= BM_SCTLR_C;
+        
+        // write modified sctlr
+        _ARM_MCR(15, 0, sctlr, 1, 0, 0);
+        
+        // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
+        _ARM_DSB();
+    }
+}
+
+void arm_dcache_disable()
+{
+    uint32_t sctlr; // System Control Register 
+    
+    // read sctlr 
+    _ARM_MRC(15, 0, sctlr, 1, 0, 0);
+    
+    // set  C bit (data caching enable) 
+    sctlr &= ~BM_SCTLR_C;
+
+    // write modified sctlr
+    _ARM_MCR(15, 0, sctlr, 1, 0, 0);
+    
+    // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
+    _ARM_DSB();
+}
+
+void arm_dcache_invalidate()
+{
+    uint32_t csid;    // Cache Size ID
+    uint32_t wayset;  // wayset parameter 
+    int num_sets; // number of sets  
+    int num_ways; // number of ways
+
+    _ARM_MRC(15, 1, csid, 0, 0, 0);    // Read Cache Size ID 
+    
+    // Fill number of sets  and number of ways from csid register  This walues are decremented by 1
+    num_ways = (csid >> 0x03) & 0x3FFu; //((csid& csid_ASSOCIATIVITY_MASK) >> csid_ASSOCIATIVITY_SHIFT)
+    
+    // Invalidation all lines (all Sets in all ways) 
+    while (num_ways >= 0)
+    {
+        num_sets = (csid >> 0x0D) & 0x7FFFu; //((csid & csid_NUMSETS_MASK) >> csid_NUMSETS_SHIFT)
+        while (num_sets >= 0 )
+        {
+            wayset = (num_sets << 5u) | (num_ways << 30u); //(num_sets << SETWAY_SET_SHIFT) | (num_sets << 3SETWAY_WAY_SHIFT)
+            // invalidate line if we know set and way 
+            _ARM_MCR(15, 0, wayset, 7, 6, 2);
+            num_sets--;
+        }
+        num_ways--;
+    }
+    
+    // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
+    _ARM_DSB();
+}
+
+void arm_dcache_invalidate_line(const void * addr)
+{
+    uint32_t csidr = 0, line_size = 0;
+    uint32_t va;
+    
+    // get the cache line size
+    _ARM_MRC(15, 1, csidr, 0, 0, 0);
+    line_size = 1 << ((csidr & 0x7) + 4);    
+    va = (uint32_t) addr & (~(line_size - 1)); //addr & va_VIRTUAL_ADDRESS_MASK
+
+    // Invalidate data cache line by va to PoC (Point of Coherency). 
+    _ARM_MCR(15, 0, va, 7, 6, 1);
+    
+    // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
+    _ARM_DSB();
+}
+
+void arm_dcache_invalidate_mlines(const void * addr, size_t length)
+{
+    uint32_t va;
+    uint32_t csidr = 0, line_size = 0;
+    
+    // get the cache line size
+    _ARM_MRC(15, 1, csidr, 0, 0, 0);
+    line_size = 1 << ((csidr & 0x7) + 4);
+
+    // align the address with line
+    const void * end_addr = (const void *)((uint32_t)addr + length);
+            
+    do
+    {
+        // Clean data cache line to PoC (Point of Coherence) by va. 
+        va = (uint32_t) ((uint32_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK
+        _ARM_MCR(15, 0, va, 7, 6, 1);
+        // increment addres to next line and decrement lenght 
+        addr = (const void *) ((uint32_t)addr + line_size);
+    } while (addr < end_addr);
+    
+    // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
+    _ARM_DSB();
+}
+
+void arm_dcache_flush()
+{
+    uint32_t csid;    // Cache Size ID
+    uint32_t wayset;  // wayset parameter 
+    int num_sets; // number of sets  
+    int num_ways; // number of ways
+
+    _ARM_MRC(15, 1, csid, 0, 0, 0);    // Read Cache Size ID 
+    
+    // Fill number of sets  and number of ways from csid register  This walues are decremented by 1
+    num_ways = (csid >> 0x03) & 0x3FFu; //((csid& csid_ASSOCIATIVITY_MASK) >> csid_ASSOCIATIVITY_SHIFT`)
+    while (num_ways >= 0)
+    {
+        num_sets = (csid >> 0x0D) & 0x7FFFu; //((csid & csid_NUMSETS_MASK)      >> csid_NUMSETS_SHIFT       )
+        while (num_sets >= 0 )
+        {
+            wayset = (num_sets << 5u) | (num_ways << 30u); //(num_sets << SETWAY_SET_SHIFT) | (num_ways << 3SETWAY_WAY_SHIFT)
+            // FLUSH (clean) line if we know set and way 
+            _ARM_MCR(15, 0, wayset, 7, 10, 2);
+            num_sets--;
+        }
+        num_ways--;
+    }
+    
+    // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
+    _ARM_DSB();
+}
+
+void arm_dcache_flush_line(const void * addr)
+{
+    uint32_t csidr = 0, line_size = 0;
+    uint32_t va;
+    
+    // get the cache line size
+    _ARM_MRC(15, 1, csidr, 0, 0, 0);
+    line_size = 1 << ((csidr & 0x7) + 4);    
+    va = (uint32_t) addr & (~(line_size - 1)); //addr & va_VIRTUAL_ADDRESS_MASK
+    
+    // Clean data cache line to PoC (Point of Coherence) by va. 
+    _ARM_MCR(15, 0, va, 7, 10, 1);
+    
+    // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
+    _ARM_DSB();
+}
+
+void arm_dcache_flush_mlines(const void * addr, size_t length)
+{
+    uint32_t va;
+    uint32_t csidr = 0, line_size = 0;
+    const void * end_addr = (const void *)((uint32_t)addr + length);
+
+    // get the cache line size
+    _ARM_MRC(15, 1, csidr, 0, 0, 0);
+    line_size = 1 << ((csidr & 0x7) + 4);
+    
+    do
+    {
+        // Clean data cache line to PoC (Point of Coherence) by va. 
+        va = (uint32_t) ((uint32_t)addr & (~(line_size  - 1))); //addr & va_VIRTUAL_ADDRESS_MASK
+        _ARM_MCR(15, 0, va, 7, 10, 1);
+        
+        // increment addres to next line and decrement lenght 
+        addr = (const void *) ((uint32_t)addr + line_size);
+    } while (addr < end_addr);
+    
+    // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
+    _ARM_DSB();
+}
+
+int arm_icache_state_query()
+{
+    uint32_t sctlr; // System Control Register 
+    
+    // read sctlr 
+    _ARM_MRC(15, 0, sctlr, 1, 0, 0);
+        
+    if (sctlr & BM_SCTLR_I)
+    {
+        return 1;
+    }
+
+    return 0;
+}
+
+void arm_icache_enable()
+{
+    uint32_t sctlr  ;// System Control Register 
+    
+    // read sctlr 
+    _ARM_MRC(15, 0, sctlr, 1, 0, 0);
+    
+    // ignore the operation if I is enabled already
+    if(!(sctlr & BM_SCTLR_I))
+    {	
+        // set  I bit (instruction caching enable)
+        sctlr |= BM_SCTLR_I;
+        
+        // write modified sctlr
+        _ARM_MCR(15, 0, sctlr, 1, 0, 0);
+        
+        // synchronize context on this processor 
+        _ARM_ISB();
+    }
+}
+
+void arm_icache_disable()
+{
+    uint32_t sctlr  ;// System Control Register 
+    
+    // read sctlr 
+    _ARM_MRC(15, 0, sctlr, 1, 0, 0);
+    
+    // Clear  I bit (instruction caching enable) 
+    sctlr &= ~BM_SCTLR_I;
+
+    // write modified sctlr
+    _ARM_MCR(15, 0, sctlr, 1, 0, 0);
+    
+    // synchronize context on this processor 
+    _ARM_ISB();
+}
+
+void arm_icache_invalidate()
+{
+    uint32_t SBZ = 0x0u;
+    
+    _ARM_MCR(15, 0, SBZ, 7, 5, 0);
+    
+    // synchronize context on this processor 
+    _ARM_ISB();
+}
+
+void arm_icache_invalidate_is()
+{
+    uint32_t SBZ = 0x0u;
+    
+    _ARM_MCR(15, 0, SBZ, 7, 1, 0);
+    
+    // synchronize context on this processor 
+    _ARM_ISB();
+}
+
+void arm_icache_invalidate_line(const void * addr)
+{
+    uint32_t csidr = 0, line_size = 0;
+    uint32_t va;
+    
+    // get the cache line size
+    _ARM_MRC(15, 1, csidr, 0, 0, 0);
+    line_size = 1 << ((csidr & 0x7) + 4);    
+    va = (uint32_t) addr & (~(line_size - 1)); //addr & va_VIRTUAL_ADDRESS_MASK
+    
+    // Invalidate instruction cache by va to PoU (Point of unification). 
+    _ARM_MCR(15, 0, va, 7, 5, 1);
+    
+    // synchronize context on this processor 
+    _ARM_ISB();
+}
+
+void arm_icache_invalidate_mlines(const void * addr, size_t length)
+{
+    uint32_t va;
+    uint32_t csidr = 0, line_size = 0;
+    const void * end_addr = (const void *)((uint32_t)addr + length);
+
+    // get the cache line size
+    _ARM_MRC(15, 1, csidr, 0, 0, 0);
+    line_size = 1 << ((csidr & 0x7) + 4);    
+    
+    do
+    {
+        // Clean data cache line to PoC (Point of Coherence) by va. 
+        va = (uint32_t) ((uint32_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK
+        _ARM_MCR(15, 0, va, 7, 5, 1);
+        // increment addres to next line and decrement lenght 
+        addr = (const void *) ((uint32_t)addr + line_size);
+    } while (addr < end_addr);
+    
+    // synchronize context on this processor 
+    _ARM_ISB();
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/cpu/ccm_pll.h

+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CCM_PLL_H_
+#define _CCM_PLL_H_
+
+#include "sdk_types.h"
+
+//! @addtogroup diag_clocks
+//! @{
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+#define CLK_SRC_32K         32768
+
+//! @brief Create a clock gate bit mask value.
+//! @param x 0..15, for CG0 to CG15
+#define CG(x) (3 << (x*2))
+
+//! @brief Constants for CCM CCGR register fields.
+enum _clock_gate_constants
+{
+    CLOCK_ON = 0x3, //!< Clock always on in both run and stop modes.
+    CLOCK_ON_RUN = 0x1, //!< Clock on only in run mode.
+    CLOCK_OFF = 0x0 //!< Clocked gated off.
+};
+
+//! @brief Low power mdoes.
+typedef enum _lp_modes {
+    RUN_MODE,
+    WAIT_MODE,
+    STOP_MODE,
+} lp_modes_t;
+
+//! @brief Main clock sources.
+typedef enum _main_clocks {
+    CPU_CLK,
+    AXI_CLK,
+    MMDC_CH0_AXI_CLK,
+    AHB_CLK,
+    IPG_CLK,
+    IPG_PER_CLK,
+    MMDC_CH1_AXI_CLK,
+} main_clocks_t;
+
+//! @brief Peripheral clocks.
+typedef enum _peri_clocks {
+    UART1_MODULE_CLK,
+    UART2_MODULE_CLK,
+    UART3_MODULE_CLK,
+    UART4_MODULE_CLK,
+    UART5_MODULE_CLK,
+    UART6_MODULE_CLK,
+    UART7_MODULE_CLK,
+    UART8_MODULE_CLK,
+    SSI1_BAUD,
+    SSI2_BAUD,
+    CSI_BAUD,
+    MSTICK1_CLK,
+    MSTICK2_CLK,
+    RAWNAND_CLK,
+    USB_CLK,
+    VPU_CLK,
+    SPI_CLK,
+    CAN_CLK
+} peri_clocks_t;
+
+//! @brief Available PLLs.
+typedef enum plls {
+    PLL1,
+    PLL2,
+    PLL3,
+    PLL4,
+    PLL5,
+} plls_t;
+
+extern const uint32_t PLL1_OUTPUT;
+extern const uint32_t PLL2_OUTPUT[];
+extern const uint32_t PLL3_OUTPUT[];
+extern const uint32_t PLL4_OUTPUT;
+extern const uint32_t PLL5_OUTPUT;
+
+////////////////////////////////////////////////////////////////////////////////
+// API
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+//! @brief Set/unset clock gating for a peripheral.
+//! @param   base_address configure clock gating for that module from the base address.
+//! @param   gating_mode clock gating mode: CLOCK_ON or CLOCK_OFF.
+void clock_gating_config(uint32_t base_address, uint32_t gating_mode);
+
+//! @brief Returns the frequency of a clock in megahertz.
+uint32_t get_main_clock(main_clocks_t clk);
+
+//! @brief Returns the frequency of a clock in megahertz.
+uint32_t get_peri_clock(peri_clocks_t clk);
+
+//! @brief Inits clock sources.
+void ccm_init(void);
+
+//! @brief Prepare and enter in a low power mode.
+//! @param lp_mode low power mode : WAIT_MODE or STOP_MODE.
+void ccm_enter_low_power(lp_modes_t lp_mode);
+
+//! @brief Mask/unmask an interrupt source that can wake up the processor when in a
+//! low power mode.
+//!
+//! @param   irq_id ID of the interrupt to mask/unmask.
+//! @param   doEnable Pass true to unmask the source ID.
+void ccm_set_lpm_wakeup_source(uint32_t irq_id, bool doEnable);
+
+#if defined(__cplusplus)
+}
+#endif
+
+//! @}
+
+#endif
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/cpu/ccm_pll2.c

+/*
+ * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "sdk.h"
+#include "registers/regsccm.h"
+#include "registers/regsccmanalog.h"
+#include "registers/regsuart.h"
+#include "registers/regsepit.h"
+#include "registers/regsspba.h"
+#include "registers/regssdmaarm.h"
+#include "registers/regsgpt.h"
+#include "registers/regsi2c.h"
+#include "registers/regsecspi.h"
+#include "ccm_pll.h"
+//#include "hardware.h"
+//#include "soc_memory_map.h"
+#define HW_ANADIG_REG_CORE		(ANATOP_IPS_BASE_ADDR + 0x140)
+#define HW_ANADIG_PLL_SYS_RW  (ANATOP_IPS_BASE_ADDR + 0x000)
+#define HW_ANADIG_REG_CORE_V_CORE_VALUE_mv(x)	((((x)-700)/25) << 0)
+#define HW_ANADIG_REG_CORE_V_SOC_VALUE_mv(x)	((((x)-700)/25) << 18)
+#define HW_ANADIG_REG_CORE_V_CORE_MSK		0x1F
+#define HW_ANADIG_REG_CORE_V_SOC_MSK		(0x1F << 18)
+
+uint32_t g_arm_clk = 528000000;
+
+const uint32_t PLL2_OUTPUT[] = { 528000000, 396000000, 352000000, 198000000 };
+const uint32_t PLL3_OUTPUT[] = { 480000000, 720000000, 540000000, 508235294, 454736842 };
+const uint32_t PLL4_OUTPUT = 650000000;
+const uint32_t PLL5_OUTPUT = 650000000;
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+void set_soc_core_voltage(unsigned int v_core_mv, unsigned int v_soc_mv)
+{
+    unsigned int val, val_v_core, val_v_soc;
+
+    val = reg32_read(HW_ANADIG_REG_CORE);
+    val &= ~HW_ANADIG_REG_CORE_V_CORE_MSK;
+    val &= ~HW_ANADIG_REG_CORE_V_SOC_MSK;
+
+    val_v_core = HW_ANADIG_REG_CORE_V_CORE_VALUE_mv(v_core_mv);
+    val_v_soc = HW_ANADIG_REG_CORE_V_SOC_VALUE_mv(v_soc_mv);
+
+    val |= val_v_core | val_v_soc;
+    reg32_write(HW_ANADIG_REG_CORE, val);
+}
+
+void setup_clk(void)
+{
+		uint32_t div_select;
+		uint32_t temp;	
+		uint32_t arm_clk = g_arm_clk/1000000;
+	  
+		switch(arm_clk)
+		{
+			case 400:
+				div_select = 33;
+				set_soc_core_voltage(1150, 1175);
+				return;
+			case 528:
+				div_select = 44;
+				set_soc_core_voltage(1250, 1250);
+				break;
+			case 756:
+				div_select = 63;
+    		set_soc_core_voltage(1250, 1250);
+    		printf("ARM Clock set to 756MHz\r\n");
+    		break;
+			default:
+				return;
+    }      	    			   	    			
+    	
+    // first, make sure ARM_PODF is clear
+    HW_CCM_CACRR_WR(0);
+    // write the div_select value into HW_ANADIG_PLL_SYS_RW
+    // this will re-program the PLL to the new freq
+
+    temp = readl(HW_ANADIG_PLL_SYS_RW);
+    temp |= 0x10000;// set BYBASS 
+    writel(temp, HW_ANADIG_PLL_SYS_RW);
+
+    temp = readl(HW_ANADIG_PLL_SYS_RW);
+    temp &= ~(0x0000007F);
+    temp |= div_select;  // Update div 
+    writel(temp, HW_ANADIG_PLL_SYS_RW);
+
+		/* Wait for PLL to lock */
+		while(!(readl(HW_ANADIG_PLL_SYS_RW) & 0x80000000));
+
+		/*disable BYPASS*/
+    temp = readl(HW_ANADIG_PLL_SYS_RW);
+		temp &= ~0x10000;
+    writel(temp, HW_ANADIG_PLL_SYS_RW);		
+}
+
+void ccm_init(void)
+{
+    HW_CCM_CCGR0_WR(0xffffffff);
+    HW_CCM_CCGR1_WR(0xffffffff);    // EPIT, ESAI, GPT enabled by driver
+    HW_CCM_CCGR2_WR(0xffffffff);    // I2C enabled by driver
+    HW_CCM_CCGR3_WR(0xffffffff);
+    HW_CCM_CCGR4_WR(0xffffffff);    // GPMI, Perfmon enabled by driver
+    HW_CCM_CCGR5_WR(0xffffffff);    // UART, SATA enabled by driver
+    HW_CCM_CCGR6_WR(0xffffffff);
+
+    /*
+     * Keep default settings at reset.
+     * pre_periph_clk_sel is by default at 0, so the selected output
+     * of PLL2 is the main output at 528MHz.
+     * => by default, ahb_podf divides by 4 => AHB_CLK@132MHz.
+     * => by default, ipg_podf divides by 2 => IPG_CLK@66MHz.
+     */    
+    HW_CCM_CBCDR.U = BF_CCM_CBCDR_AHB_PODF(3)
+        | BF_CCM_CBCDR_AXI_PODF(1)
+        | BF_CCM_CBCDR_IPG_PODF(1);
+    
+    setup_clk();
+
+    /* Power up 480MHz PLL */
+    reg32_write_mask(HW_CCM_ANALOG_PLL_USB1_ADDR, 0x00001000, 0x00001000);
+
+    /* Enable 480MHz PLL */
+    reg32_write_mask(HW_CCM_ANALOG_PLL_USB1_ADDR, 0x00002000, 0x00002000);
+    
+    reg32_write_mask(HW_CCM_CSCDR1_ADDR, 0x00000000, 0x0000003F);
+}
+
+uint32_t get_main_clock(main_clocks_t clock)
+{
+    uint32_t ret_val = 0;
+    uint32_t pre_periph_clk_sel = HW_CCM_CBCMR.B.PRE_PERIPH_CLK_SEL;
+
+    switch (clock) {
+    case CPU_CLK:
+        ret_val = g_arm_clk;
+        break;
+    case AXI_CLK:
+        ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AXI_PODF + 1);
+        break;
+    case MMDC_CH0_AXI_CLK:
+        ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.MMDC_CH0_AXI_PODF + 1);
+        break;
+    case AHB_CLK:
+        ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AHB_PODF + 1);
+        break;
+    case IPG_CLK:
+        ret_val =
+            PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AHB_PODF +
+                                               1) / (HW_CCM_CBCDR.B.IPG_PODF + 1);
+        break;
+    case IPG_PER_CLK:
+        ret_val =
+            PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AHB_PODF +
+                                               1) / (HW_CCM_CBCDR.B.IPG_PODF +
+                                                     1) / (HW_CCM_CSCMR1.B.PERCLK_PODF + 1);
+        break;
+    default:
+        break;
+    }
+
+    return ret_val;
+}
+
+uint32_t get_peri_clock(peri_clocks_t clock)
+{
+    uint32_t ret_val = 0;
+
+    switch (clock)
+    {
+        case UART1_MODULE_CLK:
+        case UART2_MODULE_CLK:
+        case UART3_MODULE_CLK:
+        case UART4_MODULE_CLK:
+       	case UART5_MODULE_CLK:
+     		case UART6_MODULE_CLK:
+   			case UART7_MODULE_CLK:
+   			case UART8_MODULE_CLK:   				
+            // UART source clock is a fixed PLL3 / 6
+            ret_val = PLL3_OUTPUT[0] / 6 / (HW_CCM_CSCDR1.B.UART_CLK_PODF + 1);
+            break;
+        case SPI_CLK:
+            ret_val = PLL3_OUTPUT[0] / 8 / (HW_CCM_CSCDR2.B.ECSPI_CLK_PODF + 1);
+            break;
+        case RAWNAND_CLK:
+            ret_val =
+                PLL3_OUTPUT[0] / (HW_CCM_CS2CDR.B.ENFC_CLK_PRED + 1) / (HW_CCM_CS2CDR.B.ENFC_CLK_PODF +
+                                                                        1);
+            break;
+        case CAN_CLK:
+            // For i.mx6dq/sdl CAN source clock is a fixed PLL3 / 8
+        	ret_val = PLL3_OUTPUT[0] / 8 / (HW_CCM_CSCMR2.B.CAN_CLK_PODF + 1);
+        	break;
+        default:
+            break;
+    }
+
+    return ret_val;
+}
+
+void ccm_ccgr_config(uint32_t ccm_ccgrx, uint32_t cgx_offset, uint32_t gating_mode)
+{
+    if (gating_mode == CLOCK_ON)
+    {
+        *(volatile uint32_t *)(ccm_ccgrx) |= cgx_offset;
+    }
+    else
+    {
+        *(volatile uint32_t *)(ccm_ccgrx) &= ~cgx_offset;
+    }
+}
+
+void clock_gating_config(uint32_t base_address, uint32_t gating_mode)
+{
+    uint32_t ccm_ccgrx = 0;
+    uint32_t cgx_offset = 0;
+
+    switch (base_address)
+    {
+        case REGS_UART1_BASE:
+            ccm_ccgrx = HW_CCM_CCGR5_ADDR;
+            cgx_offset = CG(12);
+            break;         	
+        case REGS_UART2_BASE:
+            ccm_ccgrx = HW_CCM_CCGR0_ADDR;
+            cgx_offset = CG(14);
+            break;        	
+        case REGS_UART3_BASE:
+            ccm_ccgrx = HW_CCM_CCGR1_ADDR;
+            cgx_offset = CG(5);
+            break;           	
+        case REGS_UART4_BASE:
+            ccm_ccgrx = HW_CCM_CCGR1_ADDR;
+            cgx_offset = CG(12);
+            break;         	
+        case REGS_UART5_BASE:
+            ccm_ccgrx = HW_CCM_CCGR3_ADDR;
+            cgx_offset = CG(1);
+            break;         	
+        case REGS_UART6_BASE:
+            ccm_ccgrx = HW_CCM_CCGR3_ADDR;
+            cgx_offset = CG(3);
+            break;          	
+        case REGS_UART7_BASE:
+            ccm_ccgrx = HW_CCM_CCGR5_ADDR;
+            cgx_offset = CG(13);
+            break;          	
+        case REGS_UART8_BASE:
+            ccm_ccgrx = HW_CCM_CCGR6_ADDR;
+            cgx_offset = CG(7);
+            break;
+        case REGS_SPBA_BASE:
+            ccm_ccgrx = HW_CCM_CCGR5_ADDR;
+            cgx_offset = CG(6);
+            break;
+        case REGS_SDMAARM_BASE:
+            ccm_ccgrx = HW_CCM_CCGR5_ADDR;
+            cgx_offset = CG(3);
+            break;
+        case REGS_EPIT1_BASE:
+            ccm_ccgrx = HW_CCM_CCGR1_ADDR;
+            cgx_offset = CG(6);
+            break;
+        case REGS_EPIT2_BASE:
+            ccm_ccgrx = HW_CCM_CCGR1_ADDR;
+            cgx_offset = CG(7);
+            break;
+        case REGS_GPT1_BASE:
+        case REGS_GPT2_BASE:
+            ccm_ccgrx = HW_CCM_CCGR1_ADDR;
+            cgx_offset = CG(10)|CG(11);
+            break;            
+        case REGS_I2C1_BASE:
+            ccm_ccgrx = HW_CCM_CCGR2_ADDR;
+            cgx_offset = CG(3);
+            break;
+        case REGS_I2C2_BASE:
+            ccm_ccgrx = HW_CCM_CCGR2_ADDR;
+            cgx_offset = CG(4);
+            break;
+        case REGS_I2C3_BASE:
+            ccm_ccgrx = HW_CCM_CCGR2_ADDR;
+            cgx_offset = CG(5);
+            break;
+        case REGS_ECSPI1_BASE:
+            ccm_ccgrx = HW_CCM_CCGR1_ADDR;
+            cgx_offset = CG(0);
+            break;        
+        case REGS_ECSPI2_BASE:
+            ccm_ccgrx = HW_CCM_CCGR1_ADDR;
+            cgx_offset = CG(1);
+            break;        
+        case REGS_ECSPI3_BASE:
+            ccm_ccgrx = HW_CCM_CCGR1_ADDR;
+            cgx_offset = CG(2);
+            break;        
+        case REGS_ECSPI4_BASE:
+            ccm_ccgrx = HW_CCM_CCGR1_ADDR;
+            cgx_offset = CG(3);
+            break;        
+        default:
+            break;
+    }
+
+    // apply changes only if a valid address was found 
+    if (ccm_ccgrx != 0)
+    {
+        ccm_ccgr_config(ccm_ccgrx, cgx_offset, gating_mode);
+    }
+}
+////////////////////////////////////////////////////////////////////////////////
+// End of file
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/cpu/cortex_a.h

+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__CORTEX_A_H__)
+#define __CORTEX_A9H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+
+//! @addtogroup cortexa9
+//! @{
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @name Instruction macros
+//@{
+#define _ARM_NOP()  asm volatile ("nop\n\t")
+#define _ARM_WFI()  asm volatile ("wfi\n\t")
+#define _ARM_WFE()  asm volatile ("wfe\n\t")
+#define _ARM_SEV()  asm volatile ("sev\n\t")
+#define _ARM_DSB()  asm volatile ("dsb\n\t")
+#define _ARM_ISB()  asm volatile ("isb\n\t")
+
+#define _ARM_MRC(coproc, opcode1, Rt, CRn, CRm, opcode2)	\
+    asm volatile ("mrc p" #coproc ", " #opcode1 ", %[output], c" #CRn ", c" #CRm ", " #opcode2 "\n" : [output] "=r" (Rt))
+    
+#define _ARM_MCR(coproc, opcode1, Rt, CRn, CRm, opcode2)	\
+    asm volatile ("mcr p" #coproc ", " #opcode1 ", %[input], c" #CRn ", c" #CRm ", " #opcode2 "\n" :: [input] "r" (Rt))
+//@}
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+//! @name Misc
+//@{
+//! @brief Enable or disable the IRQ and FIQ state.
+bool arm_set_interrupt_state(bool enable);
+
+//! @brief Get current CPU ID.
+int cpu_get_current(void);
+
+//! @brief Enable the NEON MPE.
+void enable_neon_fpu(void);
+
+//! @brief Disable aborts on unaligned accesses.
+void disable_strict_align_check(void);
+
+//! @brief Get base address of private perpherial space.
+//!
+//! @return The address of the ARM CPU's private peripherals.
+uint32_t get_arm_private_peripheral_base(void);
+//@}
+
+//! @name Data cache operations
+//@{
+
+//! @brief Check if dcache is enabled or disabled.
+int arm_dcache_state_query();
+
+//! @brief Enables data cache at any available cache level.
+//!
+//! Works only if MMU is enabled!
+void arm_dcache_enable();
+
+//! @brief Disables the data cache at any available cache level.
+void arm_dcache_disable();
+
+//! @brief Invalidates the entire data cache.
+void arm_dcache_invalidate();
+
+//! @brief Invalidate a line of data cache.
+void arm_dcache_invalidate_line(const void * addr);
+
+//! @brief Invalidate a number of lines of data cache.
+//!
+//! Number of lines depends on length parameter and size of line.
+//! Size of line for A9 L1 cache is 32B.
+void arm_dcache_invalidate_mlines(const void * addr, size_t length);
+
+//! @brief Flush (clean) all lines of cache (all sets in all ways).
+void arm_dcache_flush();
+
+//! @brief Flush (clean) one line of cache.
+void arm_dcache_flush_line(const void * addr);
+
+// @brief Flush (clean) multiple lines of cache.
+//!
+//! Number of lines depends on length parameter and size of line.
+void arm_dcache_flush_mlines(const void * addr, size_t length);
+//@}
+
+//! @name Instrution cache operations
+//@{
+
+//! @brief Check if icache is enabled or disabled.
+int arm_icache_state_query();
+
+//! @brief Enables instruction cache at any available cache level.
+//!
+//! Works without enabled MMU too!
+void arm_icache_enable();
+
+//! @brief Disables the instruction cache at any available cache level.
+void arm_icache_disable();
+
+//! @brief Invalidates the entire instruction cache.
+void arm_icache_invalidate();
+
+//! @brief Invalidates the entire instruction cache inner shareable.
+void arm_icache_invalidate_is();
+
+//! @brief Invalidate a line of the instruction cache.
+void arm_icache_invalidate_line(const void * addr);
+
+//! @brief Invalidate a number of lines of instruction cache.
+//!
+//! Number of lines depends on length parameter and size of line.
+void arm_icache_invalidate_mlines(const void * addr, size_t length);
+//@}
+
+//! @name TLB operations
+//@{
+//! @brief Invalidate entire unified TLB.
+void arm_unified_tlb_invalidate(void);
+
+//! @brief Invalidate entire unified TLB Inner Shareable.
+void arm_unified_tlb_invalidate_is(void);
+//@}
+
+//! @name Branch predictor operations
+//@{
+//! @brief Enable branch prediction.
+void arm_branch_prediction_enable(void);
+
+//! @brief Disable branch prediction.
+void arm_branch_prediction_disable(void);
+
+//! @brief Invalidate entire branch predictor array.
+void arm_branch_target_cache_invalidate(void);
+
+//! @brief Invalidate entire branch predictor array Inner Shareable
+void arm_branch_target_cache_invalidate_is(void);
+//@}
+
+//! @name SCU
+//@{
+//! @brief Enables the SCU.
+void scu_enable(void);
+
+//! @brief Set this CPU as participating in SMP.
+void scu_join_smp(void);
+
+//! @brief Set this CPU as not participating in SMP.
+void scu_leave_smp(void);
+
+//! @brief Determine which CPUs are participating in SMP.
+//!
+//! The return value is 1 bit per core:
+//! - bit 0 - CPU 0
+//! - bit 1 - CPU 1
+//! - etc...
+unsigned int scu_get_cpus_in_smp(void);
+
+//! @brief Enable the broadcasting of cache & TLB maintenance operations.
+//!
+//! When enabled AND in SMP, broadcast all "inner sharable"
+//! cache and TLM maintenance operations to other SMP cores
+void scu_enable_maintenance_broadcast(void);
+
+//! @brief Disable the broadcasting of cache & TLB maintenance operations.
+void scu_disable_maintenance_broadcast(void);
+
+//! @brief Invalidates the SCU copy of the tag rams for the specified core.
+//!
+//! Typically only done at start-up.
+//! Possible flow:
+//! - Invalidate L1 caches
+//! - Invalidate SCU copy of TAG RAMs
+//! - Join SMP
+//!
+//! @param cpu 0x0=CPU 0, 0x1=CPU 1, etc...
+//! @param ways The ways to invalidate. Pass 0xf to invalidate all ways.
+void scu_secure_invalidate(unsigned int cpu, unsigned int ways);
+//@}
+
+#if defined(__cplusplus)
+}
+#endif
+
+//! @}
+
+#endif // __CORTEX_A_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/cpu/cortex_a_gcc.S

+/*
+ * Copyright (c) 2010-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * @file cortexA9.s
+ * @brief This file contains cortexA9 functions
+ *
+ */
+ 
+    .code 32
+    .section ".text","ax"
+
+/*
+ * bool arm_set_interrupt_state(bool enable)
+ */
+    .global arm_set_interrupt_state
+    .func arm_set_interrupt_state
+arm_set_interrupt_state:
+    mrs             r2,CPSR            @ read CPSR (Current Program Status Register)
+    teq     r0,#0
+    bicne   r1,r2,#0xc0        @ disable IRQ and FIQ
+    orreq   r1,r2,#0xc0        @ enable IRQ and FIQ
+    msr     CPSR_c,r1
+    tst     r2,#0x80
+    movne   r0,#0
+    moveq   r0,#1
+    bx      lr
+    .endfunc
+
+  .global cpu_get_current
+  @ int cpu_get_current(void)@
+  @ get current CPU ID
+  .func cpu_get_current
+cpu_get_current: 
+    mrc   p15, 0, r0, c0, c0, 5
+    and   r0, r0, #3
+	BX	  lr
+  .endfunc    @cpu_get_current()@
+
+  .global enable_neon_fpu
+  .func enable_neon_fpu
+enable_neon_fpu:
+	/* set NSACR, both Secure and Non-secure access are allowed to NEON */
+	MRC p15, 0, r0, c1, c1, 2
+	ORR r0, r0, #(0x3<<10) @ enable fpu/neon
+	MCR p15, 0, r0, c1, c1, 2
+	/* Set the CPACR for access to CP10 and CP11*/
+	LDR r0, =0xF00000
+	MCR p15, 0, r0, c1, c0, 2
+	/* Set the FPEXC EN bit to enable the FPU */
+	MOV r3, #0x40000000 
+	@VMSR FPEXC, r3
+	MCR p10, 7, r3, c8, c0, 0
+  .endfunc
+
+  .global disable_strict_align_check
+  .func disable_strict_align_check
+disable_strict_align_check:
+  	/*Ray's note: disable strict alignment fault checking.
+ 	without disabling this, data abort will happen when accessing
+	the BPB structure of file system since it is packed.*/
+    
+  	push	{r0, lr}
+	
+	mrc p15, 0, r0, c1, c0, 0
+	bic r0, r0, #(0x1<<1) @clear A bit of SCTLR 
+	mcr p15, 0, r0, c1, c0, 0
+
+    pop {r0, pc}
+  .endfunc
+
+  .global disable_L1_cache
+  .func disable_L1_cache
+disable_L1_cache:
+    push	{r0-r6, lr}
+
+	mrc p15, 0, r0, c1, c0, 0
+	bic r0, r0, #(0x1<<12) 
+	bic r0, r0, #(0x1<<11) 
+	bic r0, r0, #(0x1<<2) 
+	bic r0, r0, #(0x1<<0) 
+	mcr p15, 0, r0, c1, c0, 0
+
+    pop {r0-r6, pc}
+
+  .endfunc
+
+  .global get_arm_private_peripheral_base
+  @ uint32_t get_arm_private_peripheral_base(void)@
+  .func get_arm_private_peripheral_base
+get_arm_private_peripheral_base: 
+
+  @ Get base address of private perpherial space
+  mrc     p15, 4, r0, c15, c0, 0  @ Read periph base address
+  bx      lr
+  
+  .endfunc    @get_arm_private_peripheral_base()@
+
+@ ------------------------------------------------------------
+@ TLB
+@ ------------------------------------------------------------
+
+  .global arm_unified_tlb_invalidate
+  @ void arm_unified_tlb_invalidate(void)@
+  .func arm_unified_tlb_invalidate
+arm_unified_tlb_invalidate:
+  mov     r0, #1
+  mcr     p15, 0, r0, c8, c7, 0                 @ TLBIALL - Invalidate entire unified TLB
+  dsb
+  bx      lr
+  .endfunc
+
+  .global arm_unified_tlb_invalidate_is
+  @ void arm_unified_tlb_invalidate_is(void)@
+  .func arm_unified_tlb_invalidate_is
+arm_unified_tlb_invalidate_is:
+  mov     r0, #1
+  mcr     p15, 0, r0, c8, c3, 0                 @ TLBIALLIS - Invalidate entire unified TLB Inner Shareable
+  dsb
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+@ Branch Prediction
+@ ------------------------------------------------------------
+
+  .global arm_branch_prediction_enable
+  @ void arm_branch_prediction_enable(void)
+  .func arm_branch_prediction_enable
+arm_branch_prediction_enable:
+  mrc     p15, 0, r0, c1, c0, 0                 @ Read SCTLR
+  orr     r0, r0, #(1 << 11)                    @ Set the Z bit (bit 11)
+  mcr     p15, 0,r0, c1, c0, 0                  @ Write SCTLR
+  bx      lr
+  .endfunc
+
+  .global arm_branch_prediction_disable
+  @ void arm_branch_prediction_disable(void)
+  .func arm_branch_prediction_disable
+arm_branch_prediction_disable:
+  mrc     p15, 0, r0, c1, c0, 0                 @ Read SCTLR
+  bic     r0, r0, #(1 << 11)                    @ Clear the Z bit (bit 11)
+  mcr     p15, 0,r0, c1, c0, 0                  @ Write SCTLR
+  bx      lr
+  .endfunc
+  
+  .global arm_branch_target_cache_invalidate
+  @ void arm_branch_target_cache_invalidate(void)
+  .func arm_branch_target_cache_invalidate
+arm_branch_target_cache_invalidate:
+  mov     r0, #0
+  mcr     p15, 0, r0, c7, c5, 6                 @ BPIALL - Invalidate entire branch predictor array
+  bx      lr
+  .endfunc
+
+  .global arm_branch_target_cache_invalidate_is
+  @ void arm_branch_target_cache_invalidate_is(void)
+  .func arm_branch_target_cache_invalidate_is
+arm_branch_target_cache_invalidate_is:
+  mov     r0, #0
+  mcr     p15, 0, r0, c7, c1, 6                 @ BPIALLIS - Invalidate entire branch predictor array Inner Shareable
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+@ SCU
+@ ------------------------------------------------------------
+
+  @ SCU offset from base of private peripheral space --> 0x000
+
+  .global scu_enable
+  @ void scu_enable(void)
+  @ Enables the SCU
+  .func scu_enable
+scu_enable:
+
+  mrc     p15, 4, r0, c15, c0, 0  @ Read periph base address
+
+  ldr     r1, [r0, #0x0]          @ Read the SCU Control Register
+  orr     r1, r1, #0x1            @ Set bit 0 (The Enable bit)
+  str     r1, [r0, #0x0]          @ Write back modifed value
+
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+
+  .global  scu_join_smp
+  @ void scu_join_smp(void)
+  @ Set this CPU as participating in SMP
+  .func scu_join_smp
+scu_join_smp:
+
+  @ SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg
+
+  mrc     p15, 0, r0, c1, c0, 1   @ Read ACTLR
+  orr     r0, r0, #0x040          @ Set bit 6
+  mcr     p15, 0, r0, c1, c0, 1   @ Write ACTLR
+
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+
+  .global scu_leave_smp
+  @ void scu_leave_smp(void)
+  @ Set this CPU as NOT participating in SMP
+  .func scu_leave_smp
+scu_leave_smp:
+
+  @ SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg
+
+  mrc     p15, 0, r0, c1, c0, 1   @ Read ACTLR
+  bic     r0, r0, #0x040          @ Clear bit 6
+  mcr     p15, 0, r0, c1, c0, 1   @ Write ACTLR
+
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+
+  .global scu_get_cpus_in_smp
+  @ unsigned int scu_get_cpus_in_smp(void)
+  @ The return value is 1 bit per core:
+  @ bit 0 - CPU 0
+  @ bit 1 - CPU 1
+  @ etc...
+  .func scu_get_cpus_in_smp
+scu_get_cpus_in_smp:
+
+  mrc     p15, 4, r0, c15, c0, 0  @ Read periph base address
+
+  ldr     r0, [r0, #0x004]        @ Read SCU Configuration register
+  mov     r0, r0, lsr #4          @ Bits 7:4 gives the cores in SMP mode, shift then mask
+  and     r0, r0, #0x0F
+
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+
+  .global scu_enable_maintenance_broadcast
+  @ void scu_enable_maintenance_broadcast(void)
+  @ Enable the broadcasting of cache & TLB maintenance operations
+  @ When enabled AND in SMP, broadcast all "inner sharable"
+  @ cache and TLM maintenance operations to other SMP cores
+  .func scu_enable_maintenance_broadcast
+scu_enable_maintenance_broadcast:
+  mrc     p15, 0, r0, c1, c0, 1   @ Read Aux Ctrl register
+  orr     r0, r0, #0x01           @ Set the FW bit (bit 0)
+  mcr     p15, 0, r0, c1, c0, 1   @ Write Aux Ctrl register
+
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+
+  .global scu_disable_maintenance_broadcast
+  @ void scu_disable_maintenance_broadcast(void)
+  @ Disable the broadcasting of cache & TLB maintenance operations
+  .func scu_disable_maintenance_broadcast
+scu_disable_maintenance_broadcast:
+  mrc     p15, 0, r0, c1, c0, 1   @ Read Aux Ctrl register
+  bic     r0, r0, #0x01           @ Clear the FW bit (bit 0)
+  mcr     p15, 0, r0, c1, c0, 1   @ Write Aux Ctrl register
+
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+
+  .global scu_secure_invalidate
+  @ void scu_secure_invalidate(unsigned int cpu, unsigned int ways)
+  @ cpu: 0x0=CPU 0 0x1=CPU 1 etc...
+  @ This function invalidates the SCU copy of the tag rams
+  @ for the specified core.  typically only done at start-up.
+  @ Possible flow:
+  @ - Invalidate L1 caches
+  @ - Invalidate SCU copy of TAG RAMs
+  @ - Join SMP
+  .func scu_secure_invalidate
+scu_secure_invalidate:
+  and     r0, r0, #0x03           @ Mask off unused bits of CPU ID
+  mov     r0, r0, lsl #2          @ Convert into bit offset (four bits per core)
+  
+  and     r1, r1, #0x0F           @ Mask off unused bits of ways
+  mov     r1, r1, lsl r0          @ Shift ways into the correct CPU field
+
+  mrc     p15, 4, r2, c15, c0, 0  @ Read periph base address
+
+  str     r1, [r2, #0x0C]         @ Write to SCU Invalidate All in Secure State
+  
+  bx      lr
+
+  .endfunc
+
+@ ------------------------------------------------------------
+@ End of cortexA9.s
+@ ------------------------------------------------------------
+    .end

bsp/imx6ul/platform/cpu/gic.c

+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <assert.h>
+#include "gic.h"
+#include "gic_registers.h"
+#include "cortex_a.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Prototypes
+////////////////////////////////////////////////////////////////////////////////
+
+static inline gicd_t * gic_get_gicd(void);
+static inline gicc_t * gic_get_gicc(void);
+static inline uint32_t irq_get_register_offset(uint32_t irqID);
+static inline uint32_t irq_get_bit_offset(uint32_t irqID);
+static inline uint32_t irq_get_bit_mask(uint32_t irqID);
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+static inline gicd_t * gic_get_gicd(void)
+{
+    uint32_t base = get_arm_private_peripheral_base() + kGICDBaseOffset;
+    return (gicd_t *)base;
+}
+
+static inline gicc_t * gic_get_gicc(void)
+{
+    uint32_t base = get_arm_private_peripheral_base() + kGICCBaseOffset;
+    return (gicc_t *)base;
+}
+
+static inline uint32_t irq_get_register_offset(uint32_t irqID)
+{
+    return irqID / 32;
+}
+
+static inline uint32_t irq_get_bit_offset(uint32_t irqID)
+{
+    return irqID & 0x1f;
+}
+
+static inline uint32_t irq_get_bit_mask(uint32_t irqID)
+{
+    return 1 << irq_get_bit_offset(irqID);    
+}
+
+void gic_enable(bool enableIt)
+{
+    gicd_t * gicd = gic_get_gicd();
+    
+    if (enableIt)
+    {
+        // Enable both secure and non-secure.
+        gicd->CTLR |= kBM_GICD_CTLR_EnableGrp0 | kBM_GICD_CTLR_EnableGrp1;
+    }
+    else
+    {
+        // Clear the enable bits.
+        gicd->CTLR &= ~(kBM_GICD_CTLR_EnableGrp0 | kBM_GICD_CTLR_EnableGrp1);
+    }
+}
+
+void gic_set_irq_security(uint32_t irqID, bool isSecure)
+{
+    gicd_t * gicd = gic_get_gicd();
+    
+    uint32_t reg = irq_get_register_offset(irqID);
+    uint32_t mask = irq_get_bit_mask(irqID);
+    
+    uint32_t value = gicd->IGROUPRn[reg];
+    if (!isSecure)
+    {
+        value &= ~mask;
+    }
+    else
+    {
+        value |= mask;
+    }
+    gicd->IGROUPRn[reg] = value;
+}
+
+void gic_enable_irq(uint32_t irqID, bool isEnabled)
+{
+    gicd_t * gicd = gic_get_gicd();
+    
+    uint32_t reg = irq_get_register_offset(irqID);
+    uint32_t mask = irq_get_bit_mask(irqID);
+    
+    // Select set-enable or clear-enable register based on enable flag.
+    if (isEnabled)
+    {
+        gicd->ISENABLERn[reg] = mask;
+    }
+    else
+    {
+        gicd->ICENABLERn[reg] = mask;
+    }
+}
+
+void gic_set_irq_priority(uint32_t ID, uint32_t priority)
+{
+    gicd_t * gicd = gic_get_gicd();
+    
+    // Update the priority register. The priority registers are byte accessible, and the register
+    // struct has the priority registers as a byte array, so we can just index directly by the
+    // interrupt ID.
+    gicd->IPRIORITYRn[ID] = priority & 0xff;
+}
+
+void gic_set_cpu_target(uint32_t irqID, unsigned cpuNumber, bool enableIt)
+{
+    // Make sure the CPU number is valid.
+    assert(cpuNumber <= 7);
+    
+    gicd_t * gicd = gic_get_gicd();
+    uint8_t cpuMask = 1 << cpuNumber;
+    
+    // Like the priority registers, the target registers are byte accessible, and the register
+    // struct has the them as a byte array, so we can just index directly by the
+    // interrupt ID.
+    if (enableIt)
+    {
+        gicd->ITARGETSRn[irqID] |= (cpuMask & 0xff);
+    }
+    else
+    {
+        gicd->ITARGETSRn[irqID] &= ~(cpuMask & 0xff);
+    }
+}
+
+void gic_send_sgi(uint32_t irqID, uint32_t target_list, uint32_t filter_list)
+{
+    gicd_t * gicd = gic_get_gicd();
+    
+    gicd->SGIR = (filter_list << kBP_GICD_SGIR_TargetListFilter)
+                    | (target_list << kBP_GICD_SGIR_CPUTargetList)
+                    | (irqID & 0xf);
+}
+
+void gic_cpu_enable(bool enableIt)
+{
+    gicc_t * gicc = gic_get_gicc();
+    
+    if (enableIt)
+    {
+        gicc->CTLR |= kBM_GICC_CTLR_EnableS | kBM_GICC_CTLR_EnableNS;
+    }
+    else
+    {
+        gicc->CTLR &= ~(kBM_GICC_CTLR_EnableS | kBM_GICC_CTLR_EnableNS);
+    }
+}
+
+void gic_set_cpu_priority_mask(uint32_t priority)
+{
+    gicc_t * gicc = gic_get_gicc();
+    gicc->PMR = priority & 0xff;    
+}
+
+uint32_t gic_read_irq_ack(void)
+{
+    gicc_t * gicc = gic_get_gicc();
+    return gicc->IAR;
+}
+
+void gic_write_end_of_irq(uint32_t irqID)
+{
+    gicc_t * gicc = gic_get_gicc();
+    gicc->EOIR = irqID;
+}
+
+void gic_init(void)
+{
+    gicd_t * gicd = gic_get_gicd();
+
+    // First disable the distributor.
+    gic_enable(false);
+    
+    // Clear all pending interrupts.
+    int i;
+    for (i = 0; i < 32; ++i)
+    {
+        gicd->ICPENDRn[i] = 0xffffffff;
+    }
+    
+    // Set all interrupts to secure.
+    for (i = 0; i < 8; ++i)
+    {
+        gicd->IGROUPRn[i] = 0;
+    }
+
+    // Init the GIC CPU interface.
+    gic_init_cpu();
+    
+    // Now enable the distributor.
+    gic_enable(true);
+}
+
+void gic_init_cpu(void)
+{
+    // Init the GIC CPU interface.
+    gic_set_cpu_priority_mask(0xff);
+
+    // Disable preemption.
+    gicc_t * gicc = gic_get_gicc();
+    gicc->BPR = 7;
+
+    // Enable signaling the CPU.
+    gic_cpu_enable(true);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/cpu/gic_registers.h

+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "sdk_types.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Offsets to the GIC registers.
+enum _gic_base_offsets
+{
+    kGICDBaseOffset = 0x1000,   //!< GIC distributor offset.
+#if defined(CHIP_MX6UL)
+    kGICCBaseOffset = 0x2000     //!< GIC CPU interface offset.
+#else    
+    kGICCBaseOffset = 0x100     //!< GIC CPU interface offset.
+#endif    
+};
+
+//! @brief GIC distributor registers.
+//!
+//! Uses the GICv2 register names, but does not include GICv2 registers.
+//!
+//! The IPRIORITYRn and ITARGETSRn registers are byte accessible, so their types are uint8_t
+//! instead of uint32_t to reflect this. These members are indexed directly with the interrupt
+//! number.
+struct _gicd_registers
+{
+    uint32_t CTLR;              //!< Distributor Control Register.
+    uint32_t TYPER;             //!< Interrupt Controller Type Register.
+    uint32_t IIDR;              //!< Distributor Implementer Identification Register.
+    uint32_t _reserved0[29];
+    uint32_t IGROUPRn[8];       //!< Interrupt Group Registers.
+    uint32_t _reserved1[24];
+    uint32_t ISENABLERn[32];    //!< Interrupt Set-Enable Registers.
+    uint32_t ICENABLERn[32];    //!< Interrupt Clear-Enable Registers.
+    uint32_t ISPENDRn[32];      //!< Interrupt Set-Pending Registers.
+    uint32_t ICPENDRn[32];      //!< Interrupt Clear-Pending Registers.
+    uint32_t ICDABRn[32];       //!< Active Bit Registers.
+    uint32_t _reserved2[32];
+    uint8_t IPRIORITYRn[255 * sizeof(uint32_t)];  //!< Interrupt Priority Registers. (Byte accessible)
+    uint32_t _reserved3;
+    uint8_t ITARGETSRn[255 * sizeof(uint32_t)];   //!< Interrupt Processor Targets Registers. (Byte accessible)
+    uint32_t _reserved4;
+    uint32_t ICFGRn[64];        //!< Interrupt Configuration Registers.
+    uint32_t _reserved5[128];
+    uint32_t SGIR;              //!< Software Generated Interrupt Register
+};
+
+//! @brief Bitfields constants for the GICD_CTLR register.
+enum _gicd_ctlr_fields
+{
+    kBM_GICD_CTLR_EnableGrp1 = (1 << 1),
+    kBM_GICD_CTLR_EnableGrp0 = (1 << 0)
+};
+
+//! @brief Bitfields constants for the GICD_SGIR register.
+enum _gicd_sgir_fields
+{
+    kBP_GICD_SGIR_TargetListFilter = 24,
+    kBM_GICD_SGIR_TargetListFilter = (0x3 << kBP_GICD_SGIR_TargetListFilter),
+    
+    kBP_GICD_SGIR_CPUTargetList = 16,
+    kBM_GICD_SGIR_CPUTargetList = (0xff << kBP_GICD_SGIR_CPUTargetList),
+    
+    kBP_GICD_SGIR_NSATT = 15,
+    kBM_GICD_SGIR_NSATT = (1 << kBP_GICD_SGIR_NSATT),
+    
+    kBP_GICD_SGIR_SGIINTID = 0,
+    kBM_GICD_SGIR_SGIINTID = 0xf
+};
+
+//! @brief GIC CPU interface registers.
+//!
+//! Uses the GICv2 register names. Does not include GICv2 registers.
+struct _gicc_registers
+{
+    uint32_t CTLR;  //!< CPU Interface Control Register.
+    uint32_t PMR;   //!< Interrupt Priority Mask Register.
+    uint32_t BPR;   //!< Binary Point Register.
+    uint32_t IAR;   //!< Interrupt Acknowledge Register.
+    uint32_t EOIR;  //!< End of Interrupt Register.
+    uint32_t RPR;   //!< Running Priority Register.
+    uint32_t HPPIR; //!< Highest Priority Pending Interrupt Register.
+    uint32_t ABPR;  //!< Aliased Binary Point Register. (only visible with a secure access)
+    uint32_t _reserved[56];
+    uint32_t IIDR;  //!< CPU Interface Identification Register.
+};
+
+//! @brief Bitfields constants for the GICC_CTLR register.
+enum _gicc_ctlr_fields
+{
+    kBP_GICC_CTLR_EnableS = 0,
+    kBM_GICC_CTLR_EnableS = (1 << 0),
+    
+    kBP_GICC_CTLR_EnableNS = 1,
+    kBM_GICC_CTLR_EnableNS = (1 << 1),
+    
+    kBP_GICC_CTLR_AckCtl = 2,
+    kBM_GICC_CTLR_AckCtl = (1 << 2),
+    
+    kBP_GICC_CTLR_FIQEn = 3,
+    kBM_GICC_CTLR_FIQEn = (1 << 3),
+    
+    kBP_GICC_CTLR_SBPR = 4,
+    kBM_GICC_CTLR_SBPR = (1 << 4)
+};
+
+//! @brier Type for the GIC distributor registers.
+typedef volatile struct _gicd_registers gicd_t;
+
+//! @brier Type for the GIC CPU interface registers.
+typedef volatile struct _gicc_registers gicc_t;
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/cpu/mmu.c

+/*
+ * Copyright (c) 2008-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * @file  mmu.c
+ * @brief System memory arangement.
+ */
+#include "cortex_a.h"
+#include "mmu.h"
+#include "arm_cp_registers.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Size in bytes of the first-level page table.
+#define MMU_L1_PAGE_TABLE_SIZE (16 * 1024)
+
+//! @brief First-level 1MB section descriptor entry.
+typedef union mmu_l1_section {
+    uint32_t u;
+    struct {
+        uint32_t id:2;  //!< ID
+        uint32_t b:1;   //!< Bufferable
+        uint32_t c:1;   //!< Cacheable
+        uint32_t xn:1;  //!< Execute-not
+        uint32_t domain:4;  //!< Domain
+        uint32_t _impl_defined:1;   //!< Implementation defined, should be zero.
+        uint32_t ap1_0:2;  //!< Access permissions AP[1:0]
+        uint32_t tex:3; //!< TEX remap
+        uint32_t ap2:1; //!< Access permissions AP[2] 
+        uint32_t s:1;   //!< Shareable
+        uint32_t ng:1;  //!< Not-global
+        uint32_t _zero:1;   //!< Should be zero.
+        uint32_t ns:1;  //!< Non-secure
+        uint32_t address:12;   //!< Physical base address
+    };
+} mmu_l1_section_t;
+
+enum {
+    kMMU_L1_Section_ID = 2,  //!< ID value for a 1MB section first-level entry.
+    kMMU_L1_Section_Address_Shift = 20  //!< Bit offset of the physical base address field.
+};
+
+////////////////////////////////////////////////////////////////////////////////
+// Externs
+////////////////////////////////////////////////////////////////////////////////
+
+extern char __l1_page_table_start;
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+void mmu_enable()
+{
+    // invalidate all tlb 
+    arm_unified_tlb_invalidate();
+
+    // read SCTLR 
+    uint32_t sctlr;
+    _ARM_MRC(15, 0, sctlr, 1, 0, 0);
+    
+    // set MMU enable bit 
+    sctlr |= BM_SCTLR_M;
+
+    // write modified SCTLR
+    _ARM_MCR(15, 0, sctlr, 1, 0, 0);
+}
+
+void mmu_disable()
+{
+    // read current SCTLR 
+    uint32_t sctlr;
+    _ARM_MRC(15, 0, sctlr, 1, 0, 0);
+    
+    // clear MMU enable bit 
+    sctlr &=~ BM_SCTLR_M;
+
+    // write modified SCTLR
+    _ARM_MCR(15, 0, sctlr, 1, 0, 0);
+}
+
+void mmu_init()
+{
+    // Get the L1 page table base address.
+    uint32_t * table = (uint32_t *)&__l1_page_table_start;
+    uint32_t share_attr = kShareable;
+
+    // write table address to TTBR0
+    _ARM_MCR(15, 0, table, 2, 0, 0);
+
+    // set Client mode for all Domains
+    uint32_t dacr = 0x55555555; 
+    _ARM_MCR(15, 0, dacr, 3, 0, 0); // MCR p15, 0, <Rd>, c3, c0, 0 ; Write DACR
+
+    // Clear the L1 table.
+    bzero(table, MMU_L1_PAGE_TABLE_SIZE);
+    
+    // Create default mappings.
+    mmu_map_l1_range(0x00000000, 0x00000000, 0x00900000, kStronglyOrdered, kShareable, kRWAccess); // ROM and peripherals
+    mmu_map_l1_range(0x00900000, 0x00900000, 0x00100000, kStronglyOrdered, kShareable, kRWAccess); // OCRAM
+    mmu_map_l1_range(0x00a00000, 0x00a00000, 0x0f600000, kStronglyOrdered, kShareable, kRWAccess); // More peripherals
+   
+    // Check whether SMP is enabled. If it is not, then we don't want to make SDRAM shareable.
+    uint32_t actlr = 0x0;
+    _ARM_MRC(15, 0, actlr, 1, 0, 1);
+    if (actlr & BM_ACTLR_SMP)
+    {
+        share_attr = kShareable;
+    }
+    else
+    {
+        share_attr = kNonshareable;
+    }
+
+#if defined(CHIP_MX6DQ) || defined(CHIP_MX6SDL)
+    mmu_map_l1_range(0x10000000, 0x10000000, 0x80000000, kOuterInner_WB_WA, share_attr, kRWAccess); // 2GB DDR
+#elif defined(CHIP_MX6SL) || defined(CHIP_MX6UL)
+    mmu_map_l1_range(0x80000000, 0x80000000, 0x40000000, kOuterInner_WB_WA, share_attr, kRWAccess); // 1GB DDR
+#else
+#error Unknown chip type!
+#endif
+}
+
+void mmu_map_l1_range(uint32_t pa, uint32_t va, uint32_t length, mmu_memory_type_t memoryType, mmu_shareability_t isShareable, mmu_access_t access)
+{
+    register mmu_l1_section_t entry;
+    entry.u = 0;
+    
+    // Set constant attributes.
+    entry.id = kMMU_L1_Section_ID;
+    entry.xn = 0; // Allow execution
+    entry.domain = 0; // Domain 0
+    entry.ng = 0; // Global
+    entry.ns = 0; // Secure
+    
+    // Set attributes based on the selected memory type.
+    switch (memoryType)
+    {
+        case kStronglyOrdered:
+            entry.c = 0;
+            entry.b = 0;
+            entry.tex = 0;
+            entry.s = 1; // Ignored
+            break;
+        case kDevice:
+            if (isShareable)
+            {
+                entry.c = 0;
+                entry.b = 1;
+                entry.tex = 0;
+                entry.s = 1; // Ignored
+            }
+            else
+            {
+                entry.c = 0;
+                entry.b = 0;
+                entry.tex = 2;
+                entry.s = 0; // Ignored
+            }
+            break;
+        case kOuterInner_WB_WA:
+            entry.c = 1;
+            entry.b = 1;
+            entry.tex = 1;
+            entry.s = isShareable;
+            break;
+        case kOuterInner_WT:
+            entry.c = 1;
+            entry.b = 0;
+            entry.tex = 0;
+            entry.s = isShareable;
+            break;
+        case kNoncacheable:
+            entry.c = 0;
+            entry.b = 0;
+            entry.tex = 1;
+            entry.s = isShareable;
+            break;
+    }
+    
+    // Set attributes from specified access mode.
+    switch (access)
+    {
+        case kNoAccess:
+            entry.ap2 = 0;
+            entry.ap1_0 = 0;
+            break;
+        case kROAccess:
+            entry.ap2 = 1;
+            entry.ap1_0 = 3;
+            break;
+        case kRWAccess:
+            entry.ap2 = 0;
+            entry.ap1_0 = 3;
+            break;
+    }
+    
+    // Get the L1 page table base address.
+    uint32_t * table = (uint32_t *)&__l1_page_table_start;
+    
+    // Convert addresses to 12-bit bases.
+    uint32_t vbase = va >> kMMU_L1_Section_Address_Shift;
+    uint32_t pbase = pa >> kMMU_L1_Section_Address_Shift;
+    uint32_t entries = length >> kMMU_L1_Section_Address_Shift;
+
+    // Fill in L1 page table entries.
+    for (; entries > 0; ++pbase, ++vbase, --entries)
+    {
+        entry.address = pbase;
+        table[vbase] = entry.u;
+    }
+    
+    // Invalidate TLB
+    arm_unified_tlb_invalidate();
+}
+
+bool mmu_virtual_to_physical(uint32_t virtualAddress, uint32_t * physicalAddress)
+{
+    uint32_t pa = 0;
+    
+    // VA to PA translation with privileged read permission check  
+    _ARM_MCR(15, 0, virtualAddress & 0xfffffc00, 7, 8, 0);
+    
+    // Read PA register 
+    _ARM_MRC(15, 0, pa, 7, 4, 0);
+    
+    // First bit of returned value is Result of conversion (0 is successful translation) 
+    if (pa & 1)
+    {
+        // We can try write permission also 
+        // VA to PA translation with privileged write permission check  
+        _ARM_MCR(15, 0, virtualAddress & 0xfffffc00, 7, 8, 1);
+        
+        // Read PA register 
+        _ARM_MRC(15, 0, pa, 7, 4, 0);
+        
+        // First bit of returned value is Result of conversion (0 is successful translation) 
+        if (pa & 1)
+        {
+            return false;
+        }
+    }
+    
+    if (physicalAddress)
+    {
+        // complete address returning base + offset
+        pa = (pa & 0xfffff000) | (virtualAddress & 0x00000fff);
+        *physicalAddress = pa;
+    }
+    
+    return true;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/cpu/mmu.h

+/*
+ * Copyright (c) 2008-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+//! @addtogroup diag_mmu
+//! @{
+
+/*!
+ * @file  mmu.h
+ * @brief System memory arrangement.
+ */
+
+#ifndef _MMU_H_
+#define _MMU_H_
+
+#include "sdk.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Memory region attributes.
+typedef enum _mmu_memory_type
+{
+    kStronglyOrdered,
+    kDevice,
+    kOuterInner_WB_WA,
+    kOuterInner_WT,
+    kNoncacheable,
+} mmu_memory_type_t;
+
+//! @brief Memory region shareability options.
+typedef enum _mmu_shareability
+{
+    kShareable = 1,
+    kNonshareable = 0
+} mmu_shareability_t;
+
+//! @brief Access permissions for a memory region.
+typedef enum _mmu_access
+{
+    kNoAccess,
+    kROAccess,
+    kRWAccess
+} mmu_access_t;
+
+////////////////////////////////////////////////////////////////////////////////
+// Prototypes
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Enable the MMU.
+ *
+ * The L1 page tables and MMU settings must have already been configured by
+ * calling mmu_init() before the MMU is enabled.
+ */
+void mmu_enable();
+
+/*!
+ * @brief Disable the MMU.
+ */
+void mmu_disable();
+
+/*!
+ * @brief Set up the default first-level page table.
+ *
+ * Initializes the L1 page table with the following regions:
+ *  - 0x00000000...0x00900000 : ROM and peripherals, strongly-ordered
+ *  - 0x00900000...0x00a00000 : OCRAM, strongly-ordered
+ *  - For MX6DQ or MX6SDL: 0x10000000...0x90000000 : DDR, normal, outer inner, write-back, write-allocate
+ *  - For MX6SL: 0x80000000...0xc0000000 : DDR, normal, outer inner, write-back, write-allocate
+ *
+ * If the CPU is participating in SMP, then the DDR regions are made shareable. Otherwise they
+ * are marked as non-shareable.
+ *
+ * The TTBR0 register is set to the base of the L1 table.
+ *
+ * All memory domains are configured to allow client access. However, note that only domain 0 is
+ * used by mmu_map_l1_range().
+ */
+void mmu_init();
+
+/*!
+ * @brief Maps a range of memory in the first-level page table.
+ *
+ * Entries in the first-level page table are filled in for the range of virtual addresses
+ * starting at @a va and continuing for @a length bytes. These virtual addreses are mapped
+ * to the physical addresses starting at @a pa and continuing for @a length bytes. All table
+ * entries for the range of mapped memory have the same attributes, which are selected with
+ * the @a memoryType, @a isShareable, and @a access parameters.
+ *
+ * @param pa The base physical address of the range to which the virtual address will be mapped.
+ * @param va The base virtual address of the range.
+ * @param length The size of the range to be mapped, in bytes. This value must be divisible by 1MB.
+ * @param memoryType The type of the memory region. This controls caching, buffering, ordering of
+ *      memory accesses, and other attributes of the region.
+ * @param isShareable The shareability of the physical memory. Ignored for strongly-ordered memory.
+ * @param access Access permissions.
+ */
+void mmu_map_l1_range(uint32_t pa, uint32_t va, uint32_t length, mmu_memory_type_t memoryType, mmu_shareability_t isShareable, mmu_access_t access);
+
+/*!
+ * @brief Convert virtual address to physical.
+ *
+ * First attempts a priviledged read translation for the current security mode. If that fails,
+ * a priviledged write translation, also for the current security mode, is attempted. If this
+ * second attempt at translation fails, then false will be returned.
+ *
+ * @param virtualAddress Virtual address to convert to a physical address.
+ * @param[out] physicalAddress This parameter is filled in with the physical address corresponding
+ *      to the virtual address passed in @a virtualAddress.
+ * @retval true The address returned through @a physicalAddress is valid.
+ * @retval false The conversion failed for some reason.
+ */
+bool mmu_virtual_to_physical(uint32_t virtualAddress, uint32_t * physicalAddress);
+
+#if defined(__cplusplus)
+}
+#endif
+
+//! @}
+
+#endif // _MMU_H_
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////
+

bsp/imx6ul/platform/drivers/epit.c

+/*
+ * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * @file epit.c
+ * @brief EPIT driver source file.
+ *
+ * @ingroup diag_timer
+ */
+
+#include "epit.h"
+
+#include "imx_timer.h"
+#include "interrupt.h"
+#include "ccm_pll.h"
+#include "registers/regsepit.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+void epit_reload_counter(uint32_t instance, uint32_t load_val)
+{
+    // set the load register especially if RLD=reload_mode=SET_AND_FORGET=1 
+    HW_EPIT_LR_WR(instance, load_val);
+}
+
+uint32_t epit_get_counter_value(uint32_t instance)
+{
+    return HW_EPIT_CNR_RD(instance);
+}
+
+void epit_set_compare_event(uint32_t instance, uint32_t compare_val)
+{
+    HW_EPIT_CMPR_WR(instance, compare_val);
+}
+
+uint32_t epit_get_compare_event(uint32_t instance)
+{
+    uint32_t status_register;
+
+    // get the status 
+    status_register = HW_EPIT_SR_RD(instance);
+    
+    // clear it if found set 
+    if (status_register & BM_EPIT_SR_OCIF)
+    {
+        HW_EPIT_SR_SET(instance, BM_EPIT_SR_OCIF);
+    }
+
+    // return the read value before the bit was cleared 
+    return status_register & BM_EPIT_SR_OCIF;
+}
+
+void epit_counter_disable(uint32_t instance)
+{
+    /* temporary workaround for the discovered issue when disabling the
+     * counter during end of count/reload/set compare flag ??.
+     * Set to the max value so that it ensures that the counter couldn't
+     * reach 0 when it is disabled.
+     */
+    HW_EPIT_LR_WR(instance, 0xFFFFFFFF);
+
+    // disable the counter 
+    HW_EPIT_CR_CLR(instance, BM_EPIT_CR_EN);
+
+    // ensure to leave the counter in a proper state
+    // by disabling the output compare interrupt
+    HW_EPIT_CR_CLR(instance, BM_EPIT_CR_OCIEN);
+    
+    // and clearing possible remaining compare event 
+    HW_EPIT_SR_SET(instance, BM_EPIT_SR_OCIF);
+}
+
+void epit_counter_enable(uint32_t instance, uint32_t load_val, uint32_t irq_mode)
+{
+    // set the load register especially if RLD=reload_mode=SET_AND_FORGET=1
+    // and if the value is different from 0 which is the lowest counter value
+    if (load_val != 0)
+    {
+        HW_EPIT_LR_WR(instance, load_val);
+    }
+
+    // ensure to start the counter in a proper state
+    // by clearing possible remaining compare event
+    HW_EPIT_SR_SET(instance, BM_EPIT_SR_OCIF);
+
+    // set the mode when the output compare event occur: IRQ or polling 
+    if (irq_mode == IRQ_MODE)
+    {
+        HW_EPIT_CR_SET(instance, BM_EPIT_CR_OCIEN);
+    }
+    else
+    {
+        // polling 
+        HW_EPIT_CR_CLR(instance, BM_EPIT_CR_OCIEN);
+    }
+
+    // finally, enable the counter 
+    HW_EPIT_CR_SET(instance, BM_EPIT_CR_EN);
+}
+
+void epit_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), bool enableIt)
+{
+    uint32_t irq_id = EPIT_IRQS(instance);
+
+    if (enableIt)
+    {    
+        // register the IRQ sub-routine 
+        register_interrupt_routine(irq_id, irq_subroutine);
+        
+        // enable the IRQ 
+        enable_interrupt(irq_id, CPU_0, 0);
+    }
+    else
+    {
+        // disable the IRQ 
+        disable_interrupt(irq_id, CPU_0);
+    }
+}
+
+void epit_init(uint32_t instance, uint32_t clock_src, uint32_t prescaler,
+               uint32_t reload_mode, uint32_t load_val, uint32_t low_power_mode)
+{
+    uint32_t control_reg_tmp = 0;
+    uint32_t base = REGS_EPIT_BASE(instance);
+
+    // enable the source clocks to the EPIT port 
+    clock_gating_config(base, CLOCK_ON);
+
+    // start with a known state by disabling and reseting the module 
+    HW_EPIT_CR_WR(instance, BM_EPIT_CR_SWR);
+    
+    // wait for the reset to complete 
+    while ((HW_EPIT_CR(instance).B.SWR) != 0) ;
+
+    // set the reference source clock for the counter 
+    control_reg_tmp |= BF_EPIT_CR_CLKSRC(clock_src);
+
+    // set the counter clock prescaler value - 0 to 4095 
+    control_reg_tmp |= BF_EPIT_CR_PRESCALAR(prescaler-1);
+
+    // set the reload mode 
+    if (reload_mode == SET_AND_FORGET)
+    {
+        control_reg_tmp |= BM_EPIT_CR_RLD;
+    }
+
+    // set behavior for low power mode 
+    if (low_power_mode & WAIT_MODE_EN)
+    {
+        control_reg_tmp |= BM_EPIT_CR_WAITEN;
+    }
+    if (low_power_mode & STOP_MODE_EN)
+    {
+        control_reg_tmp |= BM_EPIT_CR_STOPEN;
+    }
+
+    // make the counter start from a known value when enabled, this is loaded from
+    // EPITLR register if RLD=reload_mode=1 or 0xFFFFFFFF if RLD=reload_mode=0
+    control_reg_tmp |= BM_EPIT_CR_IOVW | BM_EPIT_CR_ENMOD;
+
+    // finally write the control register 
+    HW_EPIT_CR_WR(instance, control_reg_tmp);
+
+    // initialize the load register especially if RLD=reload_mode=SET_AND_FORGET=1 
+    // and if the value is different from 0 which is the lowest counter value
+    if (load_val != 0)
+    {
+        HW_EPIT_LR_WR(instance, load_val);
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/drivers/gpt.c

+/*
+ * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * @file gpt.c
+ * @brief  GPT driver source file.
+ *
+ * @ingroup diag_timer
+ */
+
+#include "sdk.h"
+#include "gpt.h"
+
+#include "imx_timer.h"
+#include "registers/regsgpt.h"
+#include "interrupt.h"
+#include "ccm_pll.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+static inline void gpt_clear_all_events(void)
+{
+    HW_GPT_SR_WR(kGPTAllEvents);
+}
+
+uint32_t gpt_get_rollover_event(void)
+{
+    // clear it if found set 
+    if (HW_GPT_SR.B.ROV)
+    {
+        HW_GPT_SR_WR(BM_GPT_SR_ROV);
+        return kGPTRollover;
+    }
+
+    // return the read value before the bit was cleared 
+    return 0;
+}
+
+uint32_t gpt_get_capture_event(uint8_t flag, uint32_t * capture_val)
+{
+    // get the capture status bit 
+    flag &= kGPTInputCapture1 | kGPTInputCapture2;
+    uint32_t status_register = HW_GPT_SR_RD() & flag;
+    
+    // Read the captured timer value.
+    if (capture_val)
+    {
+        if (status_register == kGPTInputCapture1)
+        {
+            *(uint32_t *) capture_val = HW_GPT_ICR1.B.CAPT;
+        }
+        else if (status_register == kGPTInputCapture2)
+        {
+            *(uint32_t *) capture_val = HW_GPT_ICR2.B.CAPT;
+        }
+    }
+    
+    // Clear the flag.
+    HW_GPT_SR_WR(status_register);
+
+    // return the read value before the bit was cleared 
+    return status_register;
+}
+
+void gpt_set_capture_event(uint8_t cap_input, uint8_t cap_input_mode)
+{
+    // set the new input mode 
+    switch (cap_input)
+    {
+        case kGPTInputCapture1:
+            HW_GPT_CR.B.IM1 = cap_input_mode;
+            break;
+            
+        case kGPTInputCapture2:
+            HW_GPT_CR.B.IM2 = cap_input_mode;
+            break;
+    }
+}
+
+uint32_t gpt_get_compare_event(uint8_t flag)
+{
+    // get the active compare flags 
+    flag &= kGPTOutputCompare1 | kGPTOutputCompare2 | kGPTOutputCompare3;
+    uint32_t status_register = HW_GPT_SR_RD() & flag;
+    
+    // clear flags which are active 
+    if (status_register)
+    {
+        HW_GPT_SR_WR(status_register);
+    }
+
+    // return the read value before the flags were cleared
+    return status_register;
+}
+
+void gpt_set_compare_event(uint8_t cmp_output, uint8_t cmp_output_mode, uint32_t cmp_value)
+{
+    // set the value to compare with 
+    switch (cmp_output)
+    {
+        case kGPTOutputCompare1:
+            BW_GPT_CR_OM1(cmp_output_mode);
+            HW_GPT_OCR1_WR(cmp_value);
+            break;
+
+        case kGPTOutputCompare2:
+            BW_GPT_CR_OM2(cmp_output_mode);
+            HW_GPT_OCR2_WR(cmp_value);
+            break;
+
+        case kGPTOutputCompare3:
+            BW_GPT_CR_OM3(cmp_output_mode);
+            HW_GPT_OCR3_WR(cmp_value);
+            break;
+    }
+}
+
+void gpt_counter_disable(void)
+{
+    // disable the counter 
+    HW_GPT_CR.B.EN = 0;
+
+    // ensure to leave the counter in a proper state by disabling the interrupt sources
+    HW_GPT_IR_WR(0);
+    
+    // and by clearing possible remaining events 
+    gpt_clear_all_events();
+}
+
+void gpt_counter_enable(uint32_t irq_mode)
+{
+    // ensure to start the counter in a proper state by clearing possible remaining events
+    gpt_clear_all_events();
+
+    // enable the interrupts or clear the register for polling 
+    HW_GPT_IR_WR(irq_mode & kGPTAllEvents);
+
+    // finally, enable the counter 
+    HW_GPT_CR.B.EN = 1;
+}
+
+void gpt_setup_interrupt(void (*irq_subroutine)(void), bool enableIt)
+{
+    uint32_t irq_id = IMX_INT_GPT;
+
+    if (enableIt)
+    {    
+        // register the IRQ sub-routine 
+        register_interrupt_routine(irq_id, irq_subroutine);
+        
+        // enable the IRQ 
+        enable_interrupt(irq_id, CPU_0, 0);
+    }
+    else
+    {
+        // disable the IRQ 
+        disable_interrupt(irq_id, CPU_0);
+    }
+}
+
+void gpt_init(uint32_t clock_src, uint32_t prescaler, uint32_t counter_mode, uint32_t low_power_mode)
+{
+    uint32_t control_reg_tmp = 0;
+    uint32_t base = GPT_BASE_ADDR;
+
+    // enable the source clocks to the GPT port 
+    clock_gating_config(base, CLOCK_ON);
+
+    // start with a known state by disabling and reseting the module 
+    HW_GPT_CR_WR(BM_GPT_CR_SWR);
+    
+    // wait for the reset to complete 
+    while (HW_GPT_CR.B.SWR != 0) ;
+
+    // set the reference source clock for the counter 
+    if (clock_src == CLKSRC_CKIL)
+    {
+        // CKIL source is 0x4 for GPT but 0x3 for EPIT
+        clock_src++;
+    }
+    control_reg_tmp |= BF_GPT_CR_CLKSRC(clock_src);
+
+    // the prescaler can be changed at any time, and 
+    // this affects the output clock immediately
+    HW_GPT_PR_WR(BF_GPT_PR_PRESCALER(prescaler - 1));
+
+    // set the counter mode 
+    control_reg_tmp |= BF_GPT_CR_FRR(counter_mode);
+
+    // set behavior for low power mode 
+    if (low_power_mode & WAIT_MODE_EN)
+    {
+        control_reg_tmp |= BM_GPT_CR_WAITEN;
+    }
+    if (low_power_mode & STOP_MODE_EN)
+    {
+        control_reg_tmp |= BM_GPT_CR_STOPEN;
+    }
+
+    // specify from where the counter starts to count when enabled 
+    // this code makes it start from 0 
+    control_reg_tmp |= BM_GPT_CR_ENMOD;
+
+    // finally write the control register 
+    HW_GPT_CR_WR(control_reg_tmp);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/drivers/imx_i2c.c

+/*
+ * Copyright (c) 2010-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * @file imx_i2c.c
+ * @brief Main driver for the I2C controller. It initializes the controller
+ *        and handles the master mode.
+ *
+ * @ingroup diag_i2c
+ */
+
+#include "sdk.h"
+#include "imx_i2c.h"
+#include "imx_i2c_internal.h"
+#include "registers/regsi2c.h"
+#include "ccm_pll.h"
+#include "interrupt.h"
+
+//! Set this macro to 1 to enable tracing of data send and receive.
+#define TRACE_I2C 0
+
+//! @brief Get the irq id of I2C by instance number.
+//! @param x I2C instance number, from 1 through 3.
+#define I2C_IRQS(x) ( (x) == HW_I2C1 ? IMX_INT_I2C1 : (x) == HW_I2C2 ? IMX_INT_I2C2 : (x) == HW_I2C3 ? IMX_INT_I2C3 : 0xFFFFFFFF)
+
+////////////////////////////////////////////////////////////////////////////////
+// Constants
+////////////////////////////////////////////////////////////////////////////////
+
+static const uint16_t i2c_freq_div[50][2] = {
+        { 22,   0x20 }, { 24,   0x21 }, { 26,   0x22 }, { 28,   0x23 },
+        { 30,   0x00 }, { 32,   0x24 }, { 36,   0x25 }, { 40,   0x26 },
+        { 42,   0x03 }, { 44,   0x27 }, { 48,   0x28 }, { 52,   0x05 },
+        { 56,   0x29 }, { 60,   0x06 }, { 64,   0x2A }, { 72,   0x2B },
+        { 80,   0x2C }, { 88,   0x09 }, { 96,   0x2D }, { 104,  0x0A },
+        { 112,  0x2E }, { 128,  0x2F }, { 144,  0x0C }, { 160,  0x30 },
+        { 192,  0x31 }, { 224,  0x32 }, { 240,  0x0F }, { 256,  0x33 },
+        { 288,  0x10 }, { 320,  0x34 }, { 384,  0x35 }, { 448,  0x36 },
+        { 480,  0x13 }, { 512,  0x37 }, { 576,  0x14 }, { 640,  0x38 },
+        { 768,  0x39 }, { 896,  0x3A }, { 960,  0x17 }, { 1024, 0x3B },
+        { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
+        { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
+        { 3072, 0x1E }, { 3840, 0x1F }
+};
+
+////////////////////////////////////////////////////////////////////////////////
+// Prototypes
+////////////////////////////////////////////////////////////////////////////////
+
+static inline int is_bus_free(unsigned int instance);
+static int wait_till_busy(uint32_t instance);
+static inline void imx_send_stop(unsigned int instance);
+static int wait_op_done(uint32_t instance, int is_tx);
+static int tx_byte(uint8_t * data, uint32_t instance);
+static int rx_bytes(uint8_t * data, uint32_t instance, int sz);
+static void set_i2c_clock(uint32_t instance, uint32_t baud);
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+unsigned i2c_get_request_instance(const imx_i2c_request_t * rq)
+{
+    // First see if there device info is set.
+    if (rq->device)
+    {
+        // Use the instance number in the device info.
+        return rq->device->port;
+    }
+    
+    // Check if the ctl_addr is within the range of instances.
+    if (rq->ctl_addr >= 1 && rq->ctl_addr <= HW_I2C_INSTANCE_COUNT)
+    {
+        // Valid instance number, so use it directly.
+        return rq->ctl_addr;
+    }
+    else
+    {
+        // Not a valid instance, so treat it as a base address.
+        return REGS_I2C_INSTANCE(rq->ctl_addr);
+    }
+}
+
+/*!
+ * @brief Loop status register for IBB to go 0.
+ *
+ * The loop also breaks on max number of iterations.
+ *
+ * @param instance Instance number of the I2C module.
+ *
+ * @return  0 if successful; -1 otherwise
+ */
+static inline int is_bus_free(unsigned int instance)
+{
+    int i = WAIT_RXAK_LOOPS;
+
+    while (HW_I2C_I2SR(instance).B.IBB && (--i > 0));
+
+    if (i <= 0) {
+        debug_printf("Error: I2C Bus not free!\n");
+        return -1;
+    }
+
+    return 0;
+}
+
+/*!
+ * @brief Loop status register for IBB to go 1.
+ *
+ * It breaks the loop if there's an arbitration lost occurred or the maximum
+ * number of iterations has been reached.
+ *
+ * @param instance Instance number of the I2C module.
+ *
+ * @return  0 if successful; -1 otherwise
+ */
+static int wait_till_busy(uint32_t instance)
+{
+    int i = WAIT_BUSY_LOOPS;
+
+    while (!HW_I2C_I2SR(instance).B.IBB && (--i > 0)) {
+        if (HW_I2C_I2SR(instance).B.IAL) {
+            debug_printf("Error: arbitration lost!\n");
+            return -1;
+        }
+    }
+
+    if (i <= 0) {
+        debug_printf("I2C Error: timeout in %s; %d\n", __FUNCTION__, __LINE__);
+        return -1;
+    }
+
+    return 0;
+}
+
+/*!
+ * Generates a STOP signal, called by rx and tx routines
+ *
+ * @param instance Instance number of the I2C module.
+ *
+ * @return  none
+ */
+static inline void imx_send_stop(unsigned int instance)
+{
+    HW_I2C_I2CR(instance).B.MSTA = 0;
+}
+
+/*!
+ * @brief Wait for operation done.
+ *
+ * This function loops until we get an interrupt. On timeout it returns -1.
+ * It reports arbitration lost if IAL bit of I2SR register is set
+ * Clears the interrupt
+ * If operation is transfer byte function will make sure we received an ack
+ *
+ * @param instance Instance number of the I2C module.
+ * @param   is_tx       Pass 1 for transfering, 0 for receiving 
+ *
+ * @return  0 if successful; negative integer otherwise
+ */
+static int wait_op_done(uint32_t instance, int is_tx)
+{
+    hw_i2c_i2sr_t v;
+    int i = WAIT_RXAK_LOOPS;
+
+    // Loop until we get an interrupt 
+    do {
+        v.U = HW_I2C_I2SR_RD(instance);
+    } while (!v.B.IIF && (--i > 0));
+
+    // If timeout error occurred return error 
+    if (i <= 0) {
+        debug_printf("I2C Error: timeout unexpected\n");
+        return -1;
+    }
+
+    // Clear the interrupts 
+    HW_I2C_I2SR_WR(instance, 0);
+
+    // Check for arbitration lost 
+    if (v.B.IAL) {
+        debug_printf("Error %d: Arbitration lost\n", __LINE__);
+        return ERR_ARB_LOST;
+    }
+
+    // Check for ACK received in transmit mode 
+    if (is_tx) {
+        if (v.B.RXAK) {
+            // No ACK received, generate STOP by clearing MSTA bit 
+            debug_printf("Error %d: no ack received\n", __LINE__);
+            
+            // Generate a STOP signal 
+            imx_send_stop(instance);
+            return ERR_NO_ACK;
+        }
+    }
+
+    return 0;
+}
+
+/*!
+ * @brief Implements a loop to send a byte to I2C slave.
+ *
+ * For master transmit. Always expect a RXAK signal to be set!
+ *
+ * @param   data        return buffer for data
+ * @param instance Instance number of the I2C module.
+ *
+ * @return  0 if successful; -1 otherwise
+ */
+static int tx_byte(uint8_t * data, uint32_t instance)
+{
+#if TRACE_I2C
+    debug_printf("%s(data=0x%02x, instance=%d)\n", __FUNCTION__, *data, instance);
+#endif // TRACE_I2C
+
+    // clear both IAL and IIF bits 
+    HW_I2C_I2SR_WR(instance, 0);
+
+    // write to data register 
+    HW_I2C_I2DR_WR(instance, *data);
+
+    // wait for transfer of byte to complete 
+    return wait_op_done(instance, 1);
+}
+
+/*!
+ * @brief Implements a loop to receive bytes from I2C slave.
+ *
+ * For master receive.
+ *
+ * @param   data        return buffer for data
+ * @param instance Instance number of the I2C module.
+ * @param   sz          number of bytes to receive
+ *
+ * @return  0 if successful; -1 otherwise
+ */
+static int rx_bytes(uint8_t * data, uint32_t instance, int sz)
+{
+    int i;
+
+    for (i = 0; sz > 0; sz--, i++) {
+        if (wait_op_done(instance, 0) != 0) {
+            return -1;
+        }
+
+        // the next two if-statements setup for the next read control register value 
+        if (sz == 1) {
+            // last byte --> generate STOP 
+            // generate STOP by clearing MSTA bit 
+            imx_send_stop(instance);
+        }
+
+        if (sz == 2) {
+            // 2nd last byte --> set TXAK bit to NOT generate ACK 
+            HW_I2C_I2CR(instance).B.TXAK = 1;
+        }
+        
+        // read the true data 
+        data[i] = HW_I2C_I2DR_RD(instance);
+#if TRACE_I2C
+
+        debug_printf("OK 0x%02x\n", data[i]);
+#endif // TRACE_I2C
+    }
+
+    return 0;
+}
+
+static void set_i2c_clock(uint32_t instance, uint32_t baud)
+{
+    // Adjust the divider to get the closest SCL frequency to baud rate 
+    uint32_t src_clk = get_main_clock(IPG_PER_CLK);
+    uint32_t divider = src_clk / baud;
+    uint8_t index = 0;
+    
+    if (divider < i2c_freq_div[0][0])
+    {
+        divider = i2c_freq_div[0][0];
+        index = 0;
+        debug_printf("Warning :can't find a smaller divider than %d.\n", divider);
+        debug_printf("SCL frequency is set at %d - expected was %d.\n", src_clk/divider, baud);
+    }
+    else if (divider > i2c_freq_div[49][0])
+    {
+        divider = i2c_freq_div[49][0];
+        index = 49;
+        debug_printf("Warning: can't find a bigger divider than %d.\n", divider);
+        debug_printf("SCL frequency is set at %d - expected was %d.\n", src_clk/divider, baud);
+    }
+    else
+    {
+        for (index = 0; i2c_freq_div[index][0] < divider; index++);
+        divider = i2c_freq_div[index][0];
+    }
+    
+    HW_I2C_IFDR_WR(instance, BF_I2C_IFDR_IC(i2c_freq_div[index][1]));
+}
+
+int i2c_xfer(const imx_i2c_request_t *rq, int dir)
+{
+    uint32_t reg;
+    uint32_t ret = 0;
+    uint16_t i2cr;
+    uint8_t i;
+    uint8_t data;
+    uint32_t instance = i2c_get_request_instance(rq);
+    uint8_t address = (rq->device ? rq->device->address : rq->dev_addr) << 1;
+
+    if (rq->buffer_sz == 0 || rq->buffer == NULL) {
+        debug_printf("Invalid register address size=%x, buffer size=%x, buffer=%x\n",
+               rq->reg_addr_sz, rq->buffer_sz, (unsigned int)rq->buffer);
+        return ERR_INVALID_REQUEST;
+    }
+
+    // clear the status register 
+    HW_I2C_I2SR_WR(instance, 0);
+
+    // enable the I2C controller 
+    HW_I2C_I2CR_WR(instance, BM_I2C_I2CR_IEN);
+
+    // Check if bus is free, if not return error 
+    if (is_bus_free(instance) != 0) {
+        return -1;
+    }
+    
+    // If the request has device info attached and it has a non-zero bit rate, then
+    // change the clock to the specified rate.
+    if (rq->device && rq->device->freq)
+    {
+        set_i2c_clock(instance, rq->device->freq);
+    }
+
+    // Step 1: Select master mode, assert START signal and also indicate TX mode 
+    HW_I2C_I2CR_WR(instance, BM_I2C_I2CR_IEN | BM_I2C_I2CR_MSTA | BM_I2C_I2CR_MTX);
+
+    // make sure bus is busy after the START signal 
+    if (wait_till_busy(instance) != 0) {
+        debug_printf("1\n");
+        return -1;
+    }
+    
+    // Step 2: send slave address + read/write at the LSB 
+    data = address | I2C_WRITE;
+
+    if ((ret = tx_byte(&data, instance)) != 0) {
+        debug_printf("START TX ERR %d\n", ret);
+
+        if (ret == ERR_NO_ACK) {
+            return ERR_NO_ACK_ON_START;
+        } else {
+            return ret;
+        }
+    }
+    
+    // Step 3: send I2C device register address 
+    if (rq->reg_addr_sz > 4) {
+        debug_printf("Warning register address size %d should less than 4\n", rq->reg_addr_sz);
+        return ERR_INVALID_REQUEST;
+    }
+
+    reg = rq->reg_addr;
+
+    for (i = 0; i < rq->reg_addr_sz; i++, reg >>= 8) {
+        data = reg & 0xFF;
+        
+#if TRACE_I2C
+        debug_printf("sending I2C=%d device register: data=0x%x, byte %d\n", instance, data, i);
+#endif // TRACE_I2C
+
+        if (tx_byte(&data, instance) != 0) {
+            return -1;
+        }
+    }
+
+    // Step 4: read/write data 
+    if (dir == I2C_READ) {
+        // do repeat-start 
+        HW_I2C_I2CR(instance).B.RSTA = 1;
+
+        // make sure bus is busy after the REPEATED START signal 
+        if (wait_till_busy(instance) != 0) {
+            return ERR_TX;
+        }
+        
+        // send slave address again, but indicate read operation 
+        data = address | I2C_READ;
+
+        if (tx_byte(&data, instance) != 0) {
+            return -1;
+        }
+
+        // change to receive mode 
+        i2cr = HW_I2C_I2CR_RD(instance) & ~BM_I2C_I2CR_MTX;
+        
+        // if only one byte to read, make sure don't send ack 
+        if (rq->buffer_sz == 1) {
+            i2cr |= BM_I2C_I2CR_TXAK;
+        }
+        HW_I2C_I2CR_WR(instance, i2cr);
+
+        // dummy read 
+        data = HW_I2C_I2DR_RD(instance);
+
+        // now reading ... 
+        if (rx_bytes(rq->buffer, instance, rq->buffer_sz) != 0) {
+            return -1;
+        }
+    } else {
+        // I2C_WRITE 
+        for (i = 0; i < rq->buffer_sz; i++) {
+            // send device register value 
+            data = rq->buffer[i];
+
+            if ((ret = tx_byte(&data, instance)) != 0) {
+                break;
+            }
+        }
+    }
+
+    // generate STOP by clearing MSTA bit 
+    imx_send_stop(instance);
+
+    // Check if bus is free, if not return error 
+    if (is_bus_free(instance) != 0) {
+        debug_printf("WARNING: bus is not free\n");
+    }
+    
+    // disable the controller 
+    HW_I2C_I2CR_WR(instance, 0);
+
+    return ret;
+}
+
+int i2c_read(const imx_i2c_request_t *rq)
+{
+    return i2c_xfer(rq, I2C_READ);
+}
+
+int i2c_write(const imx_i2c_request_t *rq)
+{
+    return i2c_xfer(rq, I2C_WRITE);
+}
+
+void i2c_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), bool state)
+{
+    uint32_t irq_id = I2C_IRQS(instance);
+
+    if (state) {
+        // register the IRQ sub-routine 
+        register_interrupt_routine(irq_id, irq_subroutine);
+        
+        // enable the IRQ at the ARM core level 
+        enable_interrupt(irq_id, CPU_0, 0);
+        
+        // clear the status register 
+        HW_I2C_I2SR_WR(instance, 0);
+        
+        // and enable the interrupts in the I2C controller 
+        HW_I2C_I2CR(instance).B.IIEN = 1;
+    } else {
+        // disable the IRQ at the ARM core level 
+        disable_interrupt(irq_id, CPU_0);
+        
+        // and disable the interrupts in the I2C controller 
+        HW_I2C_I2CR(instance).B.IIEN = 0;
+        
+        // clear the status register 
+        HW_I2C_I2SR_WR(instance, 0);
+    }
+}
+
+int i2c_init(uint32_t base, uint32_t baud)
+{
+    int instance;
+    
+    // Accept either an instance or base address for the base param.
+    if (base >= 1 && base <= HW_I2C_INSTANCE_COUNT)
+    {
+        instance = base;
+    }
+    else
+    {
+        instance = REGS_I2C_INSTANCE(base);
+    }
+    
+    // enable the source clocks to the I2C port 
+    clock_gating_config(REGS_I2C_BASE(instance), CLOCK_ON);
+
+    // Set iomux configuration 
+    i2c_iomux_config(instance);
+
+    // reset I2C 
+    HW_I2C_I2CR_WR(instance, 0);
+
+    // Set clock.
+    set_i2c_clock(instance, baud);
+
+    // set an I2C slave address 
+    HW_I2C_IADR_WR(instance, IMX6_DEFAULT_SLAVE_ID);
+
+    // clear the status register 
+    HW_I2C_I2SR_WR(instance, 0);
+
+    // enable the I2C controller 
+    HW_I2C_I2CR_WR(instance, BM_I2C_I2CR_IEN);
+
+    return 0;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/drivers/imx_i2c_internal.h

+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __IMX_I2C_INTERNAL_H__
+#define __IMX_I2C_INTERNAL_H__
+
+#include "imx_i2c.h"
+#include "registers/regsi2c.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! Max number of operations to wait to receive ack.
+#define WAIT_RXAK_LOOPS     1000000
+
+//! Max number of operations to wait until busy.
+#define WAIT_BUSY_LOOPS     100000
+
+////////////////////////////////////////////////////////////////////////////////
+// API
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Setup I2C interrupt.
+ *
+ * It enables or disables the related HW module interrupt, and attached the related
+ * sub-routine into the vector table.
+ *
+ * @param   port Pointer to the I2C module structure.
+ * @param   state Enable or disable the interrupt. Pass true to enable.
+ */
+void i2c_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), bool state);
+
+/*!
+ * @brief I2C interrupt routine for slave transfers.
+ */
+void i2c_slave_interrupt_routine(void);
+
+//! @brief Returns the I2C controller instance from a request struct.
+unsigned i2c_get_request_instance(const imx_i2c_request_t * rq);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // __IMX_I2C_INTERNAL_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/drivers/imx_timer.c

+/*
+ * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * @file timer.c
+ * @brief Basic timer functions
+ *
+ * @ingroup diag_timer
+ */
+
+#include <assert.h>
+
+#include "imx_timer.h"
+#include "sdk.h"
+#include "epit.h"
+#include "registers/regsarmglobaltimer.h"
+#include "ccm_pll.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Prototypes
+////////////////////////////////////////////////////////////////////////////////
+
+static void time_init_global_timer();
+
+////////////////////////////////////////////////////////////////////////////////
+// Variables
+////////////////////////////////////////////////////////////////////////////////
+
+uint32_t g_microsecondTimerMultiple=8;
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+void hal_delay_us(uint32_t usecs)
+{
+    uint32_t instance = g_system_timer_port;
+    if (usecs == 0) {
+        return;
+    }
+
+    /* enable the counter first */
+    epit_counter_enable(instance, usecs, POLLING_MODE);
+    
+    /* wait for the compare event */
+    while (!epit_get_compare_event(instance)) ;
+    
+    /* disable the counter to save power */
+    epit_counter_disable(instance);
+}
+
+void system_time_init(void)
+{
+    uint32_t freq;
+    // Init microsecond tick counter.
+    time_init_global_timer();
+    
+    /* EPIT1 is used for the delay function */
+    /* Initialize the EPIT timer used for system time functions */
+    /* typical IPG_CLK is in MHz, so divide it to get a reference
+       clock of 1MHz => 1us per count */
+    freq = get_main_clock(IPG_CLK);
+    epit_init(g_system_timer_port, CLKSRC_IPG_CLK, freq / 1000000,
+              SET_AND_FORGET, 1000, WAIT_MODE_EN | STOP_MODE_EN);
+}
+
+#if defined(CHIP_MX6UL)
+//! Init the ARM global timer to a microsecond-frequency clock.
+void time_init_global_timer()
+{
+    // Make sure the timer is off.
+    HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 0;
+    
+    HW_ARMGLOBALTIMER_CONTROL.B.FCR0 =1;
+    
+    HW_ARMGLOBALTIMER_CONTROL.B.FCR1 =0;
+    
+    HW_ARMGLOBALTIMER_CONTROL.B.DBG_ENABLE =0;
+    
+    // Clear counter.
+    HW_ARMGLOBALTIMER_COUNTER_HI_WR(0);
+    HW_ARMGLOBALTIMER_COUNTER_LO_WR(0);
+    
+    // Now turn on the timer.
+    HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 1;
+}
+
+uint64_t time_get_microseconds()
+{
+    // First read upper.
+    uint32_t upper = HW_ARMGLOBALTIMER_COUNTER_HI_RD();
+    uint32_t lower = HW_ARMGLOBALTIMER_COUNTER_LO_RD();
+
+    return (((uint64_t)upper << 32) | (uint64_t)lower)/8;
+}
+#else
+//! Init the ARM global timer to a microsecond-frequency clock.
+void time_init_global_timer()
+{
+    // The ARM private peripheral clock is half the CPU clock.
+    uint32_t periphClock = get_main_clock(CPU_CLK) / 2;
+    uint32_t prescaler = (periphClock / 1000000) - 1;
+    
+    // Divide down the prescaler until it fits into 8 bits. We add up the number of ticks
+    // it takes to equal a microsecond interval.
+    g_microsecondTimerMultiple = 1;
+    while (prescaler > 0xff)
+    {
+        prescaler /= 2;
+        ++g_microsecondTimerMultiple;
+    }
+    
+    // Make sure the timer is off.
+    HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 0;
+    
+    // Clear counter.
+    HW_ARMGLOBALTIMER_COUNTERn_WR(0, 0);
+    HW_ARMGLOBALTIMER_COUNTERn_WR(1, 0);
+    
+    // Set prescaler and clear other flags.
+    HW_ARMGLOBALTIMER_CONTROL_WR(BF_ARMGLOBALTIMER_CONTROL_PRESCALER(prescaler));
+    
+    // Now turn on the timer.
+    HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 1;
+}
+
+uint64_t time_get_microseconds()
+{
+    // First read upper.
+    uint32_t upper = HW_ARMGLOBALTIMER_COUNTERn_RD(1);
+    uint32_t lower;
+    
+    while (true)
+    {
+        // Read lower.
+        lower = HW_ARMGLOBALTIMER_COUNTERn_RD(0);
+        
+        // Read upper again.
+        uint32_t newUpper = HW_ARMGLOBALTIMER_COUNTERn_RD(1);
+        
+        // If the first and second read of the upper bits are the same, then return.
+        if (newUpper == upper)
+        {
+            return (((uint64_t)upper << 32) | (uint64_t)lower) / g_microsecondTimerMultiple;
+        }
+        
+        // Otherwise, start over again.
+        upper = newUpper;
+    }
+    
+    return 0;
+}
+#endif
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////
+

bsp/imx6ul/platform/drivers/imx_uart.c

+/*
+ * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * @file imx_uart.c
+ * @brief UART driver.
+
+ * @ingroup diag_uart
+ */
+
+#include "sdk.h"
+#include "registers/regsuart.h"
+#include "imx_uart.h"
+#include "ccm_pll.h"
+#include "interrupt.h"
+
+#define UART_UFCR_RFDIV    BF_UART_UFCR_RFDIV(4) 
+//#define UART_UFCR_RFDIV     UART_UFCR_RFDIV_4
+//#define UART_UFCR_RFDIV     UART_UFCR_RFDIV_7
+
+uint32_t uart_get_reffreq(uint32_t instance)
+{
+    uint32_t div = UART_UFCR_RFDIV;
+    uint32_t ret = 0;
+    uint32_t freq = get_peri_clock(UART_MODULE_CLK(instance));
+
+    if (div == BF_UART_UFCR_RFDIV(4))
+        ret = freq / 2;
+    else if (div == BF_UART_UFCR_RFDIV(2))
+        ret = freq / 4;
+    else if (div == BF_UART_UFCR_RFDIV(6))
+        ret = freq / 7;
+
+    return ret;
+}
+
+uint8_t uart_putchar(uint32_t instance, uint8_t * ch)
+{
+    /* Wait for Tx FIFO not full */
+    while (HW_UART_UTS(instance).B.TXFULL);
+
+    HW_UART_UTXD_WR(instance, *ch);
+
+    return *ch;
+}
+
+uint8_t uart_getchar(uint32_t instance)
+{
+    uint32_t read_data;
+
+    /* If Rx FIFO has no data ready */
+    if (!(HW_UART_USR2(instance).B.RDR))
+        return NONE_CHAR;
+
+    read_data = HW_UART_URXD_RD(instance); 
+
+    /* If error are detected */
+    if (read_data & 0x7C00)
+        return NONE_CHAR;
+
+    return (uint8_t) read_data;
+}
+
+void uart_set_FIFO_mode(uint32_t instance, uint8_t fifo, uint8_t trigger_level,
+                        uint8_t service_mode)
+{
+    if (fifo == TX_FIFO) {
+        /* Configure the TX_FIFO trigger level */
+        HW_UART_UFCR_CLR(instance,BM_UART_UFCR_TXTL);
+        HW_UART_UFCR_SET(instance, BF_UART_UFCR_TXTL(trigger_level)); 
+        /* Configure the TX_FIFO service mode */
+        /* Default mode is polling: IRQ and DMA requests are disabled */
+        HW_UART_UCR1_CLR(instance,(BM_UART_UCR1_TRDYEN | BM_UART_UCR1_TXDMAEN));
+        if (service_mode == DMA_MODE)
+           HW_UART_UCR1_SET(instance,BM_UART_UCR1_TXDMAEN);
+        else if (service_mode == IRQ_MODE)
+            HW_UART_UCR1_SET(instance,BM_UART_UCR1_TRDYEN); 
+    } else {                    /* fifo = RX_FIFO */
+        /* Configure the RX_FIFO trigger level */
+         HW_UART_UFCR_CLR(instance,BM_UART_UFCR_RXTL);
+        HW_UART_UFCR_SET(instance,BF_UART_UFCR_RXTL(trigger_level)); 
+        /* Configure the RX_FIFO service mode */
+        /* Default mode is polling: IRQ and DMA requests are disabled */
+        HW_UART_UCR1_CLR(instance,(BM_UART_UCR1_RRDYEN | BM_UART_UCR1_RXDMAEN)); 
+        if (service_mode == DMA_MODE)
+            HW_UART_UCR1_SET(instance,BM_UART_UCR1_RXDMAEN); 
+        else if (service_mode == IRQ_MODE)
+            HW_UART_UCR1_SET(instance,BM_UART_UCR1_RRDYEN); 
+    }
+}
+
+void uart_set_loopback_mode(uint32_t instance, uint8_t state)
+{
+    if (state == TRUE)
+	HW_UART_UTS_SET(instance, BM_UART_UTS_LOOP);
+    else
+        HW_UART_UTS_CLR(instance, BM_UART_UTS_LOOP);
+}
+
+void uart_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), uint8_t state)
+{
+    uint32_t irq_id = UART_IRQS(instance);
+
+    if (state == TRUE) {
+        /* register the IRQ sub-routine */
+        register_interrupt_routine(irq_id, irq_subroutine);
+        /* enable the IRQ */
+        enable_interrupt(irq_id, CPU_0, 0);
+    } else
+        /* disable the IRQ */
+        disable_interrupt(irq_id, CPU_0);
+}
+
+void uart_init(uint32_t instance, uint32_t baudrate, uint8_t parity,
+               uint8_t stopbits, uint8_t datasize, uint8_t flowcontrol)
+{
+    uint32_t base = REGS_UART_BASE(instance);
+
+   /* configure the I/O for the port */
+    uart_iomux_config(instance);
+
+    /* enable the source clocks to the UART port */
+    clock_gating_config(base, CLOCK_ON);
+
+    /* Wait for UART to finish transmitting before changing the configuration */
+    while (!(HW_UART_UTS(instance).B.TXEMPTY)) ;
+
+    /* Disable UART */
+    HW_UART_UCR1_CLR(instance,BM_UART_UCR1_UARTEN );
+
+    /* Configure FIFOs trigger level to half-full and half-empty */
+    HW_UART_UFCR_WR(instance, BF_UART_UFCR_RXTL(16) | UART_UFCR_RFDIV | BF_UART_UFCR_TXTL(16)); 
+
+    /* Setup One Millisecond timer */
+    HW_UART_ONEMS_WR(instance, uart_get_reffreq(instance) / 1000);
+
+    /* Set parity */
+    if (parity == PARITY_NONE)
+        HW_UART_UCR2_CLR(instance,(BM_UART_UCR2_PREN| BM_UART_UCR2_PROE)); 
+    else if (parity == PARITY_ODD)
+        HW_UART_UCR2_SET(instance,(BM_UART_UCR2_PREN| BM_UART_UCR2_PROE));
+    else {                      /* parity == PARITY_EVEN */
+        HW_UART_UCR2_SET(instance, BM_UART_UCR2_PREN);
+        HW_UART_UCR2_CLR(instance, BM_UART_UCR2_PROE);
+    }
+
+    /* Set stop bit */
+    if (stopbits == STOPBITS_ONE)
+        HW_UART_UCR2_CLR(instance, BM_UART_UCR2_STPB);
+    else                        /* stopbits == STOPBITS_TWO */
+        HW_UART_UCR2_SET(instance, BM_UART_UCR2_STPB);
+
+    /* Set data size */
+    if (datasize == EIGHTBITS)
+        HW_UART_UCR2_SET(instance, BM_UART_UCR2_WS);
+    else                        /* stopbits == STOPBITS_TWO */
+        HW_UART_UCR2_CLR(instance, BM_UART_UCR2_WS);
+
+    /* Configure the flow control */
+    if (flowcontrol == FLOWCTRL_ON) {
+        /* transmit done when RTS asserted */
+        HW_UART_UCR2_CLR(instance, BM_UART_UCR2_IRTS );
+        /* CTS controlled by the receiver */
+        HW_UART_UCR2_SET(instance, BM_UART_UCR2_CTSC );
+    } else {                    /* flowcontrol == FLOWCTRL_OFF */
+        /* Ignore RTS */
+        HW_UART_UCR2_SET(instance,  BM_UART_UCR2_IRTS);
+        /* CTS controlled by the CTS bit */
+        HW_UART_UCR2_CLR(instance,  BM_UART_UCR2_CTSC);
+    }
+
+    /* the reference manual says that this bit must always be set */
+    HW_UART_UCR3_SET(instance,  BM_UART_UCR3_RXDMUXSEL);
+
+    /* Enable UART */
+    HW_UART_UCR1_SET(instance, BM_UART_UCR1_UARTEN);
+
+    /* Enable FIFOs and does software reset to clear status flags, reset
+       the transmit and receive state machine, and reset the FIFOs */
+    HW_UART_UCR2_SET(instance, BM_UART_UCR2_TXEN | BM_UART_UCR2_RXEN | BM_UART_UCR2_SRST);
+
+    /* Set the numerator value minus one of the BRM ratio */
+    HW_UART_UBIR_WR(instance, (baudrate / 100) - 1);
+
+    /* Set the denominator value minus one of the BRM ratio */
+    HW_UART_UBMR_WR(instance,  ((uart_get_reffreq(instance) / 1600) - 1));
+
+    /* Optional: prevent the UART to enter debug state. Useful when debugging
+       the code with a JTAG and without active IRQ */
+    HW_UART_UTS_SET(instance, BM_UART_UTS_DBGEN);
+}
+

bsp/imx6ul/platform/include/epit.h

+/*
+ * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+//! @addtogroup diag_epit
+//! @{
+
+/*!
+ * @file epit.h
+ * @brief EPIT driver public interface.
+ */
+
+#ifndef __EPIT_H__
+#define __EPIT_H__
+
+#include "imx_timer.h"
+#include "sdk.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Free running reload mode.
+//!
+//! When the counter reaches zero it rolls over to 0xFFFF_FFFF.
+#define FREE_RUNNING    0
+
+//! @brief Set and forget reload mode.
+//!
+//! When the counter reaches zero it reloads from the modulus register.
+#define SET_AND_FORGET  1
+
+//! @brief Pass to epit_counter_enable() to enable interrupts.
+#define IRQ_MODE 1
+
+//! @brief Get the irq id of RPIT by instance number.
+//! @param x I2C instance number, from 1 through 2.
+#define EPIT_IRQS(x) ( (x) == HW_EPIT1 ? IMX_INT_EPIT1 : (x) == HW_EPIT2 ? IMX_INT_EPIT2 : 0xFFFFFFFF)
+
+////////////////////////////////////////////////////////////////////////////////
+// API
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initialize the EPIT timer.
+ *
+ * @param   instance the EPIT instance number.
+ * @param   clock_src Source clock of the counter: CLKSRC_OFF, CLKSRC_IPG_CLK,
+ *                      CLKSRC_PER_CLK, CLKSRC_CKIL.
+ * @param   prescaler Prescaler of source clock from 1 to 4096.
+ * @param   reload_mode Counter reload mode: FREE_RUNNING or SET_AND_FORGET.
+ * @param   load_val Load value from where the counter start.
+ * @param   low_power_mode Low power during which the timer is enabled:
+ *                           WAIT_MODE_EN and/or STOP_MODE_EN.
+ */
+void epit_init(uint32_t instance, uint32_t clock_src, uint32_t prescaler,
+               uint32_t reload_mode, uint32_t load_val, uint32_t low_power_mode);
+
+/*!
+ * @brief Setup EPIT interrupt.
+ *
+ * It enables or disables the related HW module interrupt, and attached the related sub-routine
+ * into the vector table.
+ *
+ * @param   instance the EPIT instance number.
+ * @param   irq_subroutine the EPIT interrupt interrupt routine.
+ * @param   enableIt True to enable the interrupt, false to disable.
+ */
+void epit_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), bool enableIt);
+
+/*!
+ * @brief Enable the EPIT module. 
+ *
+ * Used typically when the epit_init is done, and other interrupt related settings are ready.
+ *
+ * In interrupt mode, when the interrupt fires you should call epit_get_compare_event() to
+ * clear the compare flag.
+ *
+ * @param   instance the EPIT instance number.
+ * @param   load_val Load value from where the counter starts.
+ * @param   irq_mode Interrupt mode: IRQ_MODE or POLLING_MODE.
+ */
+void epit_counter_enable(uint32_t instance, uint32_t load_val, uint32_t irq_mode);
+
+/*!
+ * @brief Disable the counter.
+ *
+ * It saves energy when not used.
+ *
+ * @param   instance the EPIT instance number.
+ */
+void epit_counter_disable(uint32_t instance);
+
+/*!
+ * @brief Get the output compare status flag and clear it if set.
+ * 
+ * This function can typically be used for polling method, but
+ * is also used to clear the status compare flag in IRQ mode.
+ *
+ * @param   instance the EPIT instance number.
+ * @return  Value of the compare event flag.
+ */
+uint32_t epit_get_compare_event(uint32_t instance);
+
+/*!
+ * @brief Set the output compare register.
+ * 
+ *
+ * @param   instance the EPIT instance number.
+ * @param   Value of the compare register.
+ */
+void epit_set_compare_event(uint32_t instance, uint32_t compare_val);
+
+/*!
+ * @brief Get the counter value.
+ * 
+ *
+ * @param   instance the EPIT instance number.
+ * @return  Value of the counter register.
+ */
+uint32_t epit_get_counter_value(uint32_t instance);
+
+/*!
+ * @brief Reload the counter with a known value.
+ *
+ * @param instance the EPIT instance number.
+ * @param load_val Value loaded into the timer counter.
+ */
+void epit_reload_counter(uint32_t instance, uint32_t load_val);
+
+#if defined(__cplusplus)
+}
+#endif
+
+//! @}
+
+#endif //__EPIT_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/include/imx_timer.h

+/*
+ * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+//! @addtogroup diag_timer
+//! @{
+
+/*!
+ * @file timer.h
+ * @brief various defines used by the timer driver.
+ */
+
+#ifndef __TIMER_H__
+#define __TIMER_H__
+
+#include "sdk.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Constants
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Options for low power mode support for the timers.
+//!
+//! These constants are bit masks that are or'd together to select in which low
+//! power modes the timer will continue counting.
+enum _timer_low_power_modes
+{
+    WAIT_MODE_EN = 1,   //!< Timer is enabled in wait mode.
+    STOP_MODE_EN = 2    //!< Timer is enabled in stop mode.
+};
+
+//! @brief Available clock sources for the timers.
+enum _timer_clock_sources
+{
+    CLKSRC_OFF = 0,     //!< clock source is OFF
+    CLKSRC_IPG_CLK = 1, //!< clock source is peripheral clock
+    CLKSRC_PER_CLK = 2, //!< clock source is high-freq reference clock
+    CLKSRC_CLKIN = 3,   //!< clock source is external from a CLKIN input
+    CLKSRC_CKIL = 3     //!< clock source is low-freq reference clock
+};
+
+//! @brief Do not enable interrupts.
+#define POLLING_MODE 0
+
+////////////////////////////////////////////////////////////////////////////////
+// Externs
+////////////////////////////////////////////////////////////////////////////////
+extern uint32_t g_system_timer_port;
+
+////////////////////////////////////////////////////////////////////////////////
+// API
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+//! @brief Delay for a given number of microseconds.
+//!
+//! system_time_init() must have been called before using this function.
+//!
+//! @param usecs Delay in microseconds.
+void hal_delay_us(uint32_t usecs);
+
+//! @brief Init system timer facilities.
+//!
+//! Inits the EPIT timer used for delay, and inits the microsecond counter.
+void system_time_init(void);
+
+//! @brief Return the current microsecond counter value.
+//!
+//! @return The number of microseconds elapsed since system_time_init()
+//!     was called. This value may roll over before reaching all ones.
+uint64_t time_get_microseconds();
+
+#if defined(__cplusplus)
+}
+#endif
+
+//! @}
+
+#endif // __TIMER_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/include/mx6ul/iomux_register.h

+#ifndef _IOMUX_REGISTER_H_
+#define _IOMUX_REGISTER_H_
+#include "imx6ul-pinfunc.h"
+#endif
+

libcpu/arm/cortex-a/cp15.h

+#ifndef __CP15_H__
+#define __CP15_H__
+
+unsigned long rt_cpu_get_smp_id(void);
+
+void rt_cpu_mmu_disable(void);
+void rt_cpu_mmu_enable(void);
+void rt_cpu_tlb_set(volatile unsigned long*);
+
+void rt_cpu_vector_set_base(unsigned int addr);
+
+#endif

libcpu/arm/cortex-a/pmu.c

+#include <rtthread.h>
+#include "pmu.h"
+
+void rt_hw_pmu_dump_feature(void)
+{
+    unsigned long reg;
+
+    reg = rt_hw_pmu_get_control();
+    rt_kprintf("ARM PMU Implementor: %c, ID code: %02x, %d counters\n",
+               reg >> 24, (reg >> 16) & 0xff, (reg >> 11) & 0x1f);
+    RT_ASSERT(ARM_PMU_CNTER_NR == ((reg >> 11) & 0x1f));
+}