[libcpu][arm] Fix compilation warning

libcpu/arm/cortex-m33/trustzone.c

@@ -31,38 +31,6 @@ extern int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2);
 
 rt_ubase_t rt_trustzone_current_context;
 
-#if defined(__CC_ARM)
-static __inline rt_uint32_t __get_IPSR(void)
-{
-  register rt_uint32_t result          __asm("ipsr");
-  return(result);
-}
-#elif defined(__clang__)
-__attribute__((always_inline)) static __inline rt_uint32_t __get_IPSR(void)
-{
-    rt_uint32_t result;
-
-    __asm volatile ("MRS %0, ipsr" : "=r" (result) );
-    return(result);
-}
-#elif defined(__IAR_SYSTEMS_ICC__)
-_Pragma("inline=forced") static inline int __get_IPSR(int value)
-{
-    rt_uint32_t result;
-
-    asm("MRS  %0, ipsr" : "=r"(result));
-    return result;
-}
-#elif defined(__GNUC__)
-__attribute__((always_inline)) static inline rt_uint32_t __get_IPSR(void)
-{
-  rt_uint32_t result;
-
-  __asm volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-#endif
-
 void rt_trustzone_init(void)
 {
     static rt_uint8_t _init;
@@ -101,7 +69,6 @@ void rt_trustzone_context_load(rt_ubase_t context)
 
 int rt_secure_svc_handle(int svc_id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2)
 {
-    rt_ubase_t tmp;
     int res = 0;
 
     switch (svc_id)