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体验新版 GitCode，发现更多精彩内容 >>
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9e172489
编写于
5月 09, 2021
作者:
B
Bernard Xiong
提交者：
GitHub
5月 09, 2021
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差异文件
Merge pull request #4668 from Guozhanxin/arch_mix
[bsp]add seeed Arch_Mix bsp
上级
186466ec
7ab2cae3
变更
29
展开全部
隐藏空白更改
内联
并排
Showing
29 changed file
with
5044 addition
and
2 deletion
+5044
-2
bsp/imxrt/imxrt1052-seeed-ArchMix/.config
bsp/imxrt/imxrt1052-seeed-ArchMix/.config
+562
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/Kconfig
bsp/imxrt/imxrt1052-seeed-ArchMix/Kconfig
+16
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/README.md
bsp/imxrt/imxrt1052-seeed-ArchMix/README.md
+76
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/SConscript
bsp/imxrt/imxrt1052-seeed-ArchMix/SConscript
+14
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/SConstruct
bsp/imxrt/imxrt1052-seeed-ArchMix/SConstruct
+71
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/applications/SConscript
bsp/imxrt/imxrt1052-seeed-ArchMix/applications/SConscript
+16
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/applications/main.c
bsp/imxrt/imxrt1052-seeed-ArchMix/applications/main.c
+31
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/board/Kconfig
bsp/imxrt/imxrt1052-seeed-ArchMix/board/Kconfig
+122
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/board/MCUX_Config/MCUX_Config.mex
...imxrt1052-seeed-ArchMix/board/MCUX_Config/MCUX_Config.mex
+746
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/board/MCUX_Config/clock_config.c
.../imxrt1052-seeed-ArchMix/board/MCUX_Config/clock_config.c
+464
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/board/MCUX_Config/clock_config.h
.../imxrt1052-seeed-ArchMix/board/MCUX_Config/clock_config.h
+66
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/board/MCUX_Config/pin_mux.c
...imxrt/imxrt1052-seeed-ArchMix/board/MCUX_Config/pin_mux.c
+81
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/board/MCUX_Config/pin_mux.h
...imxrt/imxrt1052-seeed-ArchMix/board/MCUX_Config/pin_mux.h
+182
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/board/MIMXRT105x_QuadSPI_4KB_SEC.FLM
...rt1052-seeed-ArchMix/board/MIMXRT105x_QuadSPI_4KB_SEC.FLM
+0
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/board/SConscript
bsp/imxrt/imxrt1052-seeed-ArchMix/board/SConscript
+20
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/board/board.c
bsp/imxrt/imxrt1052-seeed-ArchMix/board/board.c
+138
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/board/board.h
bsp/imxrt/imxrt1052-seeed-ArchMix/board/board.h
+42
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.icf
...xrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.icf
+95
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.lds
...xrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.lds
+276
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.sct
...xrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.sct
+112
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/board/ports/sdram_port.h
bsp/imxrt/imxrt1052-seeed-ArchMix/board/ports/sdram_port.h
+49
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/figures/Arch_Mix.jpg
bsp/imxrt/imxrt1052-seeed-ArchMix/figures/Arch_Mix.jpg
+0
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/project.uvoptx
bsp/imxrt/imxrt1052-seeed-ArchMix/project.uvoptx
+189
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/project.uvprojx
bsp/imxrt/imxrt1052-seeed-ArchMix/project.uvprojx
+755
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/rtconfig.h
bsp/imxrt/imxrt1052-seeed-ArchMix/rtconfig.h
+177
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/rtconfig.py
bsp/imxrt/imxrt1052-seeed-ArchMix/rtconfig.py
+162
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/template.uvoptx
bsp/imxrt/imxrt1052-seeed-ArchMix/template.uvoptx
+189
-0
bsp/imxrt/imxrt1052-seeed-ArchMix/template.uvprojx
bsp/imxrt/imxrt1052-seeed-ArchMix/template.uvprojx
+391
-0
bsp/imxrt/libraries/MIMXRT1050/SConscript
bsp/imxrt/libraries/MIMXRT1050/SConscript
+2
-2
未找到文件。
bsp/imxrt/imxrt1052-seeed-ArchMix/.config
0 → 100644
浏览文件 @
9e172489
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX
=
8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE
=
4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32
=
y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX
=
32
CONFIG_RT_TICK_PER_SECOND
=
1000
CONFIG_RT_USING_OVERFLOW_CHECK
=
y
CONFIG_RT_USING_HOOK
=
y
CONFIG_RT_USING_IDLE_HOOK
=
y
CONFIG_RT_IDLE_HOOK_LIST_SIZE
=
4
CONFIG_IDLE_THREAD_STACK_SIZE
=
256
# CONFIG_RT_USING_TIMER_SOFT is not set
#
# kservice optimization
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
CONFIG_RT_DEBUG
=
y
CONFIG_RT_DEBUG_COLOR
=
y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE
=
y
CONFIG_RT_USING_MUTEX
=
y
CONFIG_RT_USING_EVENT
=
y
CONFIG_RT_USING_MAILBOX
=
y
CONFIG_RT_USING_MESSAGEQUEUE
=
y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL
=
y
CONFIG_RT_USING_MEMHEAP
=
y
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_SMALL_MEM is not set
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_USING_MEMHEAP_AS_HEAP
=
y
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP
=
y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE
=
y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE
=
y
CONFIG_RT_CONSOLEBUF_SIZE
=
128
CONFIG_RT_CONSOLE_DEVICE_NAME
=
"uart1"
CONFIG_RT_VER_NUM
=
0
x40003
# CONFIG_RT_USING_CPU_FFS is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT
=
y
CONFIG_RT_USING_USER_MAIN
=
y
CONFIG_RT_MAIN_THREAD_STACK_SIZE
=
2048
CONFIG_RT_MAIN_THREAD_PRIORITY
=
10
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH
=
y
CONFIG_FINSH_THREAD_NAME
=
"tshell"
CONFIG_FINSH_USING_HISTORY
=
y
CONFIG_FINSH_HISTORY_LINES
=
5
CONFIG_FINSH_USING_SYMTAB
=
y
CONFIG_FINSH_USING_DESCRIPTION
=
y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY
=
20
CONFIG_FINSH_THREAD_STACK_SIZE
=
4096
CONFIG_FINSH_CMD_SIZE
=
80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH
=
y
CONFIG_FINSH_USING_MSH_DEFAULT
=
y
CONFIG_FINSH_USING_MSH_ONLY
=
y
CONFIG_FINSH_ARG_MAX
=
10
#
# Device virtual file system
#
# CONFIG_RT_USING_DFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC
=
y
CONFIG_RT_PIPE_BUFSZ
=
512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL
=
y
CONFIG_RT_SERIAL_USING_DMA
=
y
CONFIG_RT_SERIAL_RB_BUFSZ
=
64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN
=
y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
# CONFIG__RT_USB_DEVICE_NONE is not set
# CONFIG__RT_USB_DEVICE_CDC is not set
# CONFIG__RT_USB_DEVICE_MSTORAGE is not set
# CONFIG__RT_USB_DEVICE_HID is not set
# CONFIG__RT_USB_DEVICE_WINUSB is not set
# CONFIG__RT_USB_DEVICE_AUDIO is not set
#
# POSIX layer and C standard library
#
# CONFIG_RT_USING_LIBC is not set
# CONFIG_RT_USING_PTHREADS is not set
CONFIG_RT_LIBC_USING_TIME
=
y
CONFIG_RT_LIBC_FIXED_TIMEZONE
=
8
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_AGILE_MODBUS is not set
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_PDFGEN is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
# CONFIG_PKG_USING_NUEMWIN is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_MEMORYPERF is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
# CONFIG_PKG_USING_LWLOG is not set
# CONFIG_PKG_USING_ANV_TRACE is not set
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
# CONFIG_PKG_USING_DEVMEM is not set
# CONFIG_PKG_USING_REGEX is not set
# CONFIG_PKG_USING_MEM_SANDBOX is not set
# CONFIG_PKG_USING_SOLAR_TERMS is not set
# CONFIG_PKG_USING_GAN_ZHI is not set
#
# system packages
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
# CONFIG_PKG_USING_DFS_UFFS is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
# CONFIG_PKG_USING_TMC51XX is not set
# CONFIG_PKG_USING_TCA9534 is not set
#
# AI packages
#
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
#
# entertainment: terminal games and other interesting software packages
#
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_ACLOCK is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_COWSAY is not set
#
# Hardware Drivers Config
#
CONFIG_SOC_IMXRT1052CVL5B
=
y
#
# Onboard Peripheral Drivers
#
# CONFIG_BSP_USING_SDRAM is not set
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_DMA
=
y
CONFIG_BSP_USING_GPIO
=
y
CONFIG_BSP_USING_LPUART
=
y
CONFIG_BSP_USING_LPUART1
=
y
# CONFIG_BSP_LPUART1_RX_USING_DMA is not set
# CONFIG_BSP_LPUART1_TX_USING_DMA is not set
# CONFIG_BSP_USING_LPUART4 is not set
# CONFIG_BSP_USING_SPI is not set
bsp/imxrt/imxrt1052-seeed-ArchMix/Kconfig
0 → 100644
浏览文件 @
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mainmenu "RT-Thread Configuration"
config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "../libraries/Kconfig"
source "board/Kconfig"
bsp/imxrt/imxrt1052-seeed-ArchMix/README.md
0 → 100644
浏览文件 @
9e172489
# Seeed i.MX RT1052 Arch Mix 开发板 BSP 说明
## 简介
Arch Mix 是
[
Seeed Studio
](
https://www.seeedstudio.com/
)
推出的一款基于 i.MX RT 1050 系列芯片的开发板，板载一颗 RGB 灯和一个用户按键，外扩 32M SDRAM，板载资源丰富，运行速度快（主频可达 600MHZ），并且支持外接 LCD 屏幕。Seeed Studio 是一家致力于促进开源硬件发展的服务型企业。目前，已经与众多设计者建立了紧密的合作关系，并且合作推出了涉及新媒体艺术、嵌入式平台、物联网、智能家居、便携式仪器等领域的一系列明星产品和方案。
### 板载资源：
| 硬件 | 描述 |
| ---- | ---- |
| 芯片 | i.MX RT 1052 |
| 架构 | ARM Cortex-M7 |
| 最高频率 | 600MHz |
| 内部存储器 | 512KB SRAM |
| 外部存储器 | 32M SDRAM、8M QSPI FLASH（存储代码） |
## 编译说明
Arch Mix 板级包支持MDK5﹑IAR开发环境和GCC编译器，以下是具体版本信息：
| IDE/编译器 | 已测试版本 |
| ---------- | --------- |
| MDK5 | MDK525 |
| IAR | IAR 8.11.3.13984 |
| GCC | GCC 5.4.1 20160919 (release) |
## BSP使用
### 配置工程
-
在 bsp 下打开 env 工具
-
输入
`menuconfig`
命令配置工程，配置好之后保存退出。
-
输入
`scons --target=mdk5 -s`
或
`scons --target=iar`
来生成需要的工程
### 下载和仿真
开发板支持 SWD 调试接口，连接外置仿真器后，就可以进行下载和仿真。
> 注意：下载算法默认使用 board目录下的 MIMXRT105x_QuadSPI_4KB_SEC.FLM 文件，将此文件拷贝到 Keil5安装目录下 `ARM\Flash` 目录下即可。
>
> 下载失败时：先按下 `Reset 按键`，再按下 `Boot Mode 按键`，先松开 `Reset 按键`，再松开 `Boot Mode 按键`，即可进入`下载模式`。
### 运行结果
下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，绿色 DS1 会周期性闪烁。
使用 TTL 转串口工具连接开发板上 RXD/TXD ，在终端工具里打开相应的串口(115200-N-8-1)。如果编译 & 烧写无误，当复位设备后，可以看到RT-Thread的输出信息:
```
\ | /
- RT - Thread Operating System
/ | \ 4.0.3 build May 7 2021
2006 - 2021 Copyright by rt-thread team
msh >
```
## 驱动支持情况及计划
| 驱动 | 支持情况 | 备注 |
| ------ | ---- | ------ |
| UART | 支持 | UART 1 |
| GPIO | 支持 | GPIO1~GPIO5 |
| IIC | 暂不支持 | |
| SPI | 暂不支持 | |
| LCD | 暂不支持 | |
| RTC | 暂不支持 | |
| SDIO | 暂不支持 | |
| SDRAM | 支持 | 32M SDRAM，后面 2M 作为 Non Cache 区域 |
## 联系人信息
维护人：
-
[
guozhanxin
](
https://github.com/Guozhanxin
)
bsp/imxrt/imxrt1052-seeed-ArchMix/SConscript
0 → 100644
浏览文件 @
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# for module compiling
import
os
from
building
import
*
cwd
=
GetCurrentDir
()
objs
=
[]
list
=
os
.
listdir
(
cwd
)
for
d
in
list
:
path
=
os
.
path
.
join
(
cwd
,
d
)
if
os
.
path
.
isfile
(
os
.
path
.
join
(
path
,
'SConscript'
)):
objs
=
objs
+
SConscript
(
os
.
path
.
join
(
d
,
'SConscript'
))
Return
(
'objs'
)
bsp/imxrt/imxrt1052-seeed-ArchMix/SConstruct
0 → 100644
浏览文件 @
9e172489
import
os
import
sys
import
rtconfig
if
os
.
getenv
(
'RTT_ROOT'
):
RTT_ROOT
=
os
.
getenv
(
'RTT_ROOT'
)
else
:
RTT_ROOT
=
os
.
path
.
normpath
(
os
.
getcwd
()
+
'/../../..'
)
sys
.
path
=
sys
.
path
+
[
os
.
path
.
join
(
RTT_ROOT
,
'tools'
)]
try
:
from
building
import
*
except
:
print
(
'Cannot found RT-Thread root directory, please check RTT_ROOT'
)
print
(
RTT_ROOT
)
exit
(
-
1
)
TARGET
=
'rtthread.'
+
rtconfig
.
TARGET_EXT
DefaultEnvironment
(
tools
=
[])
if
rtconfig
.
PLATFORM
==
'armcc'
:
env
=
Environment
(
tools
=
[
'mingw'
],
AS
=
rtconfig
.
AS
,
ASFLAGS
=
rtconfig
.
AFLAGS
,
CC
=
rtconfig
.
CC
,
CCFLAGS
=
rtconfig
.
CFLAGS
,
CXX
=
rtconfig
.
CXX
,
CXXFLAGS
=
rtconfig
.
CXXFLAGS
,
AR
=
rtconfig
.
AR
,
ARFLAGS
=
'-rc'
,
LINK
=
rtconfig
.
LINK
,
LINKFLAGS
=
rtconfig
.
LFLAGS
,
# overwrite cflags, because cflags has '--C99'
CXXCOM
=
'$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES'
)
else
:
env
=
Environment
(
tools
=
[
'mingw'
],
AS
=
rtconfig
.
AS
,
ASFLAGS
=
rtconfig
.
AFLAGS
,
CC
=
rtconfig
.
CC
,
CCFLAGS
=
rtconfig
.
CFLAGS
,
CXX
=
rtconfig
.
CXX
,
CXXFLAGS
=
rtconfig
.
CXXFLAGS
,
AR
=
rtconfig
.
AR
,
ARFLAGS
=
'-rc'
,
LINK
=
rtconfig
.
LINK
,
LINKFLAGS
=
rtconfig
.
LFLAGS
,
CXXCOM
=
'$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES'
)
env
.
PrependENVPath
(
'PATH'
,
rtconfig
.
EXEC_PATH
)
if
rtconfig
.
PLATFORM
==
'iar'
:
env
.
Replace
(
CCCOM
=
[
'$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'
])
env
.
Replace
(
ARFLAGS
=
[
''
])
env
.
Replace
(
LINKCOM
=
env
[
"LINKCOM"
]
+
' --map rtthread.map'
)
Export
(
'RTT_ROOT'
)
Export
(
'rtconfig'
)
SDK_ROOT
=
os
.
path
.
abspath
(
'./'
)
if
os
.
path
.
exists
(
SDK_ROOT
+
'/libraries'
):
libraries_path_prefix
=
SDK_ROOT
+
'/libraries'
else
:
libraries_path_prefix
=
os
.
path
.
dirname
(
SDK_ROOT
)
+
'/libraries'
SDK_LIB
=
libraries_path_prefix
Export
(
'SDK_LIB'
)
# prepare building environment
objs
=
PrepareBuilding
(
env
,
RTT_ROOT
,
has_libcpu
=
False
)
imxrt_library
=
'MIMXRT1050'
rtconfig
.
BSP_LIBRARY_TYPE
=
imxrt_library
# include libraries
objs
.
extend
(
SConscript
(
os
.
path
.
join
(
libraries_path_prefix
,
imxrt_library
,
'SConscript'
)))
# include drivers
objs
.
extend
(
SConscript
(
os
.
path
.
join
(
libraries_path_prefix
,
'drivers'
,
'SConscript'
)))
# make a building
DoBuilding
(
TARGET
,
objs
)
bsp/imxrt/imxrt1052-seeed-ArchMix/applications/SConscript
0 → 100644
浏览文件 @
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import
rtconfig
from
building
import
*
cwd
=
GetCurrentDir
()
src
=
Glob
(
'*.c'
)
CPPPATH
=
[
cwd
]
# add for startup script
if
rtconfig
.
CROSS_TOOL
==
'gcc'
:
CPPDEFINES
=
[
'__START=entry'
]
else
:
CPPDEFINES
=
[]
group
=
DefineGroup
(
'Applications'
,
src
,
depend
=
[
''
],
CPPPATH
=
CPPPATH
,
CPPDEFINES
=
CPPDEFINES
)
Return
(
'group'
)
bsp/imxrt/imxrt1052-seeed-ArchMix/applications/main.c
0 → 100644
浏览文件 @
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-10-10 Tanek first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "drv_gpio.h"
/* USER_LED_G,GPIO_IO01,GPIO_AD_B0_10 */
#define LED0_PIN GET_PIN(1,10)
int
main
(
void
)
{
/* set LED0 pin mode to output */
rt_pin_mode
(
LED0_PIN
,
PIN_MODE_OUTPUT
);
while
(
1
)
{
rt_pin_write
(
LED0_PIN
,
PIN_HIGH
);
rt_thread_mdelay
(
500
);
rt_pin_write
(
LED0_PIN
,
PIN_LOW
);
rt_thread_mdelay
(
500
);
}
}
bsp/imxrt/imxrt1052-seeed-ArchMix/board/Kconfig
0 → 100644
浏览文件 @
9e172489
menu "Hardware Drivers Config"
config SOC_IMXRT1052CVL5B
bool
select SOC_MIMXRT1050_SERIES
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
menu "Onboard Peripheral Drivers"
config BSP_USING_SDRAM
bool "Enable SDRAM"
default n
endmenu
menu "On-chip Peripheral Drivers"
config BSP_USING_DMA
bool "Enable DMA"
default n
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_LPUART
bool "Enable UART"
select RT_USING_SERIAL
default y
if BSP_USING_LPUART
config BSP_USING_LPUART1
bool "Enable LPUART1"
default y
config BSP_LPUART1_RX_USING_DMA
bool "Enable LPUART1 RX DMA"
depends on BSP_USING_LPUART1
select BSP_USING_DMA
select RT_SERIAL_USING_DMA
default n
config BSP_LPUART1_RX_DMA_CHANNEL
depends on BSP_LPUART1_RX_USING_DMA
int "Set LPUART1 RX DMA channel (0-32)"
default 0
config BSP_LPUART1_TX_USING_DMA
bool "Enable LPUART1 TX DMA"
depends on BSP_USING_LPUART1
select BSP_USING_DMA
select RT_SERIAL_USING_DMA
default n
config BSP_LPUART1_TX_DMA_CHANNEL
depends on BSP_LPUART1_TX_USING_DMA
int "Set LPUART1 TX DMA channel (0-32)"
default 1
config BSP_USING_LPUART4
bool "Enable LPUART4"
default n
config BSP_LPUART4_RX_USING_DMA
bool "Enable LPUART4 RX DMA"
depends on BSP_USING_LPUART4
select BSP_USING_DMA
select RT_SERIAL_USING_DMA
default n
config BSP_LPUART4_RX_DMA_CHANNEL
depends on BSP_LPUART4_RX_USING_DMA
int "Set LPUART4 RX DMA channel (0-32)"
default 2
config BSP_LPUART4_TX_USING_DMA
bool "Enable LPUART4 TX DMA"
depends on BSP_USING_LPUART4
select BSP_USING_DMA
select RT_SERIAL_USING_DMA
default n
config BSP_LPUART4_TX_DMA_CHANNEL
depends on BSP_LPUART4_TX_USING_DMA
int "Set LPUART4 TX DMA channel (0-32)"
default 3
endif
menuconfig BSP_USING_SPI
bool "Enable SPI"
select RT_USING_SPI
select RT_USING_PIN
default n
if BSP_USING_SPI
config BSP_USING_SPI3
bool "Enable SPI3"
default n
config BSP_SPI3_USING_DMA
bool "Enable SPI3 DMA xfer"
depends on BSP_USING_SPI3
select BSP_USING_DMA
default n
config BSP_SPI3_RX_DMA_CHANNEL
depends on BSP_SPI3_USING_DMA
int "Set SPI3 RX DMA channel (0-32)"
default 4
config BSP_SPI3_TX_DMA_CHANNEL
depends on BSP_SPI3_USING_DMA
int "Set SPI3 TX DMA channel (0-32)"
default 5
endif
endmenu
endmenu
bsp/imxrt/imxrt1052-seeed-ArchMix/board/MCUX_Config/MCUX_Config.mex
0 → 100644
浏览文件 @
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此差异已折叠。
点击以展开。
bsp/imxrt/imxrt1052-seeed-ArchMix/board/MCUX_Config/clock_config.c
0 → 100644
浏览文件 @
9e172489
此差异已折叠。
点击以展开。
bsp/imxrt/imxrt1052-seeed-ArchMix/board/MCUX_Config/clock_config.h
0 → 100644
浏览文件 @
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#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 24000000U
/*!< Board xtal0 frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U
/*!< Board xtal32k frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern
"C"
{
#endif
/* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void
BOARD_InitBootClocks
(
void
);
#if defined(__cplusplus)
}
#endif
/* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U
/*!< Core clock frequency: 600000000Hz */
/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
*/
extern
const
clock_arm_pll_config_t
armPllConfig_BOARD_BootClockRUN
;
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
*/
extern
const
clock_usb_pll_config_t
usb1PllConfig_BOARD_BootClockRUN
;
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
*/
extern
const
clock_sys_pll_config_t
sysPllConfig_BOARD_BootClockRUN
;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern
"C"
{
#endif
/* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void
BOARD_BootClockRUN
(
void
);
#if defined(__cplusplus)
}
#endif
/* __cplusplus*/
#endif
/* _CLOCK_CONFIG_H_ */
bsp/imxrt/imxrt1052-seeed-ArchMix/board/MCUX_Config/pin_mux.c
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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v5.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
processor_version: 5.0.2
board: IMXRT1050-EVKB
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
#include "fsl_common.h"
#include "fsl_iomuxc.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void
BOARD_InitBootPins
(
void
)
{
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13}
- {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12}
- {pin_num: M14, peripheral: LPSPI3, signal: SCK, pin_signal: GPIO_AD_B0_00}
- {pin_num: M11, peripheral: LPSPI3, signal: SDI, pin_signal: GPIO_AD_B0_02}
- {pin_num: H10, peripheral: LPSPI3, signal: SDO, pin_signal: GPIO_AD_B0_01}
- {pin_num: M5, peripheral: LPUART4, signal: RX, pin_signal: GPIO_SD_B1_01}
- {pin_num: L5, peripheral: LPUART4, signal: TX, pin_signal: GPIO_SD_B1_00}
- {pin_num: F11, peripheral: GPIO1, signal: 'gpio_io, 04', pin_signal: GPIO_AD_B0_04}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void
BOARD_InitPins
(
void
)
{
CLOCK_EnableClock
(
kCLOCK_Iomuxc
);
/* iomuxc clock (iomuxc_clk_enable): 0x03U */
IOMUXC_SetPinMux
(
IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK
,
/* GPIO_AD_B0_00 is configured as LPSPI3_SCK */
0U
);
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux
(
IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO
,
/* GPIO_AD_B0_01 is configured as LPSPI3_SDO */
0U
);
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux
(
IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI
,
/* GPIO_AD_B0_02 is configured as LPSPI3_SDI */
0U
);
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux
(
IOMUXC_GPIO_AD_B0_12_LPUART1_TX
,
/* GPIO_AD_B0_12 is configured as LPUART1_TX */
0U
);
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux
(
IOMUXC_GPIO_AD_B0_13_LPUART1_RX
,
/* GPIO_AD_B0_13 is configured as LPUART1_RX */
0U
);
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux
(
IOMUXC_GPIO_SD_B1_00_LPUART4_TX
,
/* GPIO_SD_B1_00 is configured as LPUART4_TX */
0U
);
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux
(
IOMUXC_GPIO_SD_B1_01_LPUART4_RX
,
/* GPIO_SD_B1_01 is configured as LPUART4_RX */
0U
);
/* Software Input On Field: Input Path is determined by functionality */
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/
bsp/imxrt/imxrt1052-seeed-ArchMix/board/MCUX_Config/pin_mux.h
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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/***********************************************************************************************************************
* Definitions
**********************************************************************************************************************/
/*! @brief Direction type */
typedef
enum
_pin_mux_direction
{
kPIN_MUX_DirectionInput
=
0U
,
/* Input direction */
kPIN_MUX_DirectionOutput
=
1U
,
/* Output direction */
kPIN_MUX_DirectionInputOrOutput
=
2U
/* Input or output direction */
}
pin_mux_direction_t
;
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern
"C"
{
#endif
/*!
* @brief Calls initialization functions.
*
*/
void
BOARD_InitBootPins
(
void
);
/* GPIO_AD_B0_13 (coord L14), UART1_RXD */
#define BOARD_INITPINS_UART1_RXD_PERIPHERAL LPUART1
/*!< Device name: LPUART1 */
#define BOARD_INITPINS_UART1_RXD_SIGNAL RX
/*!< LPUART1 signal: RX */
/* GPIO_AD_B0_12 (coord K14), UART1_TXD */
#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1
/*!< Device name: LPUART1 */
#define BOARD_INITPINS_UART1_TXD_SIGNAL TX
/*!< LPUART1 signal: TX */
/* GPIO_SD_B1_03 (coord M4), FlexSPI_D0_B */
#define BOARD_INITPINS_FlexSPI_D0_B_GPIO GPIO3
/*!< GPIO device name: GPIO3 */
#define BOARD_INITPINS_FlexSPI_D0_B_PORT GPIO3
/*!< PORT device name: GPIO3 */
#define BOARD_INITPINS_FlexSPI_D0_B_PIN 3U
/*!< GPIO3 pin index: 3 */
/* PMIC_ON_REQ (coord K7), PMIC_ON_REQ */
#define BOARD_INITPINS_PMIC_ON_REQ_GPIO GPIO5
/*!< GPIO device name: GPIO5 */
#define BOARD_INITPINS_PMIC_ON_REQ_PORT GPIO5
/*!< PORT device name: GPIO5 */
#define BOARD_INITPINS_PMIC_ON_REQ_PIN 1U
/*!< GPIO5 pin index: 1 */
/* GPIO_AD_B0_05 (coord G14), CAN_STBY/BOOT_MODE[1]/Flash_RST/U12[8] */
#define BOARD_INITPINS_CAN_STBY_GPIO GPIO1
/*!< GPIO device name: GPIO1 */
#define BOARD_INITPINS_CAN_STBY_PORT GPIO1
/*!< PORT device name: GPIO1 */
#define BOARD_INITPINS_CAN_STBY_PIN 5U
/*!< GPIO1 pin index: 5 */
/* GPIO_EMC_40 (coord A7), ENET_MDC */
#define BOARD_INITPINS_ENET_MDC_GPIO GPIO3
/*!< GPIO device name: GPIO3 */
#define BOARD_INITPINS_ENET_MDC_PORT GPIO3
/*!< PORT device name: GPIO3 */
#define BOARD_INITPINS_ENET_MDC_PIN 26U
/*!< GPIO3 pin index: 26 */
/* GPIO_B0_00 (coord D7), LCDIF_CLK */
#define BOARD_INITPINS_LCDIF_CLK_PERIPHERAL LCDIF
/*!< Device name: LCDIF */
#define BOARD_INITPINS_LCDIF_CLK_SIGNAL lcdif_clk
/*!< LCDIF signal: lcdif_clk */
/* GPIO_B0_04 (coord C8), LCDIF_D0/BT_CFG[0] */
#define BOARD_INITPINS_LCDIF_D0_PERIPHERAL LCDIF
/*!< Device name: LCDIF */
#define BOARD_INITPINS_LCDIF_D0_SIGNAL lcdif_data
/*!< LCDIF signal: lcdif_data */
#define BOARD_INITPINS_LCDIF_D0_CHANNEL 0U
/*!< LCDIF lcdif_data channel: 00 */
/* GPIO_B0_05 (coord B8), LCDIF_D1/BT_CFG[1] */
#define BOARD_INITPINS_LCDIF_D1_PERIPHERAL LCDIF
/*!< Device name: LCDIF */
#define BOARD_INITPINS_LCDIF_D1_SIGNAL lcdif_data
/*!< LCDIF signal: lcdif_data */
#define BOARD_INITPINS_LCDIF_D1_CHANNEL 1U
/*!< LCDIF lcdif_data channel: 01 */
/* GPIO_B0_06 (coord A8), LCDIF_D2/BT_CFG[2] */
#define BOARD_INITPINS_LCDIF_D2_PERIPHERAL LCDIF
/*!< Device name: LCDIF */
#define BOARD_INITPINS_LCDIF_D2_SIGNAL lcdif_data
/*!< LCDIF signal: lcdif_data */
#define BOARD_INITPINS_LCDIF_D2_CHANNEL 2U
/*!< LCDIF lcdif_data channel: 02 */
/* GPIO_B0_08 (coord B9), LCDIF_D4/BT_CFG[4] */
#define BOARD_INITPINS_LCDIF_D4_PERIPHERAL LCDIF
/*!< Device name: LCDIF */
#define BOARD_INITPINS_LCDIF_D4_SIGNAL lcdif_data
/*!< LCDIF signal: lcdif_data */
#define BOARD_INITPINS_LCDIF_D4_CHANNEL 4U
/*!< LCDIF lcdif_data channel: 04 */
/* GPIO_B0_07 (coord A9), LCDIF_D3/BT_CFG[3] */
#define BOARD_INITPINS_LCDIF_D3_PERIPHERAL LCDIF
/*!< Device name: LCDIF */
#define BOARD_INITPINS_LCDIF_D3_SIGNAL lcdif_data
/*!< LCDIF signal: lcdif_data */
#define BOARD_INITPINS_LCDIF_D3_CHANNEL 3U
/*!< LCDIF lcdif_data channel: 03 */
/* GPIO_B0_09 (coord C9), LCDIF_D5/BT_CFG[5] */
#define BOARD_INITPINS_LCDIF_D5_PERIPHERAL LCDIF
/*!< Device name: LCDIF */
#define BOARD_INITPINS_LCDIF_D5_SIGNAL lcdif_data
/*!< LCDIF signal: lcdif_data */
#define BOARD_INITPINS_LCDIF_D5_CHANNEL 5U
/*!< LCDIF lcdif_data channel: 05 */
/* GPIO_B0_10 (coord D9), LCDIF_D6/BT_CFG[6] */
#define BOARD_INITPINS_LCDIF_D6_PERIPHERAL LCDIF
/*!< Device name: LCDIF */
#define BOARD_INITPINS_LCDIF_D6_SIGNAL lcdif_data
/*!< LCDIF signal: lcdif_data */
#define BOARD_INITPINS_LCDIF_D6_CHANNEL 6U
/*!< LCDIF lcdif_data channel: 06 */
/* GPIO_B0_11 (coord A10), LCDIF_D7/BT_CFG[7] */
#define BOARD_INITPINS_LCDIF_D7_PERIPHERAL LCDIF
/*!< Device name: LCDIF */
#define BOARD_INITPINS_LCDIF_D7_SIGNAL lcdif_data
/*!< LCDIF signal: lcdif_data */
#define BOARD_INITPINS_LCDIF_D7_CHANNEL 7U
/*!< LCDIF lcdif_data channel: 07 */
/* GPIO_B0_12 (coord C10), LCDIF_D8/BT_CFG[8] */
#define BOARD_INITPINS_LCDIF_D8_PERIPHERAL LCDIF
/*!< Device name: LCDIF */
#define BOARD_INITPINS_LCDIF_D8_SIGNAL lcdif_data
/*!< LCDIF signal: lcdif_data */
#define BOARD_INITPINS_LCDIF_D8_CHANNEL 8U
/*!< LCDIF lcdif_data channel: 08 */
/* GPIO_B0_13 (coord D10), LCDIF_D9/BT_CFG[9] */
#define BOARD_INITPINS_LCDIF_D9_PERIPHERAL LCDIF
/*!< Device name: LCDIF */
#define BOARD_INITPINS_LCDIF_D9_SIGNAL lcdif_data
/*!< LCDIF signal: lcdif_data */
#define BOARD_INITPINS_LCDIF_D9_CHANNEL 9U
/*!< LCDIF lcdif_data channel: 09 */
/* GPIO_B0_14 (coord E10), LCDIF_D10/BT_CFG[10] */
#define BOARD_INITPINS_LCDIF_D10_PERIPHERAL LCDIF
/*!< Device name: LCDIF */
#define BOARD_INITPINS_LCDIF_D10_SIGNAL lcdif_data
/*!< LCDIF signal: lcdif_data */
#define BOARD_INITPINS_LCDIF_D10_CHANNEL 10U
/*!< LCDIF lcdif_data channel: 10 */
/* GPIO_B0_15 (coord E11), LCDIF_D11/BT_CFG[11] */
#define BOARD_INITPINS_LCDIF_D11_PERIPHERAL LCDIF
/*!< Device name: LCDIF */
#define BOARD_INITPINS_LCDIF_D11_SIGNAL lcdif_data
/*!< LCDIF signal: lcdif_data */
#define BOARD_INITPINS_LCDIF_D11_CHANNEL 11U
/*!< LCDIF lcdif_data channel: 11 */
/* GPIO_B1_00 (coord A11), LCDIF_D12 */
#define BOARD_INITPINS_LCDIF_D12_PERIPHERAL LCDIF
/*!< Device name: LCDIF */
#define BOARD_INITPINS_LCDIF_D12_SIGNAL lcdif_data
/*!< LCDIF signal: lcdif_data */
#define BOARD_INITPINS_LCDIF_D12_CHANNEL 12U
/*!< LCDIF lcdif_data channel: 12 */
/* GPIO_B1_01 (coord B11), LCDIF_D13 */
#define BOARD_INITPINS_LCDIF_D13_PERIPHERAL LCDIF
/*!< Device name: LCDIF */
#define BOARD_INITPINS_LCDIF_D13_SIGNAL lcdif_data
/*!< LCDIF signal: lcdif_data */
#define BOARD_INITPINS_LCDIF_D13_CHANNEL 13U
/*!< LCDIF lcdif_data channel: 13 */
/* GPIO_B1_02 (coord C11), LCDIF_D14 */
#define BOARD_INITPINS_LCDIF_D14_PERIPHERAL LCDIF
/*!< Device name: LCDIF */
#define BOARD_INITPINS_LCDIF_D14_SIGNAL lcdif_data
/*!< LCDIF signal: lcdif_data */
#define BOARD_INITPINS_LCDIF_D14_CHANNEL 14U
/*!< LCDIF lcdif_data channel: 14 */
/* GPIO_B1_03 (coord D11), LCDIF_D15 */
#define BOARD_INITPINS_LCDIF_D15_PERIPHERAL LCDIF
/*!< Device name: LCDIF */
#define BOARD_INITPINS_LCDIF_D15_SIGNAL lcdif_data
/*!< LCDIF signal: lcdif_data */
#define BOARD_INITPINS_LCDIF_D15_CHANNEL 15U
/*!< LCDIF lcdif_data channel: 15 */
/* GPIO_B0_01 (coord E7), LCDIF_ENABLE */
#define BOARD_INITPINS_LCDIF_ENABLE_PERIPHERAL LCDIF
/*!< Device name: LCDIF */
#define BOARD_INITPINS_LCDIF_ENABLE_SIGNAL lcdif_enable
/*!< LCDIF signal: lcdif_enable */
/* GPIO_B0_02 (coord E8), LCDIF_HSYNC */
#define BOARD_INITPINS_LCDIF_HSYNC_PERIPHERAL LCDIF
/*!< Device name: LCDIF */
#define BOARD_INITPINS_LCDIF_HSYNC_SIGNAL lcdif_hsync
/*!< LCDIF signal: lcdif_hsync */
/* GPIO_B0_03 (coord D8), LCDIF_VSYNC */
#define BOARD_INITPINS_LCDIF_VSYNC_PERIPHERAL LCDIF
/*!< Device name: LCDIF */
#define BOARD_INITPINS_LCDIF_VSYNC_SIGNAL lcdif_vsync
/*!< LCDIF signal: lcdif_vsync */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void
BOARD_InitPins
(
void
);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif
/* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/
bsp/imxrt/imxrt1052-seeed-ArchMix/board/MIMXRT105x_QuadSPI_4KB_SEC.FLM
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bsp/imxrt/imxrt1052-seeed-ArchMix/board/SConscript
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from
building
import
*
cwd
=
GetCurrentDir
()
# add the general drivers.
src
=
Split
(
"""
board.c
MCUX_Config/clock_config.c
MCUX_Config/pin_mux.c
"""
)
CPPPATH
=
[
cwd
,
cwd
+
'/MCUX_Config'
,
cwd
+
'/ports'
]
CPPDEFINES
=
[
'CPU_MIMXRT1052CVL5B'
,
'SKIP_SYSCLK_INIT'
,
'EVK_MCIMXRM'
,
'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1'
,
'XIP_EXTERNAL_FLASH=1'
]
if
GetDepend
([
'BSP_USING_SPI_FLASH'
]):
src
+=
Glob
(
'ports/spi_flash_init.c'
)
group
=
DefineGroup
(
'Drivers'
,
src
,
depend
=
[
''
],
CPPPATH
=
CPPPATH
,
CPPDEFINES
=
CPPDEFINES
)
Return
(
'group'
)
bsp/imxrt/imxrt1052-seeed-ArchMix/board/board.c
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard first implementation
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include "pin_mux.h"
#ifdef BSP_USING_DMA
#include "fsl_dmamux.h"
#include "fsl_edma.h"
#endif
#define NVIC_PRIORITYGROUP_0 0x00000007U
/*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 0x00000006U
/*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 0x00000005U
/*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 0x00000004U
/*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4 0x00000003U
/*!< 4 bits for pre-emption priority
0 bits for subpriority */
/* MPU configuration. */
static
void
BOARD_ConfigMPU
(
void
)
{
/* Disable I cache and D cache */
SCB_DisableICache
();
SCB_DisableDCache
();
/* Disable MPU */
ARM_MPU_Disable
();
/* Region 0 setting */
MPU
->
RBAR
=
ARM_MPU_RBAR
(
0
,
0xC0000000U
);
MPU
->
RASR
=
ARM_MPU_RASR
(
0
,
ARM_MPU_AP_FULL
,
2
,
0
,
0
,
0
,
0
,
ARM_MPU_REGION_SIZE_512MB
);
/* Region 1 setting */
MPU
->
RBAR
=
ARM_MPU_RBAR
(
1
,
0x80000000U
);
MPU
->
RASR
=
ARM_MPU_RASR
(
0
,
ARM_MPU_AP_FULL
,
2
,
0
,
0
,
0
,
0
,
ARM_MPU_REGION_SIZE_1GB
);
/* Region 2 setting */
// spi flash: normal type, cacheable, no bufferable, no shareable
MPU
->
RBAR
=
ARM_MPU_RBAR
(
2
,
0x60000000U
);
MPU
->
RASR
=
ARM_MPU_RASR
(
0
,
ARM_MPU_AP_FULL
,
0
,
0
,
1
,
0
,
0
,
ARM_MPU_REGION_SIZE_512MB
);
/* Region 3 setting */
MPU
->
RBAR
=
ARM_MPU_RBAR
(
3
,
0x00000000U
);
MPU
->
RASR
=
ARM_MPU_RASR
(
0
,
ARM_MPU_AP_FULL
,
2
,
0
,
0
,
0
,
0
,
ARM_MPU_REGION_SIZE_1GB
);
/* Region 4 setting */
MPU
->
RBAR
=
ARM_MPU_RBAR
(
4
,
0x00000000U
);
MPU
->
RASR
=
ARM_MPU_RASR
(
0
,
ARM_MPU_AP_FULL
,
0
,
0
,
1
,
1
,
0
,
ARM_MPU_REGION_SIZE_128KB
);
/* Region 5 setting */
MPU
->
RBAR
=
ARM_MPU_RBAR
(
5
,
0x20000000U
);
MPU
->
RASR
=
ARM_MPU_RASR
(
0
,
ARM_MPU_AP_FULL
,
0
,
0
,
1
,
1
,
0
,
ARM_MPU_REGION_SIZE_128KB
);
/* Region 6 setting */
MPU
->
RBAR
=
ARM_MPU_RBAR
(
6
,
0x20200000U
);
MPU
->
RASR
=
ARM_MPU_RASR
(
0
,
ARM_MPU_AP_FULL
,
0
,
0
,
1
,
1
,
0
,
ARM_MPU_REGION_SIZE_256KB
);
#if defined(BSP_USING_SDRAM)
/* Region 7 setting */
MPU
->
RBAR
=
ARM_MPU_RBAR
(
7
,
0x80000000U
);
MPU
->
RASR
=
ARM_MPU_RASR
(
0
,
ARM_MPU_AP_FULL
,
0
,
0
,
1
,
1
,
0
,
ARM_MPU_REGION_SIZE_32MB
);
/* Region 8 setting */
MPU
->
RBAR
=
ARM_MPU_RBAR
(
8
,
0x81E00000U
);
MPU
->
RASR
=
ARM_MPU_RASR
(
0
,
ARM_MPU_AP_FULL
,
1
,
1
,
0
,
0
,
0
,
ARM_MPU_REGION_SIZE_2MB
);
#endif
/* Enable MPU */
ARM_MPU_Enable
(
MPU_CTRL_PRIVDEFENA_Msk
);
/* Enable I cache and D cache */
SCB_EnableDCache
();
SCB_EnableICache
();
}
/* This is the timer interrupt service routine. */
void
SysTick_Handler
(
void
)
{
/* enter interrupt */
rt_interrupt_enter
();
rt_tick_increase
();
/* leave interrupt */
rt_interrupt_leave
();
}
#ifdef BSP_USING_DMA
void
imxrt_dma_init
(
void
)
{
edma_config_t
config
;
DMAMUX_Init
(
DMAMUX
);
EDMA_GetDefaultConfig
(
&
config
);
EDMA_Init
(
DMA0
,
&
config
);
}
#endif
void
rt_hw_board_init
()
{
BOARD_ConfigMPU
();
BOARD_InitPins
();
BOARD_BootClockRUN
();
NVIC_SetPriorityGrouping
(
NVIC_PRIORITYGROUP_4
);
SysTick_Config
(
SystemCoreClock
/
RT_TICK_PER_SECOND
);
#ifdef BSP_USING_DMA
imxrt_dma_init
();
#endif
#ifdef RT_USING_HEAP
rt_system_heap_init
((
void
*
)
HEAP_BEGIN
,
(
void
*
)
HEAP_END
);
#endif
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init
();
#endif
#ifdef RT_USING_CONSOLE
rt_console_set_device
(
RT_CONSOLE_DEVICE_NAME
);
#endif
}
bsp/imxrt/imxrt1052-seeed-ArchMix/board/board.h
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2009-09-22 Bernard add board.h to this bsp
*/
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef __BOARD_H__
#define __BOARD_H__
#include "fsl_common.h"
#include "clock_config.h"
#ifdef __CC_ARM
extern
int
Image
$$
RTT_HEAP
$$
ZI
$$
Base
;
extern
int
Image
$$
RTT_HEAP
$$
ZI
$$
Limit
;
#define HEAP_BEGIN (&Image$$RTT_HEAP$$ZI$$Base)
#define HEAP_END (&Image$$RTT_HEAP$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
extern
void
__RTT_HEAP_END
;
#define HEAP_END (&__RTT_HEAP_END)
#else
extern
int
heap_start
;
extern
int
heap_end
;
#define HEAP_BEGIN (&heap_start)
#define HEAP_END (&heap_end)
#endif
#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN)
void
rt_hw_board_init
(
void
);
#endif
bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.icf
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/*
** ###################################################################
** Processors: MIMXRT1052CVJ5B
** MIMXRT1052CVL5B
** MIMXRT1052DVJ6B
** MIMXRT1052DVL6B
**
** Compiler: IAR ANSI C/C++ Compiler for ARM
** Reference manual: IMXRT1050RM Rev.1, 03/2018
** Version: rev. 1.0, 2018-09-21
** Build: b180921
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
define symbol m_interrupts_start = 0x60002000;
define symbol m_interrupts_end = 0x600023FF;
define symbol m_text_start = 0x60002400;
define symbol m_text_end = 0x607FFFFF;
define symbol m_data_start = 0x20000000;
define symbol m_data_end = 0x2001FFFF;
define symbol m_data2_start = 0x20200000;
define symbol m_data2_end = 0x2023FFFF;
define exported symbol m_boot_hdr_conf_start = 0x60000000;
define symbol m_boot_hdr_ivt_start = 0x60001000;
define symbol m_boot_hdr_boot_data_start = 0x60001020;
define symbol m_boot_hdr_dcd_data_start = 0x60001030;
/* Sizes */
if (isdefinedsymbol(__stack_size__)) {
define symbol __size_cstack__ = __stack_size__;
} else {
define symbol __size_cstack__ = 0x0400;
}
if (isdefinedsymbol(__heap_size__)) {
define symbol __size_heap__ = __heap_size__;
} else {
define symbol __size_heap__ = 0x0400;
}
define exported symbol __VECTOR_TABLE = m_interrupts_start;
define exported symbol __VECTOR_RAM = m_interrupts_start;
define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
define exported symbol __RTT_HEAP_END = m_data_end;
define memory mem with size = 4G;
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
| mem:[from m_text_start to m_text_end];
define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
define region DATA2_region = mem:[from m_data2_start to m_data2_end];
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block RW { readwrite };
define block ZI { zi };
define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
initialize by copy { readwrite, section .textrw };
do not initialize { section .noinit };
place at address mem: m_interrupts_start { readonly section .intvec };
place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
place in TEXT_region { readonly };
place in DATA_region { block RW };
place in DATA_region { block ZI };
place in DATA_region { last block HEAP };
place in DATA_region { block NCACHE_VAR };
place in CSTACK_region { block CSTACK };
bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.lds
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/*
** ###################################################################
** Processors: MIMXRT1052CVL5A
** MIMXRT1052DVL6A
**
** Compiler: GNU C Compiler
** Reference manual: IMXRT1050RM Rev.C, 08/2017
** Version: rev. 0.1, 2017-01-10
** Build: b170927
**
** Abstract:
** Linker file for the GNU C Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** 1. Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** 2. Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** 3. Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
/* Entry Point */
ENTRY(Reset_Handler)
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
/* Specify the memory areas */
MEMORY
{
m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000
m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000
m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400
m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x1F7FDC00
m_itcm (RW) : ORIGIN = 0x00000000, LENGTH = 0x00020000
m_dtcm (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
m_ocram (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000
m_sdram (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000
m_nocache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000
}
/* Define output sections */
SECTIONS
{
.boot_data :
{
KEEP(*(.boot_hdr.conf))
} > m_boot_data
.image_vertor_table :
{
KEEP(*(.boot_hdr.ivt))
KEEP(*(.boot_hdr.boot_data))
KEEP(*(.boot_hdr.dcd_data))
} > m_image_vertor_table
/* The startup code goes first into internal RAM */
.interrupts :
{
__VECTOR_TABLE = .;
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} > m_interrupts
__VECTOR_RAM = __VECTOR_TABLE;
__RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;
/* The program code and other data goes into internal RAM */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
} > m_text
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > m_text
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > m_text
.ctors :
{
PROVIDE(__ctors_start__ = .);
/* __CTOR_LIST__ = .; */
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
/* __CTOR_END__ = .; */
PROVIDE(__ctors_end__ = .);
} > m_text
.dtors :
{
PROVIDE(__dtors_start__ = .);
/* __DTOR_LIST__ = .; */
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* __DTOR_END__ = .; */
PROVIDE(__dtors_end__ = .);
} > m_text
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} > m_text
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} > m_text
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} > m_text
__etext = .; /* define a global symbol at end of code */
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
.data : AT(__DATA_ROM)
{
. = ALIGN(4);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(m_usb_dma_init_data)
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
. = ALIGN(4);
__data_end__ = .; /* define a global symbol at data end */
} > m_dtcm
__NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);
.ncache.init : AT(__NDATA_ROM)
{
__noncachedata_start__ = .; /* create a global symbol at ncache data start */
*(NonCacheable.init)
. = ALIGN(4);
__noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
} > m_nocache
. = __noncachedata_init_end__;
.ncache :
{
*(NonCacheable)
. = ALIGN(4);
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
} > m_nocache
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
text_end = ORIGIN(m_text) + LENGTH(m_text);
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
/* Uninitialized data section */
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
. = ALIGN(4);
__START_BSS = .;
__bss_start__ = .;
*(m_usb_dma_noninit_data)
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > m_dtcm
.stack :
{
. = ALIGN(8);
stack_start = .;
. += STACK_SIZE;
stack_end = .;
__StackTop = .;
} > m_dtcm
.RTT_HEAP :
{
heap_start = .;
. = ALIGN(8);
} > m_dtcm
PROVIDE(heap_end = ORIGIN(m_dtcm) + LENGTH(m_dtcm));
.ARM.attributes 0 : { *(.ARM.attributes) }
}
bsp/imxrt/imxrt1052-seeed-ArchMix/board/linker_scripts/link.sct
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#! armcc -E
/*
** ###################################################################
** Processors: MIMXRT1052CVL5A
** MIMXRT1052DVL6A
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1050RM Rev.C, 08/2017
** Version: rev. 0.1, 2017-01-10
** Build: b170927
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
** 1. Redistributions of source code must retain the above copyright notice, this list
** of conditions and the following disclaimer.
**
** 2. Redistributions in binary form must reproduce the above copyright notice, this
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
** 3. Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
#define m_flash_config_start 0x60000000
#define m_flash_config_size 0x00001000
#define m_ivt_start 0x60001000
#define m_ivt_size 0x00001000
#define m_text_start 0x60002000
#define m_text_size 0x1F7FE000
#define m_data_start 0x20000000
#define m_data_size 0x00020000
#define m_ncache_start 0x81E00000
#define m_ncache_size 0x00200000
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x1000
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
; load region size_region
LR_IROM1 m_text_start m_text_size
{
ER_IROM1 m_text_start m_text_size ; load address = execution address
{
* (RESET,+FIRST)
* (InRoot$$Sections)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data
{
.ANY (+RW +ZI)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up
ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
; ncache RW data
RW_m_ncache m_ncache_start m_ncache_size
{
* (NonCacheable.init)
* (NonCacheable)
}
ITCM 0x400 0xFBFF {
;drv_flexspi_hyper.o(+RO)
;fsl_flexspi.o(+RO)
* (*CLOCK_DisableClock)
* (*CLOCK_ControlGate)
* (*CLOCK_EnableClock)
* (*CLOCK_SetDiv)
* (itcm)
}
}
bsp/imxrt/imxrt1052-seeed-ArchMix/board/ports/sdram_port.h
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-05 zylx The first version for STM32F4xx
* 2019-4-25 misonyo port to IMXRT
*/
#ifndef SDRAM_PORT_H__
#define SDRAM_PORT_H__
/* parameters for sdram peripheral */
#define SDRAM_BANK_ADDR ((uint32_t)0x80000000U)
/* region#0/1/2/3: kSEMC_SDRAM_CS0/1/2/3 */
#define SDRAM_REGION kSEMC_SDRAM_CS0
/* CS pin: kSEMC_MUXCSX0/1/2/3 */
#define SDRAM_CS_PIN kSEMC_MUXCSX0
/* size(kbyte):32MB = 32*1024*1KBytes */
#define SDRAM_SIZE ((uint32_t)0x8000)
/* data width: kSEMC_PortSize8Bit,kSEMC_PortSize16Bit */
#define SDRAM_DATA_WIDTH kSEMC_PortSize16Bit
/* column bit numbers: kSEMC_SdramColunm_9/10/11/12bit */
#define SDRAM_COLUMN_BITS kSEMC_SdramColunm_9bit
/* cas latency clock number: kSEMC_LatencyOne/Two/Three */
#define SDRAM_CAS_LATENCY kSEMC_LatencyThree
/* Timing configuration for W9825G6KH */
/* TRP:precharge to active command time (ns) */
#define SDRAM_TRP 18
/* TRCD:active to read/write command delay time (ns) */
#define SDRAM_TRCD 18
/* The time between two refresh commands,Use the maximum of the (Trfc , Txsr).(ns) */
#define SDRAM_REFRESH_RECOVERY 67
/* TWR:write recovery time (ns). */
#define SDRAM_TWR 12
/* TRAS:active to precharge command time (ns). */
#define SDRAM_TRAS 42
/* TRC time (ns). */
#define SDRAM_TRC 60
/* active to active time (ns). */
#define SDRAM_ACT2ACT 60
/* refresh time (ns). 64ms */
#define SDRAM_REFRESH_ROW 64 * 1000000 / 8192
#endif
/* SDRAM_PORT_H__ */
bsp/imxrt/imxrt1052-seeed-ArchMix/figures/Arch_Mix.jpg
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bsp/imxrt/imxrt1052-seeed-ArchMix/project.uvoptx
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt
xmlns:xsi=
"http://www.w3.org/2001/XMLSchema-instance"
xsi:noNamespaceSchemaLocation=
"project_optx.xsd"
>
<SchemaVersion>
1.0
</SchemaVersion>
<Header>
### uVision Project, (C) Keil Software
</Header>
<Extensions>
<cExt>
*.c
</cExt>
<aExt>
*.s*; *.src; *.a*
</aExt>
<oExt>
*.obj; *.o
</oExt>
<lExt>
*.lib
</lExt>
<tExt>
*.txt; *.h; *.inc; *.md
</tExt>
<pExt>
*.plm
</pExt>
<CppX>
*.cpp
</CppX>
<nMigrate>
0
</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>
0
</dwLowDateTime>
<dwHighDateTime>
0
</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>
rtthread
</TargetName>
<ToolsetNumber>
0x4
</ToolsetNumber>
<ToolsetName>
ARM-ADS
</ToolsetName>
<TargetOption>
<CLKADS>
12000000
</CLKADS>
<OPTTT>
<gFlags>
1
</gFlags>
<BeepAtEnd>
1
</BeepAtEnd>
<RunSim>
0
</RunSim>
<RunTarget>
1
</RunTarget>
<RunAbUc>
0
</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>
1
</HexSelection>
<FlashByte>
65535
</FlashByte>
<HexRangeLowAddress>
0
</HexRangeLowAddress>
<HexRangeHighAddress>
0
</HexRangeHighAddress>
<HexOffset>
0
</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>
79
</PageWidth>
<PageLength>
66
</PageLength>
<TabStop>
8
</TabStop>
<ListingPath>
.\build\keil\List\
</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>
1
</CreateCListing>
<CreateAListing>
1
</CreateAListing>
<CreateLListing>
1
</CreateLListing>
<CreateIListing>
0
</CreateIListing>
<AsmCond>
1
</AsmCond>
<AsmSymb>
1
</AsmSymb>
<AsmXref>
0
</AsmXref>
<CCond>
1
</CCond>
<CCode>
0
</CCode>
<CListInc>
0
</CListInc>
<CSymb>
0
</CSymb>
<LinkerCodeListing>
0
</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>
1
</LMap>
<LComments>
1
</LComments>
<LGenerateSymbols>
1
</LGenerateSymbols>
<LLibSym>
1
</LLibSym>
<LLines>
1
</LLines>
<LLocSym>
1
</LLocSym>
<LPubSym>
1
</LPubSym>
<LXref>
0
</LXref>
<LExpSel>
0
</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>
1
</tvExp>
<tvExpOptDlg>
0
</tvExpOptDlg>
<IsCurrentTarget>
1
</IsCurrentTarget>
</OPTFL>
<CpuCode>
8
</CpuCode>
<DebugOpt>
<uSim>
0
</uSim>
<uTrg>
1
</uTrg>
<sLdApp>
1
</sLdApp>
<sGomain>
1
</sGomain>
<sRbreak>
1
</sRbreak>
<sRwatch>
1
</sRwatch>
<sRmem>
1
</sRmem>
<sRfunc>
1
</sRfunc>
<sRbox>
1
</sRbox>
<tLdApp>
1
</tLdApp>
<tGomain>
1
</tGomain>
<tRbreak>
1
</tRbreak>
<tRwatch>
1
</tRwatch>
<tRmem>
1
</tRmem>
<tRfunc>
0
</tRfunc>
<tRbox>
1
</tRbox>
<tRtrace>
1
</tRtrace>
<sRSysVw>
1
</sRSysVw>
<tRSysVw>
1
</tRSysVw>
<sRunDeb>
0
</sRunDeb>
<sLrtime>
0
</sLrtime>
<bEvRecOn>
1
</bEvRecOn>
<bSchkAxf>
0
</bSchkAxf>
<bTchkAxf>
0
</bTchkAxf>
<nTsel>
3
</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile>
.\flexspi_nor.ini
</tIfile>
<pMon>
BIN\CMSIS_AGDI.dll
</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>
0
</Number>
<Key>
CMSIS_AGDI
</Key>
<Name>
-X"Any" -UAny -O206 -S8 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC8000 -FN1 -FF0MIMXRT105x_QuadSPI_4KB_SEC.FLM -FS060000000 -FL0800000 -FP0($$Device:MIMXRT1052CVL5B$arm\MIMXRT105x_QuadSPI_4KB_SEC.FLM)
</Name>
</SetRegEntry>
<SetRegEntry>
<Number>
0
</Number>
<Key>
JL2CM3
</Key>
<Name>
-U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC8000 -FN1 -FF0MIMXRT105x_QuadSPI_4KB_SEC -FS060000000 -FL0800000 -FP0($$Device:MIMXRT1052CVL5B$arm\MIMXRT105x_QuadSPI_4KB_SEC.FLM)
</Name>
</SetRegEntry>
<SetRegEntry>
<Number>
0
</Number>
<Key>
UL2CM3
</Key>
<Name>
UL2CM3(-S0 -C0 -P0 ) -FN2 -FC8000 -FD20000000 -FF0MIMXRT105x_HYPER_256KB_SEC -FF1MIMXRT105x_QuadSPI_4KB_SEC -FL04000000 -FL1800000 -FS060000000 -FS160000000 -FP0($$Device:MIMXRT1052CVL5B$arm\MIMXRT105x_HYPER_256KB_SEC.FLM) -FP1($$Device:MIMXRT1052CVL5B$arm\MIMXRT105x_QuadSPI_4KB_SEC.FLM)
</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>
0
</THDelay>
</Tracepoint>
<DebugFlag>
<trace>
0
</trace>
<periodic>
0
</periodic>
<aLwin>
0
</aLwin>
<aCover>
0
</aCover>
<aSer1>
0
</aSer1>
<aSer2>
0
</aSer2>
<aPa>
0
</aPa>
<viewmode>
0
</viewmode>
<vrSel>
0
</vrSel>
<aSym>
0
</aSym>
<aTbox>
0
</aTbox>
<AscS1>
0
</AscS1>
<AscS2>
0
</AscS2>
<AscS3>
0
</AscS3>
<aSer3>
0
</aSer3>
<eProf>
0
</eProf>
<aLa>
0
</aLa>
<aPa1>
0
</aPa1>
<AscS4>
0
</AscS4>
<aSer4>
0
</aSer4>
<StkLoc>
0
</StkLoc>
<TrcWin>
0
</TrcWin>
<newCpu>
0
</newCpu>
<uProt>
0
</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>
0
</bLintAuto>
<bAutoGenD>
0
</bAutoGenD>
<LntExFlags>
0
</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
<DebugDescription>
<Enable>
1
</Enable>
<EnableFlashSeq>
1
</EnableFlashSeq>
<EnableLog>
0
</EnableLog>
<Protocol>
2
</Protocol>
<DbgClock>
10000000
</DbgClock>
</DebugDescription>
</TargetOption>
</Target>
</ProjectOpt>
bsp/imxrt/imxrt1052-seeed-ArchMix/project.uvprojx
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此差异已折叠。
点击以展开。
bsp/imxrt/imxrt1052-seeed-ArchMix/rtconfig.h
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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
/* kservice optimization */
#define RT_DEBUG
#define RT_DEBUG_COLOR
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_MEMHEAP
#define RT_USING_MEMHEAP_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40003
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
/* Command shell */
#define RT_USING_FINSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_USING_MSH_ONLY
#define FINSH_ARG_MAX 10
/* Device virtual file system */
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
/* Using USB */
/* POSIX layer and C standard library */
#define RT_LIBC_USING_TIME
#define RT_LIBC_FIXED_TIMEZONE 8
/* Network */
/* Socket abstraction layer */
/* Network interface device */
/* light weight TCP/IP stack */
/* AT commands */
/* VBUS(Virtual Software BUS) */
/* Utilities */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* multimedia packages */
/* tools packages */
/* system packages */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* AI packages */
/* miscellaneous packages */
/* samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* Hardware Drivers Config */
#define SOC_IMXRT1052CVL5B
/* Onboard Peripheral Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_DMA
#define BSP_USING_GPIO
#define BSP_USING_LPUART
#define BSP_USING_LPUART1
#endif
bsp/imxrt/imxrt1052-seeed-ArchMix/rtconfig.py
0 → 100644
浏览文件 @
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import
os
import
sys
# toolchains options
ARCH
=
'arm'
CPU
=
'cortex-m7'
CROSS_TOOL
=
'gcc'
# bsp lib config
BSP_LIBRARY_TYPE
=
None
if
os
.
getenv
(
'RTT_CC'
):
CROSS_TOOL
=
os
.
getenv
(
'RTT_CC'
)
if
os
.
getenv
(
'RTT_ROOT'
):
RTT_ROOT
=
os
.
getenv
(
'RTT_ROOT'
)
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if
CROSS_TOOL
==
'gcc'
:
PLATFORM
=
'gcc'
EXEC_PATH
=
r
'C:\Users\XXYYZZ'
elif
CROSS_TOOL
==
'keil'
:
PLATFORM
=
'armcc'
EXEC_PATH
=
r
'C:/Keil_v5'
elif
CROSS_TOOL
==
'iar'
:
PLATFORM
=
'iar'
EXEC_PATH
=
r
'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
if
os
.
getenv
(
'RTT_EXEC_PATH'
):
EXEC_PATH
=
os
.
getenv
(
'RTT_EXEC_PATH'
)
BUILD
=
'debug'
#BUILD = 'release'
if
PLATFORM
==
'gcc'
:
PREFIX
=
'arm-none-eabi-'
CC
=
PREFIX
+
'gcc'
CXX
=
PREFIX
+
'g++'
AS
=
PREFIX
+
'gcc'
AR
=
PREFIX
+
'ar'
LINK
=
PREFIX
+
'gcc'
TARGET_EXT
=
'elf'
SIZE
=
PREFIX
+
'size'
OBJDUMP
=
PREFIX
+
'objdump'
OBJCPY
=
PREFIX
+
'objcopy'
STRIP
=
PREFIX
+
'strip'
DEVICE
=
' -mcpu='
+
CPU
+
' -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
CFLAGS
=
DEVICE
+
' -Wall -D__FPU_PRESENT -eentry'
AFLAGS
=
' -c'
+
DEVICE
+
' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry'
LFLAGS
=
DEVICE
+
' -lm -lgcc -lc'
+
' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
CPATH
=
''
LPATH
=
''
if
BUILD
==
'debug'
:
CFLAGS
+=
' -gdwarf-2'
AFLAGS
+=
' -gdwarf-2'
CFLAGS
+=
' -O0'
else
:
CFLAGS
+=
' -O2 -Os'
POST_ACTION
=
OBJCPY
+
' -O binary --remove-section=.boot_data --remove-section=.image_vertor_table --remove-section=.ncache $TARGET rtthread.bin
\n
'
+
SIZE
+
' $TARGET
\n
'
# module setting
CXXFLAGS
=
' -Woverloaded-virtual -fno-exceptions -fno-rtti '
M_CFLAGS
=
CFLAGS
+
' -mlong-calls -fPIC '
M_CXXFLAGS
=
CXXFLAGS
+
' -mlong-calls -fPIC'
M_LFLAGS
=
DEVICE
+
CXXFLAGS
+
' -Wl,--gc-sections,-z,max-page-size=0x4'
+
\
' -shared -fPIC -nostartfiles -static-libgcc'
M_POST_ACTION
=
STRIP
+
' -R .hash $TARGET
\n
'
+
SIZE
+
' $TARGET
\n
'
elif
PLATFORM
==
'armcc'
:
CC
=
'armcc'
CXX
=
'armcc'
AS
=
'armasm'
AR
=
'armar'
LINK
=
'armlink'
TARGET_EXT
=
'axf'
DEVICE
=
' --cpu '
+
CPU
+
'.fp.sp'
CFLAGS
=
DEVICE
+
' --apcs=interwork'
AFLAGS
=
DEVICE
LFLAGS
=
DEVICE
+
' --libpath "'
+
EXEC_PATH
+
'\ARM\ARMCC\lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board\linker_scripts\link.sct"'
CFLAGS
+=
' --diag_suppress=66,1296,186,6134'
CFLAGS
+=
' -I'
+
EXEC_PATH
+
'/ARM/RV31/INC'
LFLAGS
+=
' --libpath '
+
EXEC_PATH
+
'/ARM/RV31/LIB'
EXEC_PATH
+=
'/arm/bin40/'
if
BUILD
==
'debug'
:
CFLAGS
+=
' -g -O0'
AFLAGS
+=
' -g'
else
:
CFLAGS
+=
' -O2'
CXXFLAGS
=
CFLAGS
CFLAGS
+=
' --c99'
POST_ACTION
=
'fromelf -z $TARGET'
# POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif
PLATFORM
==
'iar'
:
CC
=
'iccarm'
CXX
=
'iccarm'
AS
=
'iasmarm'
AR
=
'iarchive'
LINK
=
'ilinkarm'
TARGET_EXT
=
'out'
DEVICE
=
' -D__FPU_PRESENT'
CFLAGS
=
DEVICE
CFLAGS
+=
' --diag_suppress Pa050'
CFLAGS
+=
' --no_cse'
CFLAGS
+=
' --no_unroll'
CFLAGS
+=
' --no_inline'
CFLAGS
+=
' --no_code_motion'
CFLAGS
+=
' --no_tbaa'
CFLAGS
+=
' --no_clustering'
CFLAGS
+=
' --no_scheduling'
CFLAGS
+=
' --debug'
CFLAGS
+=
' --endian=little'
CFLAGS
+=
' --cpu='
+
CPU
CFLAGS
+=
' -e'
CFLAGS
+=
' --fpu=None'
CFLAGS
+=
' --dlib_config "'
+
EXEC_PATH
+
'/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS
+=
' -Ol'
CFLAGS
+=
' --use_c++_inline'
AFLAGS
=
''
AFLAGS
+=
' -s+'
AFLAGS
+=
' -w+'
AFLAGS
+=
' -r'
AFLAGS
+=
' --cpu '
+
CPU
AFLAGS
+=
' --fpu None'
if
BUILD
==
'debug'
:
CFLAGS
+=
' --debug'
CFLAGS
+=
' -On'
else
:
CFLAGS
+=
' -Oh'
LFLAGS
=
' --config "board/linker_scripts/link.icf"'
LFLAGS
+=
' --redirect _Printf=_PrintfTiny'
LFLAGS
+=
' --redirect _Scanf=_ScanfSmall'
LFLAGS
+=
' --entry __iar_program_start'
CXXFLAGS
=
CFLAGS
EXEC_PATH
=
EXEC_PATH
+
'/arm/bin/'
POST_ACTION
=
'ielftool --bin $TARGET rtthread.bin'
def
dist_handle
(
BSP_ROOT
,
dist_dir
):
import
sys
cwd_path
=
os
.
getcwd
()
sys
.
path
.
append
(
os
.
path
.
join
(
os
.
path
.
dirname
(
BSP_ROOT
),
'tools'
))
from
sdk_dist
import
dist_do_building
dist_do_building
(
BSP_ROOT
,
dist_dir
)
\ No newline at end of file
bsp/imxrt/imxrt1052-seeed-ArchMix/template.uvoptx
0 → 100644
浏览文件 @
9e172489
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt
xmlns:xsi=
"http://www.w3.org/2001/XMLSchema-instance"
xsi:noNamespaceSchemaLocation=
"project_optx.xsd"
>
<SchemaVersion>
1.0
</SchemaVersion>
<Header>
### uVision Project, (C) Keil Software
</Header>
<Extensions>
<cExt>
*.c
</cExt>
<aExt>
*.s*; *.src; *.a*
</aExt>
<oExt>
*.obj; *.o
</oExt>
<lExt>
*.lib
</lExt>
<tExt>
*.txt; *.h; *.inc; *.md
</tExt>
<pExt>
*.plm
</pExt>
<CppX>
*.cpp
</CppX>
<nMigrate>
0
</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>
0
</dwLowDateTime>
<dwHighDateTime>
0
</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>
rtthread
</TargetName>
<ToolsetNumber>
0x4
</ToolsetNumber>
<ToolsetName>
ARM-ADS
</ToolsetName>
<TargetOption>
<CLKADS>
12000000
</CLKADS>
<OPTTT>
<gFlags>
1
</gFlags>
<BeepAtEnd>
1
</BeepAtEnd>
<RunSim>
0
</RunSim>
<RunTarget>
1
</RunTarget>
<RunAbUc>
0
</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>
1
</HexSelection>
<FlashByte>
65535
</FlashByte>
<HexRangeLowAddress>
0
</HexRangeLowAddress>
<HexRangeHighAddress>
0
</HexRangeHighAddress>
<HexOffset>
0
</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>
79
</PageWidth>
<PageLength>
66
</PageLength>
<TabStop>
8
</TabStop>
<ListingPath>
.\build\keil\List\
</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>
1
</CreateCListing>
<CreateAListing>
1
</CreateAListing>
<CreateLListing>
1
</CreateLListing>
<CreateIListing>
0
</CreateIListing>
<AsmCond>
1
</AsmCond>
<AsmSymb>
1
</AsmSymb>
<AsmXref>
0
</AsmXref>
<CCond>
1
</CCond>
<CCode>
0
</CCode>
<CListInc>
0
</CListInc>
<CSymb>
0
</CSymb>
<LinkerCodeListing>
0
</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>
1
</LMap>
<LComments>
1
</LComments>
<LGenerateSymbols>
1
</LGenerateSymbols>
<LLibSym>
1
</LLibSym>
<LLines>
1
</LLines>
<LLocSym>
1
</LLocSym>
<LPubSym>
1
</LPubSym>
<LXref>
0
</LXref>
<LExpSel>
0
</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>
1
</tvExp>
<tvExpOptDlg>
0
</tvExpOptDlg>
<IsCurrentTarget>
1
</IsCurrentTarget>
</OPTFL>
<CpuCode>
8
</CpuCode>
<DebugOpt>
<uSim>
0
</uSim>
<uTrg>
1
</uTrg>
<sLdApp>
1
</sLdApp>
<sGomain>
1
</sGomain>
<sRbreak>
1
</sRbreak>
<sRwatch>
1
</sRwatch>
<sRmem>
1
</sRmem>
<sRfunc>
1
</sRfunc>
<sRbox>
1
</sRbox>
<tLdApp>
1
</tLdApp>
<tGomain>
1
</tGomain>
<tRbreak>
1
</tRbreak>
<tRwatch>
1
</tRwatch>
<tRmem>
1
</tRmem>
<tRfunc>
0
</tRfunc>
<tRbox>
1
</tRbox>
<tRtrace>
1
</tRtrace>
<sRSysVw>
1
</sRSysVw>
<tRSysVw>
1
</tRSysVw>
<sRunDeb>
0
</sRunDeb>
<sLrtime>
0
</sLrtime>
<bEvRecOn>
1
</bEvRecOn>
<bSchkAxf>
0
</bSchkAxf>
<bTchkAxf>
0
</bTchkAxf>
<nTsel>
3
</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile>
.\flexspi_nor.ini
</tIfile>
<pMon>
BIN\CMSIS_AGDI.dll
</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>
0
</Number>
<Key>
CMSIS_AGDI
</Key>
<Name>
-X"Any" -UAny -O206 -S8 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC8000 -FN1 -FF0MIMXRT105x_QuadSPI_4KB_SEC.FLM -FS060000000 -FL0800000 -FP0($$Device:MIMXRT1052CVL5B$arm\MIMXRT105x_QuadSPI_4KB_SEC.FLM)
</Name>
</SetRegEntry>
<SetRegEntry>
<Number>
0
</Number>
<Key>
JL2CM3
</Key>
<Name>
-U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC8000 -FN1 -FF0MIMXRT105x_QuadSPI_4KB_SEC -FS060000000 -FL0800000 -FP0($$Device:MIMXRT1052CVL5B$arm\MIMXRT105x_QuadSPI_4KB_SEC.FLM)
</Name>
</SetRegEntry>
<SetRegEntry>
<Number>
0
</Number>
<Key>
UL2CM3
</Key>
<Name>
UL2CM3(-S0 -C0 -P0 ) -FN2 -FC8000 -FD20000000 -FF0MIMXRT105x_HYPER_256KB_SEC -FF1MIMXRT105x_QuadSPI_4KB_SEC -FL04000000 -FL1800000 -FS060000000 -FS160000000 -FP0($$Device:MIMXRT1052CVL5B$arm\MIMXRT105x_HYPER_256KB_SEC.FLM) -FP1($$Device:MIMXRT1052CVL5B$arm\MIMXRT105x_QuadSPI_4KB_SEC.FLM)
</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>
0
</THDelay>
</Tracepoint>
<DebugFlag>
<trace>
0
</trace>
<periodic>
0
</periodic>
<aLwin>
0
</aLwin>
<aCover>
0
</aCover>
<aSer1>
0
</aSer1>
<aSer2>
0
</aSer2>
<aPa>
0
</aPa>
<viewmode>
0
</viewmode>
<vrSel>
0
</vrSel>
<aSym>
0
</aSym>
<aTbox>
0
</aTbox>
<AscS1>
0
</AscS1>
<AscS2>
0
</AscS2>
<AscS3>
0
</AscS3>
<aSer3>
0
</aSer3>
<eProf>
0
</eProf>
<aLa>
0
</aLa>
<aPa1>
0
</aPa1>
<AscS4>
0
</AscS4>
<aSer4>
0
</aSer4>
<StkLoc>
0
</StkLoc>
<TrcWin>
0
</TrcWin>
<newCpu>
0
</newCpu>
<uProt>
0
</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>
0
</bLintAuto>
<bAutoGenD>
0
</bAutoGenD>
<LntExFlags>
0
</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
<DebugDescription>
<Enable>
1
</Enable>
<EnableFlashSeq>
1
</EnableFlashSeq>
<EnableLog>
0
</EnableLog>
<Protocol>
2
</Protocol>
<DbgClock>
10000000
</DbgClock>
</DebugDescription>
</TargetOption>
</Target>
</ProjectOpt>
bsp/imxrt/imxrt1052-seeed-ArchMix/template.uvprojx
0 → 100644
浏览文件 @
9e172489
此差异已折叠。
点击以展开。
bsp/imxrt/libraries/MIMXRT1050/SConscript
浏览文件 @
9e172489
...
...
@@ -73,8 +73,8 @@ if GetDepend(['BSP_USING_DMA']):
src
+=
[
'MIMXRT1052/drivers/fsl_dmamux.c'
]
src
+=
[
'MIMXRT1052/drivers/fsl_edma.c'
]
src
+=
[
'MIMXRT1052/drivers/fsl_lpuart_edma.c'
]
src
+=
[
'MIMXRT1052/drivers/fsl_lpspi_edma.c'
]
if
GetDepend
([
'BSP_USING_SPI'
]):
src
+=
[
'MIMXRT1052/drivers/fsl_lpspi_edma.c'
]
if
rtconfig
.
CROSS_TOOL
==
'gcc'
:
group
=
DefineGroup
(
'Libraries'
,
src
,
depend
=
[
''
],
CPPPATH
=
path
,
ASFLAGS
=
'$ASFLAGS -D __STARTUP_CLEAR_BSS'
)
...
...
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