Add Microchip SAM series MCU support for RT-Thread (#5771)

* Add Microchip SAM series MCU support for RT-Thread

Add Microchip SAM series MCU support for RT-Thread, including SAM Cortex-M0+, M4F and M7.

* Add bsp directory to ignored check list

Add bsp directory to ignored check list, add microchip /samc21/same54/same70 to workflows list

* remove STDIO definition and bug fix

1. remove STDIO code from Microchip official BSP. 2. bug fix of SAME70 hpl/hpl_usart.c, samc21&same54 hpl/hpl_sercom.c baudrate update interface.  3. Add RT-Thread standard STDIO implementation on Microchip SAM MCU.

* add CAN driver & example and script fix

Add CAN driver and example for SAMC21/SAME5x/SAME70 and fix rtconfig.py issue(unused space might result link error)

* Add Chinese version README

Add Chinese version README for SAMC21/E54/E70

.github/workflows/action.yml

@@ -168,6 +168,9 @@ jobs:
          - {RTT_BSP: "raspberry-pi/raspi3-64", RTT_TOOL_CHAIN: "sourcery-aarch64"}
          - {RTT_BSP: "raspberry-pi/raspi4-64", RTT_TOOL_CHAIN: "sourcery-aarch64"}
          - {RTT_BSP: "rockchip/rk3568", RTT_TOOL_CHAIN: "sourcery-aarch64"}
+         - {RTT_BSP: "microchip/samc21", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "microchip/same54", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "microchip/same70", RTT_TOOL_CHAIN: "sourcery-arm"}
     steps:
       - uses: actions/checkout@v3
       - name: Set up Python

bsp/microchip/README.md

+# 1. Microchip BSP Introduction
+
+Supported Microchip SAM (ARM Cortex-Mx Core) MCU is as following：
+
+## ARM Cortex-M0+ Series
+- samc21 | 5V Cortex-M0+ with 2 CAN-FD support
+- saml21 | 3.3V low power Cortex-M0+
+- samd21 | 3.3V industrial level Cortex-M0+
+
+## ARM Cortex-M4 Series
+- same54 | 3.3V 120MHz Cortex-M4F core with CAN-FD/USB/Ethernet support
+
+## ARM Cortex-M7 Series
+- same70 | 3.3V 300MHz Cortex-M7 core with CAN-FD/High speed USB/Ethernet support
+
+## Directory description：
+	* applications: 
+		* user main function entrance,
+		* driver example - like i2c, can, adc ...
+		* application example
+	* board: 
+		* user board initialization
+		* user driver adpater code, like console device, ethernet device
+	* bsp:
+		* MCU BSP files - startup file, peripheral drivers, configuation headers and linker script
+		* generated from start.atmel.com - DO NOT modify it
+
+# 2. RT-Thread porting guide of Microchip SAM MCU
+
+## 2.1 Configure project BSP on Atmel Start
+
+	* Visit <https://start.atmel.com/#> and click CREATE NEW PROJECT.
+
+![](doc/2-1-1-atmel-start-online.png)
+
+	* Input MCU part number and then select device, click CREATE NEW PROJECT.
+
+![](doc/2-1-2-atmel-start-newproject.png)
+
+	* Add STDIO and other driver/middleware to project.
+
+![](doc/2-1-3-atmel-start-add-STDIO.png)
+
+	* Configure STDIO driver.
+
+![](doc/2-1-4-atmel-start-driver-stdio.png)
+
+	* Configure CAN module clock.
+
+![](doc/2-1-5-atmel-start-can-clock.png)
+
+	* Configure CAN module driver.
+
+![](doc/2-1-6-atmel-start-driver-can0.png)
+
+![](doc/2-1-6-atmel-start-driver-can1.png)
+
+	* Add LED pin description.
+
+![](doc/2-1-8-atmel-start-add-LED0.png)
+
+	* Rename project.
+
+![](doc/2-1-7-atmel-start-rename-project.png)
+
+	* Save project configuration.
+
+![](doc/2-1-9-atmel-start-save-configuration.png)
+
+	* Export project source code.
+
+![](doc/2-1-10-atmel-start-export-project.png)
+
+## 2.2 Add project to RT-Thread source code
+
+	* Link: <https://github.com/RT-Thread/rt-thread> and download RT souce code.
+
+![](doc/2-2-1-atmel-start-download-RT-Thread.png)
+
+	* Unzip downloaded RT-Thread and SAME70 CAN Example
+
+![](doc/2-2-2-atmel-start-unzip-file.png)
+
+	* Enter rt-thread-xxx/bsp/microchip directory and copy same70 folder and rename it to same70q20.
+
+![](doc/2-2-3-atmel-start-copy-file.png)
+
+	* Enter same70q20 directory and remove all files except SConscript file.
+
+![](doc/2-2-4-atmel-start-remove-old-files.png)
+
+	* Copy all files from SAME70 CAN Example to rt-thread-xxx/bsp/microchip/same70q20/bsp.
+
+![](doc/2-2-5-atmel-start-copy-files.png)
+
+	* Modify rt-thread-xxx\bsp\microchip\same70q20\rtconfig.py.
+
+![](doc/2-2-6-atmel-start-modify-file0.png)
+
+	* Modify rt-thread-xxx\bsp\microchip\same70q20\bsp\SConscript.
+
+![](doc/2-2-6-atmel-start-modify-file1.png)
+
+	* Modify rt-thread-xxx\bsp\microchip\same70q20\bsp\same70b\gcc\gcc\same70q20b_flash.ld.
+
+![](doc/2-2-6-atmel-start-modify-file2.png)
+
+	* Modify rt-thread-xxx\bsp\microchip\same70q20\bsp\same70b\gcc\gcc\startup_same70q20b.c.
+
+![](doc/2-2-6-atmel-start-modify-file3.png)
+
+	* Alright, now you can use RT-Thread env tools to compile the project.
+
+## 2.3 Compile project with RT-Thread env tools
+
+About RT-Thread env tools, click [Here](https://github.com/RT-Thread/rt-thread/blob/master/documentation/env/env.md).
+
+	* Download RT-Thread env tools <https://www.rt-thread.org/page/download.html>
+
+![](doc/2-3-1-atmel-start-download-env-tools.png)
+
+	* Unzip downloaded file and run env.exe.
+
+![](doc/2-3-2-atmel-start-run-env-tools.png)
+
+	* Enter your project directory and run scons command to compile it.
+
+![](doc/2-3-3-atmel-start-env-tools-compile.png)
+
+	* Compile error you may have and proposed solution.
+
+![](doc/2-3-4-atmel-start-env-tools-errors.png)
+
+	* Fix compiling error
+
+![](doc/2-3-5-atmel-start-env-tools-fixerrors.png)
+
+	* Compiling success
+
+![](doc/2-3-6-atmel-start-env-tools-compiling-OK.png)
+
+	* In the following chapter I will show you how to debug RT-Thread with Studio 7.
+
+# 3. RT-Thread debugging with Microchip IDE
+
+	* Link: <https://www.microchip.com/en-us/tools-resources/develop/microchip-studio>, download & install Microchip Studio 7.
+
+![](doc/3-1-1-atmel-start-Studio7-download.png)
+
+	* Open installed Microchip Studio 7 and open object file for debugging.
+
+![](doc/3-1-2-atmel-start-Studio7-open-objects.png)
+
+	* Choose object file, fill project name and select where to save this project.
+
+![](doc/3-1-3-atmel-start-Studio7-import-debug.png)
+
+	* Select the right part number and complete object set up.
+
+![](doc/3-1-4-atmel-start-Studio7-select-device.png)
+
+	* Object file import complete and you can see related files are linked to project.
+
+![](doc/3-1-5-atmel-start-Studio7-project-complete.png)
+
+	* Right click the project and choose the debug tools in project propertities setting.
+
+![](doc/3-1-6-atmel-start-Studio7-project-properties.png)
+
+	* Choose debugger/programmer and debugger interface - SWD or JTGA.
+
+![](doc/3-1-7-atmel-start-Studio7-select-tools.png)
+
+	* Press debugging button and enjoy your debugging journey.
+
+![](doc/3-1-8-atmel-start-Studio7-start-debugging1.png)
+
+		* Debugging start and you can add breakpoint.
+
+![](doc/3-1-8-atmel-start-Studio7-start-debugging2.png)
+
+		* Debugging paused at breakpoint and you can monitor local variables at Watch window.
+
+![](doc/3-1-8-atmel-start-Studio7-start-debugging3.png)
+
+
+# 4. Reconfigure MCU BSP
+
+	* Visit <https://start.atmel.com/#> and upload project configuration.
+
+![](doc/4-1-1-atmel-start-Studio7-reimport-project.png)
+
+	* Now you can reconfigure your project.
+
+![](doc/4-1-2-atmel-start-Studio7-project-configurtion.png)
+
+
+# 5. Microchip SAM MCU BSP configuration and user guide
+
+	* Please refer to <ASF4 API Reference Manual> for more details
+[ASF4 API Reference Manual](https://ww1.microchip.com/downloads/en/DeviceDoc/50002633B.pdf)
+
+## 5.1 SAMC2x/E5x/E70 CAN Driver
+
+	* CAN driver configuration.
+
+![](doc/5-1-1-atmel-start-driver-can0.png)
+![](doc/5-1-1-atmel-start-driver-can1.png)
+
+	* CAN driver user guide - see <ASF4 API Reference Manual.pdf> P121 for more details. 
+
+	* To be continued.
+
+# 6. Contact Info
+
+- [Kevin Liu](https://github.com/klmchp)
+
+	* https://github.com/klmchp && kevin.liu.mchp@gmail.com
\ No newline at end of file

bsp/microchip/samc21/.config

+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=200
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_PRINTF_LONGLONG is not set
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x40100
+CONFIG_ARCH_ARM=y
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_ARM_CORTEX_M=y
+CONFIG_ARCH_ARM_CORTEX_M0=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+# CONFIG_RT_USING_MSH is not set
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_USING_FAL is not set
+# CONFIG_RT_USING_LWP is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_PIN is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# POSIX extension functions
+#
+# CONFIG_PKG_USING_POSIX_GETLINE is not set
+# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
+# CONFIG_PKG_USING_POSIX_ITOA is not set
+# CONFIG_PKG_USING_POSIX_STRINGS is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_RTDUINO is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_SAMC21J18=y
+# CONFIG_SOC_SAMC21G18 is not set
+# CONFIG_SOC_SAMC21E18 is not set
+
+#
+# Onboard Peripheral Drivers
+#
+CONFIG_SAMC21_CAN0=y
+CONFIG_SAMC21_ADC0=y
+
+#
+# Application Demo Config
+#
+CONFIG_SAM_CAN_EXAMPLE=y
+CONFIG_SAM_ADC_EXAMPLE=y
+CONFIG_SOC_SAMC21=y

bsp/microchip/samc21/.ignore_format.yml

+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- bsp

bsp/microchip/samc21/Kconfig

+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+# you can change the RTT_ROOT default: "rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "board/Kconfig"
+
+config SOC_SAMC21
+    bool 
+    select ARCH_ARM
+    select ARCH_ARM_CORTEX_M
+    select ARCH_ARM_CORTEX_M0
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y

bsp/microchip/samc21/README.md

+# SAMC21J18A BSP Introduction
+
+[中文](README_zh.md) 
+
+- MCU: ATSAMC21J18A @64MHz, 256KB FLASH, 32KB RAM, 2.7V – 5.5V
+- C21: Cortex-M0+ + Advanced Feature Set + 2x CAN-FD + Delta-Sigma ADC
+- Pin: N=100 pins, J=64 pins, G=48 pins, E=32 pins
+- Flash: 18=256KB, 17=128KB, 16=64KB , 15=32KB(size=2^n)
+- SRAM : 32KB(Flash 256KB), 16KB(Flash 128KB), 8KB(Flash 64KB), 4KB(Flash 32KB)
+## Datasheet: <https://www.microchip.com/en-us/product/ATSAMC21J18A>
+
+#### KEY FEATURES
+
+#### Core
+  - 32-bit Arm® Cortex®-M0+ CPU running at up to 48 MHz or 64 MHz with Single-cycle hardware multiplier
+
+####  Memories
+  - 32/64/128/256 KB in-system self-programmable Flash
+  - 1/2/4/8 KB independent self-programmable Flash for EEPROM emulation
+  - 4/8/16/32 KB SRAM main memory
+
+#### System
+  - Power-on Reset (POR) and Brown-out Detection (BOD)
+  - Internal and external clock options with 48 MHz to 96 MHz Fractional Digital Phase Locked Loop (FDPLL96M)
+  - External Interrupt Controller (EIC) (Interrupt pin debouncing is only available in SAM C20/C21 N)
+  - 16 external interrupts
+  - One non-maskable interrupt
+  - Two-pin Serial Wire Debug (SWD) programming, test, and debugging interface
+
+#### High-Performance Peripherals
+  - Hardware Divide and Square Root Accelerator (DIVAS)
+  - 12-channel Direct Memory Access Controller (DMAC)
+  - 12-channel Event System
+  - Up to eight 16-bit Timer/Counters (TC), configurable as either
+  - Two 24-bit and one 16-bit Timer/Counter for Control (TCC), with extended functions
+  - Frequency Meter (The division reference clock is only available in the SAM C21N)
+  - 32-bit Real Time Counter (RTC) with clock/calendar function
+  - Watchdog Timer (WDT)
+  - CRC-32 generator
+  - Up to two Controller Area Network (CAN) interfaces in the SAM C21
+  - Up to eight Serial Communication Interfaces (SERCOM), each configurable to operate as USART/I2C/SPI
+  - One Configurable Custom Logic (CCL)
+  - Up to Two 12-bit, 1 Msps Analog-to-Digital Converter (ADC) with up to 12 channels each (20 unique channels)
+  - One 16-bit Sigma-Delta Analog-to-Digital Converter (SDADC) with up to 3 differential channels in the SAM C21
+  - 10-bit, 350 ksps Digital-to-Analog Converter (DAC) in the SAM C21
+  - Up to four Analog Comparators (AC) with Window Compare function
+  - Integrated Temperature Sensor in the SAM C21
+  - Peripheral Touch Controller (PTC)
+  - 256-Channel capacitive touch
+
+#### I/O
+  - Up to 84 programmable I/O pins
+
+#### Qualification
+  - AEC - Q100 Grade 1 (-40°C to 125°C)
+
+#### Voltage
+  - 2.7V – 5.5V
+  - -40°C to +125°C, DC to 48 MHz
+  - -40°C to +85°C, DC to 64 MHz
+
+#### Packages
+  - 100-pin TQFP
+  - 64-pin TQFP, VQFN
+  - 56-pin WLCSP
+  - 48-pin TQFP, VQFN
+  - 32-pin TQFP, VQFN
+
+#### Board info
+- [SAM C21 XPLAINED PRO]（https://www.microchip.com/en-us/development-tool/ATSAMC21-XPRO）

bsp/microchip/samc21/README_zh.md

+# SAMC21J18A BSP 介绍
+
+[English](README.md) 
+
+- MCU: ATSAMC21J18A @64MHz, 256KB FLASH, 32KB RAM, 2.7V – 5.5V
+- C21: Cortex-M0+内核 + 丰富外设 + 2路CAN-FD + Delta-Sigma ADC
+- 管脚: N系列-100 pins, J系列-64 pins, G系列-48 pins, E系列-32 pins
+- Flash: 18=256KB, 17=128KB, 16=64KB , 15=32KB(size=2^n)
+- SRAM : 32KB(Flash 256KB), 16KB(Flash 128KB), 8KB(Flash 64KB), 4KB(Flash 32KB)
+## 手册: <https://www.microchip.com/en-us/product/ATSAMC21J18A>
+
+#### KEY FEATURES
+
+#### 内核
+  - 32-bit Arm® Cortex®-M0+ 内核， 主频最高48MHz和64 MHz+单指令周期的硬件乘法器
+
+####  内存
+  - 32/64/128/256 KB in-system self-programmable Flash
+  - 1/2/4/8 KB independent self-programmable Flash for EEPROM emulation
+  - 4/8/16/32 KB SRAM main memory
+
+#### 系统特性
+  - Power-on Reset (POR) and Brown-out Detection (BOD)
+  - Internal and external clock options with 48 MHz to 96 MHz Fractional Digital Phase Locked Loop (FDPLL96M)
+  - External Interrupt Controller (EIC) (Interrupt pin debouncing is only available in SAM C20/C21 N)
+  - 16 external interrupts
+  - One non-maskable interrupt
+  - Two-pin Serial Wire Debug (SWD) programming, test, and debugging interface
+
+#### 高性能外设
+  - Hardware Divide and Square Root Accelerator (DIVAS)
+  - 12-channel Direct Memory Access Controller (DMAC)
+  - 12-channel Event System
+  - Up to eight 16-bit Timer/Counters (TC), configurable as either
+  - Two 24-bit and one 16-bit Timer/Counter for Control (TCC), with extended functions
+  - Frequency Meter (The division reference clock is only available in the SAM C21N)
+  - 32-bit Real Time Counter (RTC) with clock/calendar function
+  - Watchdog Timer (WDT)
+  - CRC-32 generator
+  - Up to two Controller Area Network (CAN) interfaces in the SAM C21
+  - Up to eight Serial Communication Interfaces (SERCOM), each configurable to operate as USART/I2C/SPI
+  - One Configurable Custom Logic (CCL)
+  - Up to Two 12-bit, 1 Msps Analog-to-Digital Converter (ADC) with up to 12 channels each (20 unique channels)
+  - One 16-bit Sigma-Delta Analog-to-Digital Converter (SDADC) with up to 3 differential channels in the SAM C21
+  - 10-bit, 350 ksps Digital-to-Analog Converter (DAC) in the SAM C21
+  - Up to four Analog Comparators (AC) with Window Compare function
+  - Integrated Temperature Sensor in the SAM C21
+  - Peripheral Touch Controller (PTC)
+  - 256-Channel capacitive touch
+
+#### I/O管脚
+  - 最多提供84个用户可编程I/O管脚
+
+#### 汽车应用
+  - AEC - Q100 Grade 1 (-40°C to 125°C)
+
+#### 工作电压
+  - 2.7V – 5.5V
+  - -40°C to +125°C, DC to 48 MHz
+  - -40°C to +85°C, DC to 64 MHz
+
+#### 封装
+  - 100-pin TQFP
+  - 64-pin TQFP, VQFN
+  - 56-pin WLCSP
+  - 48-pin TQFP, VQFN
+  - 32-pin TQFP, VQFN
+
+#### 官方开发板信息
+- [SAM C21 XPLAINED PRO]（https://www.microchip.com/en-us/development-tool/ATSAMC21-XPRO）
\ No newline at end of file

bsp/microchip/samc21/SConscript

+# for module compiling
+import os
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/microchip/samc21/SConstruct

+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rt-thread-' + rtconfig.DEVICE_PART + '.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread-'+ rtconfig.DEVICE_PART + '.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/microchip/samc21/applications/SConscript

+import rtconfig
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/microchip/samc21/applications/can_demo.c

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#include <rtthread.h>
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+#include <shell.h>
+#endif
+
+#include "atmel_start.h"
+#include "driver_init.h"
+#include "utils.h"
+
+#include "can_demo.h"
+
+#ifdef SAM_CAN_EXAMPLE
+
+static volatile enum can_async_interrupt_type can_errors;
+static rt_sem_t   can_txdone;
+static rt_sem_t   can_rxdone;
+static rt_uint8_t can_stack[ 512 ];
+static struct rt_thread can_thread;
+
+/**
+ * @brief    Callback function and should be invoked after call can_async_write.
+ *
+ * @note
+ *
+ * @param    descr is CAN device description.
+ *
+ * @return   None.
+ */
+
+static void can_tx_callback(struct can_async_descriptor *const descr)
+{
+    rt_err_t result;
+
+    rt_interrupt_enter();
+    result = rt_sem_release(can_txdone);
+    if (RT_EOK != result)
+    {
+#ifndef RT_USING_FINSH
+        rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__);
+#endif
+    }
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief    Callback function and should be invoked after remote device send.
+ *
+ * @note     This callback function will be called in CAN interrupt function
+ *
+ * @param    descr is CAN device description.
+ *
+ * @return   None.
+ */
+
+static void can_rx_callback(struct can_async_descriptor *const descr)
+{
+    rt_err_t result;
+
+    rt_interrupt_enter();
+    result = rt_sem_release(can_rxdone);
+    if (RT_EOK != result)
+    {
+#ifndef RT_USING_FINSH
+        rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__);
+#endif
+    }
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief    Callback function and should be invoked after CAN device IRQ handler detects errors happened.
+ *
+ * @note     This callback function will be called in CAN interrupt function
+ *
+ * @param    descr is CAN device description.
+ *
+ * @return   None.
+ */
+
+static void can_err_callback(struct can_async_descriptor *const descr,
+                             enum can_async_interrupt_type type)
+{
+    rt_err_t result;
+
+    if (type == CAN_IRQ_EW)
+    {
+      /* Error warning, Error counter has reached the error warning limit of 96,
+       * An error count value greater than about 96 indicates a heavily disturbed
+       * bus. It may be of advantage to provide means to test for this condition.
+       */
+    }
+    else if (type == CAN_IRQ_EA)
+    {
+        /* Error Active State, The CAN node normally take part in bus communication
+         * and sends an ACTIVE ERROR FLAG when an error has been detected.
+         */
+    }
+    else if (type == CAN_IRQ_EP)
+    {
+        /* Error Passive State, The Can node goes into error passive state if at least
+         * one of its error counters is greater than 127. It still takes part in bus
+         * activities, but it sends a passive error frame only, on errors.
+         */
+    }
+    else if (type == CAN_IRQ_BO)
+    {
+        /* Bus Off State, The CAN node is 'bus off' when the TRANSMIT ERROR COUNT is
+         * greater than or equal to 256.
+         */
+
+        /* Suspend CAN task and re-initialize CAN module. */
+        can_errors = type;
+        rt_interrupt_enter();
+        result = rt_sem_release(can_rxdone);
+        if (RT_EOK != result)
+        {
+#ifndef RT_USING_FINSH
+            rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__);
+#endif
+        }
+        rt_interrupt_leave();
+    }
+    else if (type == CAN_IRQ_DO)
+    {
+        /* Data Overrun in receive queue. A message was lost because the messages in
+         * the queue was not reading and releasing fast enough. There is not enough
+         * space for a new message in receive queue.
+         */
+
+        /* Suggest to delete CAN task and re-initialize it. */
+        can_errors = type;
+        rt_interrupt_enter();
+        result = rt_sem_release(can_rxdone);
+        if (RT_EOK != result)
+        {
+#ifndef RT_USING_FINSH
+            rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__);
+#endif
+        }
+        rt_interrupt_leave();
+    }
+};
+
+/**
+ * @brief    Initialize CAN module before task run.
+ *
+ * @note     This function will set CAN Tx/Rx callback function and filters.
+ *
+ * @param    None.
+ *
+ * @return   None.
+ */
+
+static inline void can_demo_init(void)
+{
+    struct can_filter  filter;
+
+    /**
+     * CAN_Node0_tx_callback callback should be invoked after call
+     * can_async_write, and remote device should receive message with ID=0x45A
+     */
+    can_async_register_callback(&CAN_0, CAN_ASYNC_TX_CB, (FUNC_PTR)can_tx_callback);
+
+    /**
+     * CAN_0_rx_callback callback should be invoked after call
+     * can_async_set_filter and remote device send CAN Message with the same
+     * content as the filter.
+     */
+    can_async_register_callback(&CAN_0, CAN_ASYNC_RX_CB, (FUNC_PTR)can_rx_callback);
+
+
+    /* Should set at least one CAN standard & message filter before enable it. */
+
+    filter.id   = 0x469;
+    filter.mask = 0;
+    can_async_set_filter(&CAN_0, 0, CAN_FMT_STDID, &filter);
+
+    /* If set second standard message filter, should increase filter index
+     * and filter algorithm
+     * For example: index should set to 1, otherwise it will replace filter 0.
+     * can_async_set_filter(&CAN_0, 1, CAN_FMT_STDID, &filter); */
+
+    filter.id   = 0x10000096;
+    filter.mask = 0;
+    can_async_set_filter(&CAN_0, 0, CAN_FMT_EXTID, &filter);
+
+    can_async_enable(&CAN_0);
+}
+
+/**
+ * @brief    CAN task.
+ *
+ * @note     This task will waiting for CAN RX semaphore and then process input.
+ *
+ * @param    parameter - task input parameter.
+ *
+ * @return   None.
+ */
+
+static void can_thread_entry(void* parameter)
+{
+    int32_t  ret;
+    rt_err_t result;
+    uint8_t  data[64];
+    uint32_t count=0;
+    struct can_message msg;
+
+    while (1)
+    {
+#ifndef RT_USING_FINSH
+        rt_kprintf("can task run count : %d\r\n",count);
+#endif
+        count++;
+
+        result = rt_sem_take(can_rxdone, RT_WAITING_FOREVER);
+        if (RT_EOK != result)
+            continue;
+
+        do
+        {
+            /* Process the incoming packet. */
+            ret = can_async_read(&CAN_0, &msg);
+            if (ret == ERR_NONE)
+            {
+#ifndef RT_USING_FINSH
+                rt_kprintf("CAN RX Message is % frame\r\n",
+                           msg.type == CAN_TYPE_DATA ? "data" : "remote");
+                rt_kprintf("CAN RX Message is % frame\r\n",
+                           msg.type == CAN_FMT_STDID ? "Standard" : "Extended");
+                rt_kprintf("can RX Message ID: 0x%X length: %d\r\n", msg.id, msg.len);
+                rt_kprintf("CAN RX Message content: ");
+                for (uint8_t i = 0; i < msg.len; i++)
+                    rt_kprintf("0x%02X ", data[i]);
+                rt_kprintf("\r\n");
+#endif
+            }
+        } while (ret == ERR_NONE); /* Get all data stored in CAN RX FIFO */
+
+        /* CAN task got CAN error message, handler CAN Error Status */
+        if ((can_errors == CAN_IRQ_BO) || (can_errors == CAN_IRQ_DO))
+        {
+            can_async_init(&CAN_0, CAN1);
+        }
+    }
+}
+
+/**
+ * @brief    Call this function will to send a CAN message.
+ *
+ * @note
+ *
+ * @param    msg - message to be sent, timeouts - wait timeouts for Tx completion.
+ *
+ * @return   RT_OK or RT_ERROR.
+ */
+
+rt_err_t can_send_message(struct can_message *msg, rt_uint32_t timeouts)
+{
+    rt_err_t result;
+
+    if (RT_NULL == msg)
+    {
+        rt_kprintf("can_send_message input message error\r\n");
+        return RT_ERROR;
+    }
+
+    can_async_write(&CAN_0, msg);
+    result = rt_sem_take(can_rxdone, timeouts);
+
+    return result;
+}
+
+/**
+ * @brief    Call this function will create a CAN task.
+ *
+ * @note     Should create Tx/Rx semaphore before run task.
+ *
+ * @param    None.
+ *
+ * @return   RT_OK or -RT_ERROR.
+ */
+
+rt_err_t can_demo_run(void)
+{
+    rt_err_t result;
+
+    can_rxdone = rt_sem_create("can_rx", 0, RT_IPC_FLAG_FIFO);
+    if (RT_NULL == can_rxdone)
+    {
+        rt_kprintf("can_rx semaphore create failed\r\n");
+        return (-RT_ERROR);
+    }
+
+    can_txdone = rt_sem_create("can_tx", 0, RT_IPC_FLAG_FIFO);
+    if (RT_NULL == can_txdone)
+    {
+        rt_kprintf("can_tx semaphore create failed\r\n");
+        return (-RT_ERROR);
+    }
+
+    can_demo_init();
+
+    /* initialize CAN thread */
+    result = rt_thread_init(&can_thread,
+                            "can",
+                            can_thread_entry,
+                            RT_NULL,
+                            (rt_uint8_t*)&can_stack[0],
+                            sizeof(can_stack),
+                            RT_THREAD_PRIORITY_MAX/3,
+                            5);
+    if (result == RT_EOK)
+    {
+        rt_thread_startup(&can_thread);
+    }
+
+    return result;
+}
+#endif
+
+/*@}*/

bsp/microchip/samc21/applications/can_demo.h

+/*
+ * Copyright (c)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#ifndef __APPLICATION_CAN_H_
+#define __APPLICATION_CAN_H_
+
+#include <rtthread.h>
+
+/**
+ * @brief External function definitions
+ *
+ */
+rt_err_t can_demo_run(void);
+
+rt_err_t can_send_message(struct can_message *msg, rt_uint32_t timeouts);
+
+#endif // __APPLICATION_CAN_H_

bsp/microchip/samc21/applications/main.c

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#include <rtthread.h>
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+#include <shell.h>
+#endif
+
+#include "atmel_start.h"
+#include <hal_gpio.h>
+
+#ifdef SAM_CAN_EXAMPLE
+#include "can_demo.h"
+#endif
+
+static rt_uint8_t led_stack[ 512 ];
+static struct rt_thread led_thread;
+
+static void led_thread_entry(void* parameter)
+{
+    unsigned int count=0;
+
+    while (1)
+    {
+        /* toggle led */
+#ifndef RT_USING_FINSH
+        rt_kprintf("led toggle, count : %d\r\n",count);
+#endif
+        count++;
+        gpio_toggle_pin_level(LED0);
+        rt_thread_delay( RT_TICK_PER_SECOND/2 ); /* sleep 0.5 second and switch to other thread */
+    }
+}
+
+int main(void)
+{
+    rt_err_t result;
+
+    /* initialize led thread */
+    result = rt_thread_init(&led_thread,
+                            "led",
+                            led_thread_entry,
+                            RT_NULL,
+                            (rt_uint8_t*)&led_stack[0],
+                            sizeof(led_stack),
+                            RT_THREAD_PRIORITY_MAX/3,
+                            5);
+    if (result == RT_EOK)
+    {
+        rt_thread_startup(&led_thread);
+    }
+
+#ifdef SAM_CAN_EXAMPLE
+    can_demo_run();
+#endif
+
+    return 0;
+}
+
+/*@}*/

bsp/microchip/samc21/board/Kconfig

+menu "Hardware Drivers Config"
+
+choice
+    prompt "select chip type"
+    default SOC_SAMC21J18
+
+    config SOC_SAMC21J18
+    bool "SOC_SAMC21J18"
+    help
+        Refer to SAMC21 DataSheet
+
+    config SOC_SAMC21G18
+    bool "SOC_SAMC21G18"
+    help
+        Refer to SAMC21 DataSheet
+
+    config SOC_SAMC21E18
+    bool "SOC_SAMC21E18"
+    help
+        Refer to SAMC21 DataSheet
+
+endchoice 
+endmenu
+
+menu "Onboard Peripheral Drivers"
+    depends on SOC_SAMC21J18
+
+    config SAMC21_CAN0
+        bool "Enable CAN0"
+        default false
+
+    config SAMC21_ADC0
+        bool "Enable ADC0"
+        default false
+endmenu
+
+menu "Application Demo Config"
+    config SAM_CAN_EXAMPLE
+        bool "Enable SAM CAN Example"
+        depends on SAMC21_CAN0
+        default true
+        help
+            Add CAN example task to project
+
+    config SAM_ADC_EXAMPLE
+        bool "Enable SAM ADC Example"
+        depends on SAMC21_ADC0
+        default true
+        help
+            Add ADC example task to project
+
+endmenu

bsp/microchip/samc21/board/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+#remove other no use files
+#SrcRemove(src, '*.c')
+
+# You can select chips from the list above
+CPPDEFINES = ['SAMC21xxx']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')
\ No newline at end of file

bsp/microchip/samc21/board/board.c

+/*
+ * Copyright (c)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#include <string.h>
+
+#include <atmel_start.h>
+#include "peripheral_clk_config.h"
+
+#include <rtthread.h>
+#include "board.h"
+
+#ifdef RT_USING_SERIAL
+extern int rt_hw_uart_init(void);
+#endif
+
+static struct io_descriptor* g_stdio;
+
+void rt_hw_console_output(const char *str)
+{
+    io_write(g_stdio, (uint8_t *)str, strlen(str));
+}
+RTM_EXPORT(rt_hw_console_output);
+
+static inline void hw_board_init_usart(void)
+{
+    usart_sync_get_io_descriptor(&TARGET_IO, &g_stdio);
+    usart_sync_enable(&TARGET_IO);
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * This function will initial SAMC21 board.
+ */
+void rt_hw_board_init(void)
+{
+    /* Initializes MCU, drivers and middleware */
+    atmel_start_init();
+
+    /* enable USART stdout module */
+    hw_board_init_usart();
+
+    /* UART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_uart_init();
+#endif
+
+    /* init systick */
+    SysTick_Config(CONF_CPU_FREQUENCY / RT_TICK_PER_SECOND);
+
+    /* set pend exception priority */
+    NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
+
+#ifdef RT_USING_HEAP
+    #if defined(__CC_ARM) || defined(__CLANG_ARM)
+        rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)HEAP_END);
+    #elif __ICCARM__
+        rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
+    #else
+        /* init memory system */
+        rt_system_heap_init((void*)&__bss_end, (void*)HEAP_END);
+    #endif
+#endif
+
+    /* Set the shell console output device */
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+/*@}*/

bsp/microchip/samc21/board/board.h

+/*
+ * Copyright (c)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+// <o> Internal SRAM memory size[Kbytes] <4-32>
+//  <i>Default: 32
+#if   defined(__SAMC21E15A__) || defined(__ATSAMC21E15A__)
+  #define SAMC21_SRAM_SIZE   4
+#elif defined(__SAMC21E16A__) || defined(__ATSAMC21E16A__)
+  #define SAMC21_SRAM_SIZE   8
+#elif defined(__SAMC21E17A__) || defined(__ATSAMC21E17A__)
+  #define SAMC21_SRAM_SIZE   16
+#elif defined(__SAMC21E18A__) || defined(__ATSAMC21E18A__)
+  #define SAMC21_SRAM_SIZE   32
+#elif defined(__SAMC21G15A__) || defined(__ATSAMC21G15A__)
+  #define SAMC21_SRAM_SIZE   4
+#elif defined(__SAMC21G16A__) || defined(__ATSAMC21G16A__)
+  #define SAMC21_SRAM_SIZE   8
+#elif defined(__SAMC21G17A__) || defined(__ATSAMC21G17A__)
+  #define SAMC21_SRAM_SIZE   16
+#elif defined(__SAMC21G18A__) || defined(__ATSAMC21G18A__)
+  #define SAMC21_SRAM_SIZE   32
+#elif defined(__SAMC21J15A__) || defined(__ATSAMC21J15A__)
+  #define SAMC21_SRAM_SIZE   4
+#elif defined(__SAMC21J16A__) || defined(__ATSAMC21J16A__)
+  #define SAMC21_SRAM_SIZE   8
+#elif defined(__SAMC21J17A__) || defined(__ATSAMC21J17A__)
+  #define SAMC21_SRAM_SIZE   16
+#elif defined(__SAMC21J17AU__) || defined(__ATSAMC21J17AU__)
+  #define SAMC21_SRAM_SIZE   16
+#elif defined(__SAMC21J18A__) || defined(__ATSAMC21J18A__)
+  #define SAMC21_SRAM_SIZE   32
+#elif defined(__SAMC21J18AU__) || defined(__ATSAMC21J18AU__)
+  #define SAMC21_SRAM_SIZE   32
+#else
+  #error Board does not support the specified device.
+#endif
+
+#define SAMC21_SRAM_END        (0x20000000 + SAMC21_SRAM_SIZE * 1024)
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN    (__segment_begin("HEAP"))
+#define HEAP_END      (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN    (&__bss_end)
+#define HEAP_END      SAMC21_SRAM_END
+#endif
+
+void rt_hw_board_init(void);
+
+#endif
+

bsp/microchip/samc21/board/serial.c

+/*
+ * Copyright (c)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include <atmel_start.h>
+
+/* SAM MCU serial device */
+static struct rt_serial_device sam_serial;
+
+/**
+ * @brief Configure serial port
+ *
+ * This function will configure UART baudrate, parity and so on.
+ *
+ * @return RT_EOK.
+ */
+static rt_err_t serial_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct usart_sync_descriptor* desc;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    desc = (struct usart_sync_descriptor *)serial->parent.user_data;
+
+    RT_ASSERT(desc != RT_NULL);
+    RT_ASSERT(cfg  != RT_NULL);
+
+    usart_sync_disable(desc);
+
+    /* Set baudrate */
+    usart_sync_set_baud_rate(desc, (const uint32_t)cfg->baud_rate);
+
+    /* Set stop bit */
+    if (cfg->stop_bits == STOP_BITS_1)
+        usart_sync_set_stopbits(desc, USART_STOP_BITS_ONE);
+    else if (cfg->stop_bits == STOP_BITS_2)
+        usart_sync_set_stopbits(desc, USART_STOP_BITS_TWO);
+
+    if (cfg->bit_order == BIT_ORDER_LSB)
+        usart_sync_set_data_order(desc, USART_DATA_ORDER_LSB);
+    else if (cfg->bit_order == BIT_ORDER_MSB)
+        usart_sync_set_data_order(desc, USART_DATA_ORDER_MSB);
+
+    /* Set character size */
+    switch (cfg->data_bits)
+    {
+        case DATA_BITS_5:
+            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_5BITS);
+            break;
+        case DATA_BITS_6:
+            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_6BITS);
+            break;
+        case DATA_BITS_7:
+            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_7BITS);
+            break;
+        case DATA_BITS_8:
+            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_8BITS);
+            break;
+        case DATA_BITS_9:
+            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_9BITS);
+            break;
+        default:
+            break;
+    }
+
+    if (cfg->parity == PARITY_NONE)
+        usart_sync_set_parity(desc, USART_PARITY_NONE);
+    else if (cfg->parity == PARITY_ODD)
+        usart_sync_set_parity(desc, USART_PARITY_ODD);
+    else if (cfg->parity == PARITY_EVEN)
+        usart_sync_set_parity(desc, USART_PARITY_EVEN);
+
+    usart_sync_enable(desc);
+
+    return RT_EOK;
+}
+
+/**
+ * @brief Control serial port
+ *
+ * This function provide UART enable/disable control.
+ *
+ * @return RT_EOK.
+ */
+static rt_err_t serial_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct usart_sync_descriptor* desc;
+
+    RT_ASSERT(serial != RT_NULL);
+    desc = (struct usart_sync_descriptor *)serial->parent.user_data;
+
+    RT_ASSERT(desc != RT_NULL);
+
+    switch (cmd)
+    {
+        /* disable interrupt */
+        case RT_DEVICE_CTRL_CLR_INT:
+            usart_sync_disable(desc);
+            break;
+        /* enable interrupt */
+        case RT_DEVICE_CTRL_SET_INT:
+            usart_sync_enable(desc);
+            break;
+        /* UART config */
+        case RT_DEVICE_CTRL_CONFIG :
+            break;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * @brief Serial sends a char
+ *
+ * This function will send a char to the UART
+ *
+ * @return 1.
+ */
+static int serial_putc(struct rt_serial_device *serial, char c)
+{
+    struct usart_sync_descriptor* desc;
+
+    RT_ASSERT(serial != RT_NULL);
+    desc = (struct usart_sync_descriptor *)serial->parent.user_data;
+
+    RT_ASSERT(desc != RT_NULL);
+
+    io_write(&desc->io, (const uint8_t *)&c, 1);
+
+    return 1;
+}
+
+/**
+ * @brief Serial gets a char
+ *
+ * This function will get a char from the UART
+ *
+ * @return received char character or -1 if no char received.
+ */
+static int serial_getc(struct rt_serial_device *serial)
+{
+    char c;
+    int ch;
+    struct usart_sync_descriptor* desc;
+
+    RT_ASSERT(serial != RT_NULL);
+    desc = (struct usart_sync_descriptor *)serial->parent.user_data;
+
+    RT_ASSERT(desc != RT_NULL);
+
+    ch = -1;
+    if (usart_sync_is_rx_not_empty(desc))
+    {
+        io_read(&desc->io, (uint8_t *)&c, 1);;
+        ch = c & 0xff;
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops sam_serial_ops =
+{
+    serial_configure,
+    serial_control,
+    serial_putc,
+    serial_getc,
+};
+
+/**
+ * @brief Initialize the UART
+ *
+ * This function initialize the UART
+ *
+ * @return None.
+ */
+int rt_hw_uart_init(void)
+{
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+    sam_serial.ops       = &sam_serial_ops;
+    sam_serial.config    = config;
+    sam_serial.serial_rx = RT_NULL;
+    sam_serial.serial_rx = RT_NULL;
+    rt_hw_serial_register(&sam_serial, "uart0",
+                          RT_DEVICE_FLAG_RDWR, (void *)&TARGET_IO);
+
+    return 0;
+}
+
+/*@}*/

bsp/microchip/samc21/board/serial.h

+/*
+ * Copyright (c)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#ifndef __BOARD_SERIAL_H_
+#define __BOARD_SERIAL_H_
+
+#include <rtthread.h>
+
+/**
+ * @brief External function definitions
+ *
+ */
+int rt_hw_uart_init(void);
+
+#endif // __BOARD_SERIAL_H_

bsp/microchip/samc21/bsp/AtmelStart.env_conf

+<environment>
+  <configurations/>
+  <device-packs>
+    <device-pack device="ATSAMC21J18A" name="SAMC21_DFP" vendor="Atmel" version="1.2.176"/>
+  </device-packs>
+</environment>

bsp/microchip/samc21/bsp/AtmelStart.gpdsc

+<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="PACK.xsd">
+  <vendor>Atmel</vendor>
+  <name>SAMC21 LED switcher</name>
+  <description>Project generated by Atmel Start</description>
+  <url>http://start.atmel.com/</url>
+  <releases>
+    <release version="1.0.1">Initial version</release>
+  </releases>
+  <taxonomy>
+    <description Cclass="AtmelStart" generator="AtmelStart">Configuration Files generated by Atmel Start</description>
+  </taxonomy>
+  <generators>
+    <generator id="AtmelStart">
+      <description>Atmel Start</description>
+      <select Dname="ATSAMC21J18A" Dvendor="Atmel:3"/>
+      <command>http://start.atmel.com/</command>
+      <files>
+        <file category="generator" name="atmel_start_config.atstart"/>
+        <file attr="template" category="other" name="AtmelStart.env_conf" select="Environment configuration"/>
+      </files>
+    </generator>
+  </generators>
+  <conditions>
+    <condition id="CMSIS Device Startup">
+      <description>Dependency on CMSIS core and Device Startup components</description>
+      <require Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.2"/>
+      <require Cclass="Device" Cgroup="Startup" Cversion="1.2.0"/>
+    </condition>
+    <condition id="ARMCC, GCC, IAR">
+      <require Dname="ATSAMC21J18A"/>
+      <accept Tcompiler="ARMCC"/>
+      <accept Tcompiler="GCC"/>
+      <accept Tcompiler="IAR"/>
+    </condition>
+    <condition id="GCC">
+      <require Dname="ATSAMC21J18A"/>
+      <accept Tcompiler="GCC"/>
+    </condition>
+  </conditions>
+  <components generator="AtmelStart">
+    <component Cclass="AtmelStart" Cgroup="Framework" Cversion="1.0.0" condition="CMSIS Device Startup">
+      <description>Atmel Start Framework</description>
+      <RTE_Components_h>#define ATMEL_START</RTE_Components_h>
+      <files>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/can_async.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/flash.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/usart_sync.rst"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_can_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_delay.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_flash.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_gpio.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_init.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_io.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_can.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_can_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_core.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_delay.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_div.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_dma.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_flash.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_gpio.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_init.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_irq.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_sleep.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_user_area.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_atomic.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_can_async.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_delay.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_flash.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/compiler.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/err_codes.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/events.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_assert.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_event.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
+        <file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/divas/hpl_divas.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ac_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_adc_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_can_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ccl_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dac_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_divas_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dmac_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dsu_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_eic_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_evsys_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_freqm_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_gclk_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_hmatrixb_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_mclk_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_mpu_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_mtb_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_nvic_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_nvmctrl_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_osc32kctrl_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_oscctrl_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pac_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pm_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_port_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rstc_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rtc_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sdadc_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sercom_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_supc_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_systemcontrol_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_systick_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tc_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tcc_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tsens_c21.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_wdt_c21.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="main.c"/>
+        <file category="other" condition="ARMCC, GCC, IAR" name="documentation/rww_flash.rst/"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="driver_init.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="driver_init.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="atmel_start_pins.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="examples/driver_examples.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="config/hpl_divas_config.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_usart_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_reset.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_dma.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_sync.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_usart_sync.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/can/hpl_can.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/can/hpl_can_base.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_m0plus_base.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_port.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_init.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/dmac/hpl_dmac.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk_base.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/mclk/hpl_mclk.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/nvmctrl/hpl_nvmctrl.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl/hpl_osc32kctrl.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/oscctrl/hpl_oscctrl.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm_base.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/port/hpl_gpio_base.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_can_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_dmac_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gclk_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_mclk_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_nvmctrl_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_osc32kctrl_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_oscctrl_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_port_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_sercom_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/peripheral_clk_config.h"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name=""/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="config"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="examples"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hal/include"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hal/utils/include"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/can"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/core"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/divas"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/dmac"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/gclk"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/mclk"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/nvmctrl"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/oscctrl"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/pm"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/port"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/sercom"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hri"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name=""/>
+      </files>
+    </component>
+  </components>
+</package>

bsp/microchip/samc21/bsp/atmel_start.c

+#include <atmel_start.h>
+
+/**
+ * Initializes MCU, drivers and middleware in the project
+ **/
+void atmel_start_init(void)
+{
+	system_init();
+}