更正stm32/stm32f103-100ask-mini和pro的默认下载器为st-link，添加基于mm32f3270系列由百问网自主设计的火龙果开发板的bsp

.github/workflows/action.yml

@@ -86,6 +86,7 @@ jobs:
          - {RTT_BSP: "fujitsu/mb9x/mb9bf618s", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "fujitsu/mb9x/mb9bf568r", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "mini2440", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "mm32/mm32f3270-100ask-pitaya", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "nrf5x/nrf51822", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "nrf5x/nrf52832", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "nrf5x/nrf52833", RTT_TOOL_CHAIN: "sourcery-arm"}

bsp/mm32/README.md

+# MM32 BSP 说明
+
+MM32 系列 BSP 目前支持情况如下表所示：
+
+| **BSP 文件夹名称**       | **开发板名称**                 |
+|:------------------------- |:-------------------------- |
+| **F3270 系列** |  |
+| [mm32f3270-100ask-pitaya](mm32f3270-100ask-pitaya) | 百问网MM32F3273G8P火龙果开发板 |
+
+可以通过阅读相应 BSP 下的 README 来快速上手。
\ No newline at end of file

bsp/mm32/libraries/HAL_Drivers/Kconfig

+if BSP_USING_USBD
+    config BSP_USBD_TYPE_FS
+        bool
+        # "USB Full Speed (FS) Core"
+    config BSP_USBD_TYPE_HS
+        bool
+        # "USB High Speed (HS) Core"
+
+    config BSP_USBD_SPEED_HS
+        bool 
+        # "USB High Speed (HS) Mode"
+    config BSP_USBD_SPEED_HSINFS
+        bool 
+        # "USB High Speed (HS) Core in FS mode"
+
+    config BSP_USBD_PHY_EMBEDDED
+        bool 
+        # "Using Embedded phy interface"
+    config BSP_USBD_PHY_UTMI
+        bool 
+        # "UTMI: USB 2.0 Transceiver Macrocell Interace"
+    config BSP_USBD_PHY_ULPI
+        bool 
+        # "ULPI: UTMI+ Low Pin Interface"
+endif

bsp/mm32/libraries/HAL_Drivers/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+""")
+
+if GetDepend(['RT_USING_PIN']):
+    src += ['drv_gpio.c']
+
+if GetDepend(['RT_USING_SERIAL']):
+        src += ['drv_uart.c']
+
+src += ['drv_common.c']
+
+path =  [cwd]
+path += [cwd + '/config']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/mm32/libraries/HAL_Drivers/config/mm32f3277g8p/dma_config.h

+/**
+ * @file dma_config.h
+ * @author 100ask development team
+ * @brief 
+ * @version 0.1
+ * @date 2022-06-16
+ * 
+ * @copyright Copyright (c) 2022 Chongqing 100ASK Technology Co., LTD
+ * 
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 channel1 */
+#if defined(BSP_ADC1_USING_DMA) && !defined(ADC1_DMA_INSTANCE)
+#define ADC1_DMA_INSTANCE               DMA1
+#define ADC1_DMA_REQ                    DMA_REQ_DMA1_ADC1
+#define ADC1_DMA_IRQ                    DMA1_CH1_IRQn
+#define ADC1_DMA_IRQHandler             DMA1_Channel1_IRQHandler
+#define ADC1_DMA_RCC                    RCC_AHB1_PERIPH_DMA1
+#elif defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE)
+#define UART6_DMA_INSTANCE              DMA1
+#define UART6_RX_DMA_REQ                DMA_REQ_DMA1_UART6_RX
+#define UART6_RX_DMA_IRQ                DMA1_CH1_IRQn
+#define UART6_DMA_RX_IRQHandler         DMA1_Channel1_IRQHandler
+#define UART6_RX_DMA_RCC                RCC_AHB1_PERIPH_DMA1
+#endif
+
+/* DMA1 channel2 */
+#if defined(BSP_ADC2_USING_DMA) && !defined(ADC2_DMA_INSTANCE)
+#define ADC2_DMA_INSTANCE               DMA1
+#define ADC2_DMA_REQ                    DMA_REQ_DMA1_ADC2
+#define ADC2_DMA_IRQ                    DMA1_CH2_IRQn
+#define ADC2_DMA_IRQHandler             DMA1_Channel2_IRQHandler
+#define ADC2_DMA_RCC                    RCC_AHB1_PERIPH_DMA1
+#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_RX_DMA_INSTANCE            DMA1
+#define SPI1_RX_DMA_REQ                 DMA_REQ_DMA1_SPI1_RX
+#define SPI1_RX_DMA_IRQ                 DMA1_CH2_IRQn
+#define SPI1_DMA_RX_IRQHandler          DMA1_Channel2_IRQHandler
+#define SPI1_RX_DMA_RCC                 RCC_AHB1_PERIPH_DMA1
+#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
+#define UART3_TX_DMA_INSTANCE           DMA1
+#define UART3_TX_DMA_REQ                DMA_REQ_DMA1_UART3_TX
+#define UART3_TX_DMA_IRQ                DMA1_CH2_IRQn
+#define UART3_DMA_TX_IRQHandler         DMA1_Channel2_IRQHandler
+#define UART3_TX_DMA_RCC                RCC_AHB1_PERIPH_DMA1
+#endif
+
+/* DMA1 channel3 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_TX_DMA_INSTANCE            DMA1
+#define SPI1_TX_DMA_REQ                 DMA_REQ_DMA1_SPI1_TX
+#define SPI1_TX_DMA_IRQ                 DMA1_CH3_IRQn
+#define SPI1_DMA_TX_IRQHandler          DMA1_Channel3_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHB1_PERIPH_DMA1
+#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_RX_DMA_INSTANCE           DMA1
+#define UART3_RX_DMA_REQ                DMA_REQ_DMA1_UART3_RX
+#define UART3_RX_DMA_IRQ                DMA1_CH3_IRQn
+#define UART3_DMA_RX_IRQHandler         DMA1_Channel3_IRQHandler
+#define UART3_RX_DMA_RCC                RCC_AHB1_PERIPH_DMA1
+#endif
+
+/* DMA1 channel4 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_RX_DMA_INSTANCE            DMA1
+#define SPI2_RX_DMA_REQ                 DMA_REQ_DMA1_SPI2_RX
+#define SPI2_RX_DMA_IRQ                 DMA1_CH4_IRQn
+#define SPI2_DMA_RX_IRQHandler          DMA1_Channel4_IRQHandler
+#define SPI2_RX_DMA_RCC                 RCC_AHB1_PERIPH_DMA1
+#elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_TX_DMA_INSTANCE           DMA1
+#define UART1_TX_DMA_REQ                DMA_REQ_DMA1_UART1_TX
+#define UART1_TX_DMA_IRQ                DMA1_CH4_IRQn
+#define UART1_DMA_TX_IRQHandler         DMA1_Channel4_IRQHandler
+#define UART1_TX_DMA_RCC                RCC_AHB1_PERIPH_DMA1
+#endif
+
+/* DMA1 channel5 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_TX_DMA_INSTANCE            DMA1
+#define SPI2_TX_DMA_REQ                 DMA_REQ_DMA1_SPI2_TX
+#define SPI2_TX_DMA_IRQ                 DMA1_CH5_IRQn
+#define SPI2_DMA_TX_IRQHandler          DMA1_Channel5_IRQHandler
+#define SPI2_TX_DMA_RCC                 RCC_AHB1_PERIPH_DMA1
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_RX_DMA_INSTANCE           DMA1
+#define UART1_RX_DMA_REQ                DMA_REQ_DMA1_UART1_RX
+#define UART1_RX_DMA_IRQ                DMA1_CH5_IRQn
+#define UART1_DMA_RX_IRQHandler         DMA1_Channel5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1_PERIPH_DMA1
+#endif
+
+/* DMA1 channel6 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART6_RX_DMA_INSTANCE           DMA1
+#define UART6_RX_DMA_REQ                DMA_REQ_DMA1_UART6_RX
+#define UART6_RX_DMA_IRQ                DMA1_CH6_IRQn
+#define UART6_DMA_RX_IRQHandler         DMA1_Channel6_IRQHandler
+#define UART6_RX_DMA_RCC                RCC_AHB1_PERIPH_DMA1
+#endif
+
+/* DMA1 channel7 */
+#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
+#define UART2_TX_DMA_INSTANCE           DMA1
+#define UART2_TX_DMA_REQ                DMA_REQ_DMA1_UART2_TX
+#define UART2_TX_DMA_IRQ                DMA1_CH7_IRQn
+#define UART2_DMA_TX_IRQHandler         DMA1_Channel7_IRQHandler
+#define UART2_TX_DMA_RCC                RCC_AHB1_PERIPH_DMA1
+#endif
+
+/* DMA2 channel1 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_RX_DMA_INSTANCE            DMA2
+#define SPI3_RX_DMA_REQ                 DMA_REQ_DMA2_SPI3_RX
+#define SPI3_RX_DMA_IRQ                 DMA2_CH1_IRQn
+#define SPI3_DMA_RX_IRQHandler          DMA2_Channel1_IRQHandler
+#define SPI3_RX_DMA_RCC                 RCC_AHB1_PERIPH_DMA2
+#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_RX_DMA_INSTANCE           DMA2
+#define UART5_RX_DMA_REQ                DMA_REQ_DMA2_UART5_RX
+#define UART5_RX_DMA_IRQ                DMA2_CH1_IRQn
+#define UART5_DMA_RX_IRQHandler         DMA2_Channel1_IRQHandler
+#define UART5_RX_DMA_RCC                RCC_AHB1_PERIPH_DMA2
+#elif defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE)
+#define UART7_RX_DMA_INSTANCE           DMA2
+#define UART7_RX_DMA_REQ                DMA_REQ_DMA2_UART7_RX
+#define UART7_RX_DMA_IRQ                DMA2_CH1_IRQn
+#define UART7_DMA_RX_IRQHandler         DMA2_Channel1_IRQHandler
+#define UART7_RX_DMA_RCC                RCC_AHB1_PERIPH_DMA2
+#endif
+
+/* DMA2 channel2 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_TX_DMA_INSTANCE            DMA2
+#define SPI3_TX_DMA_REQ                 DMA_REQ_DMA2_SPI3_TX
+#define SPI3_TX_DMA_IRQ                 DMA2_CH2_IRQn
+#define SPI3_DMA_TX_IRQHandler          DMA2_Channel2_IRQHandler
+#define SPI3_TX_DMA_RCC                 RCC_AHB1_PERIPH_DMA2
+#elif defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
+#define UART5_TX_DMA_INSTANCE           DMA2
+#define UART5_TX_DMA_REQ                DMA_REQ_DMA2_UART5_TX
+#define UART5_TX_DMA_IRQ                DMA2_CH2_IRQn
+#define UART5_DMA_TX_IRQHandler         DMA2_Channel2_IRQHandler
+#define UART5_TX_DMA_RCC                RCC_AHB1_PERIPH_DMA2
+#elif defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE)
+#define UART7_TX_DMA_INSTANCE           DMA2
+#define UART7_TX_DMA_REQ                DMA_REQ_DMA2_UART7_TX
+#define UART7_TX_DMA_IRQ                DMA2_CH2_IRQn
+#define UART7_DMA_TX_IRQHandler         DMA2_Channel2_IRQHandler
+#define UART7_TX_DMA_RCC                RCC_AHB1_PERIPH_DMA2
+#endif
+
+/* DMA2 channel3 */
+#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_RX_DMA_INSTANCE           DMA2
+#define UART4_RX_DMA_REQ                DMA_REQ_DMA2_UART4_RX
+#define UART4_RX_DMA_IRQ                DMA2_CH3_IRQn
+#define UART4_DMA_RX_IRQHandler         DMA2_Channel3_IRQHandler
+#define UART4_RX_DMA_RCC                RCC_AHB1_PERIPH_DMA2
+#elif defined(BSP_UART8_RX_USING_DMA) && !defined(UART8_RX_DMA_INSTANCE)
+#define UART8_RX_DMA_INSTANCE           DMA2
+#define UART8_RX_DMA_REQ                DMA_REQ_DMA2_UART8_RX
+#define UART8_RX_DMA_IRQ                DMA2_CH3_IRQn
+#define UART8_DMA_RX_IRQHandler         DMA2_Channel3_IRQHandler
+#define UART8_RX_DMA_RCC                RCC_AHB1_PERIPH_DMA2
+#endif
+
+/* DMA2 channel4 */
+#if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE)
+#define UART6_TX_DMA_INSTANCE           DMA2
+#define UART6_TX_DMA_REQ                DMA_REQ_DMA2_UART6_TX
+#define UART6_TX_DMA_IRQ                DMA2_CH4_IRQn
+#define UART6_DMA_TX_IRQHandler         DMA2_Channel4_IRQHandler
+#define UART6_TX_DMA_RCC                RCC_AHB1_PERIPH_DMA2
+#endif
+
+/* DMA2 channel5 */
+#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
+#define UART4_TX_DMA_INSTANCE           DMA2
+#define UART4_TX_DMA_REQ                DMA_REQ_DMA2_UART4_TX
+#define UART4_TX_DMA_IRQ                DMA2_CH5_IRQn
+#define UART4_DMA_TX_IRQHandler         DMA2_Channel5_IRQHandler
+#define UART4_TX_DMA_RCC                RCC_AHB1_PERIPH_DMA2
+#elif defined(BSP_UART8_TX_USING_DMA) && !defined(UART8_TX_DMA_INSTANCE)
+#define UART8_TX_DMA_INSTANCE           DMA2
+#define UART8_TX_DMA_REQ                DMA_REQ_DMA2_UART8_TX
+#define UART8_TX_DMA_IRQ                DMA2_CH5_IRQn
+#define UART8_DMA_TX_IRQHandler         DMA2_Channel5_IRQHandler
+#define UART8_TX_DMA_RCC                RCC_AHB1_PERIPH_DMA2
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */
+

bsp/mm32/libraries/HAL_Drivers/config/mm32f3277g8p/spi_config.h

+/**
+ * @file spi_config.h
+ * @author 100ask development team
+ * @brief 
+ * @version 0.1
+ * @date 2022-06-16
+ * 
+ * @copyright Copyright (c) 2022 Chongqing 100ASK Technology Co., LTD
+ * 
+ */
+
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_port = SPI1_TX_DMA_PORT,               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI2_TX_DMA_RCC,                \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .dma_irq  = SPI2_TX_DMA_IRQ,                \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI2_RX_DMA_RCC,                \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .dma_irq  = SPI2_RX_DMA_IRQ,                \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI3,                           \
+        .bus_name = "spi3",                         \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+    
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI3_TX_DMA_RCC,                \
+        .Instance = SPI3_TX_DMA_INSTANCE,           \
+        .dma_irq  = SPI3_TX_DMA_IRQ,                \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI3_RX_DMA_RCC,                \
+        .Instance = SPI3_RX_DMA_INSTANCE,           \
+        .dma_irq  = SPI3_RX_DMA_IRQ,                \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
+

bsp/mm32/libraries/HAL_Drivers/config/mm32f3277g8p/uart_config.h

+/*
+ * Copyright (c) 2020-2022, CQ 100ask Development Team
+ *
+ * Change Logs:
+ *   Date           Author          Notes
+ * 2022-05-29        Alen       first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = UART1,                                         \
+        .irq_type = UART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = UART2,                                         \
+        .irq_type = UART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = UART3,                                         \
+        .irq_type = UART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#endif /* UART4_CONFIG */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+    
+#if defined(BSP_USING_UART6)
+#ifndef UART6_CONFIG
+#define UART6_CONFIG                                                \
+    {                                                               \
+        .name = "uart6",                                            \
+        .Instance = UART6,                                          \
+        .irq_type = UART6_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+    
+#if defined(BSP_USING_UART7)
+#ifndef UART7_CONFIG
+#define UART7_CONFIG                                                \
+    {                                                               \
+        .name = "uart7",                                            \
+        .Instance = UART7,                                          \
+        .irq_type = UART7_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+    
+#if defined(BSP_USING_UART8)
+#ifndef UART8_CONFIG
+#define UART8_CONFIG                                                \
+    {                                                               \
+        .name = "uart8",                                            \
+        .Instance = UART8,                                          \
+        .irq_type = UART8_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/mm32/libraries/HAL_Drivers/drv_common.c

+/*
+ * Copyright (c) 2020-2022, CQ 100ask Development Team
+ *
+ * Change Logs:
+ *   Date           Author          Notes
+ * 2022-05-29        Alen       first version
+ */
+
+#include "drv_common.h"
+
+#define DBG_TAG    "drv_common"
+#define DBG_LVL    DBG_INFO
+#include <rtdbg.h>
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+static void reboot(uint8_t argc, char **argv)
+{
+    rt_hw_cpu_reset();
+}
+MSH_CMD_EXPORT(reboot, Reboot System);
+#endif /* RT_USING_FINSH */
+
+volatile uint32_t uwTick;
+static uint32_t _systick_ms = 1;
+void HAL_IncTick(void);
+
+/* SysTick configuration */
+void rt_hw_systick_init(void)
+{
+    uint32_t prioritygroup = 0x00U;
+    uint32_t SystemCoreClock = HAL_GetSysClockFreq();
+    /* Configure the SysTick to have interrupt in 1ms time basis*/
+    if(SysTick_Config(SystemCoreClock/1000) > 0)
+    {
+        return;
+    }
+    /* Configure the SysTick IRQ priority */
+    prioritygroup = NVIC_GetPriorityGrouping();
+    NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(prioritygroup, 15, 0));
+
+    _systick_ms = 1000u / RT_TICK_PER_SECOND;
+    if(_systick_ms == 0)
+        _systick_ms = 1;
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)
+        HAL_IncTick();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void HAL_IncTick(void)
+{
+    uwTick += _systick_ms;
+}
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @param  None
+  * @retval None
+  */
+void _Error_Handler(char *s, int num)
+{
+    /* USER CODE BEGIN Error_Handler */
+    /* User can add his own implementation to report the HAL error return state */
+    LOG_E("Error_Handler at file:%s num:%d", s, num);
+    while (1)
+    {
+    }
+    /* USER CODE END Error_Handler */
+}
+
+/**
+ * This function will delay for some us.
+ *
+ * @param us the delay time of us
+ */
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    rt_uint32_t ticks;
+    rt_uint32_t told, tnow, tcnt = 0;
+    rt_uint32_t reload = SysTick->LOAD;
+
+    ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
+    told = SysTick->VAL;
+    while (1)
+    {
+        tnow = SysTick->VAL;
+        if (tnow != told)
+        {
+            if (tnow < told)
+            {
+                tcnt += told - tnow;
+            }
+            else
+            {
+                tcnt += reload - tnow + told;
+            }
+            told = tnow;
+            if (tcnt >= ticks)
+            {
+                break;
+            }
+        }
+    }
+}
+
+/**
+ * This function will initial STM32 board.
+ */
+RT_WEAK void rt_hw_board_init()
+{
+#ifdef BSP_SCB_ENABLE_I_CACHE
+    /* Enable I-Cache---------------------------------------------------------*/
+    SCB_EnableICache();
+#endif
+
+#ifdef BSP_SCB_ENABLE_D_CACHE
+    /* Enable D-Cache---------------------------------------------------------*/
+    SCB_EnableDCache();
+#endif
+
+    /* System clock initialization */
+    SystemClock_Config();
+    
+    rt_hw_systick_init();
+
+    /* Heap initialization */
+#if defined(RT_USING_HEAP)
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+
+    /* Pin driver initialization is open by default */
+#ifdef RT_USING_PIN
+    rt_hw_pin_init();
+#endif
+
+    /* USART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_uart_init();
+#endif
+
+    /* Set the shell console output device */
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+    /* Board underlying hardware initialization */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+

bsp/mm32/libraries/HAL_Drivers/drv_common.h

+/*
+ * Copyright (c) 2020-2022, CQ 100ask Development Team
+ *
+ * Change Logs:
+ *   Date           Author          Notes
+ * 2022-05-29        Alen       first version
+ */
+
+#ifndef __DRV_COMMON_H__
+#define __DRV_COMMON_H__
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include <board.h>
+
+#include <hal_common.h>
+#include <hal_dma.h>
+#include <hal_rcc.h>
+
+#ifdef RT_USING_PIN
+#include <hal_exti.h>
+#include <hal_syscfg.h>
+#include <hal_gpio.h>
+#endif
+
+#ifdef RT_USING_SERIAL
+#include <hal_uart.h>
+#endif
+
+#ifdef RT_USING_SPI
+#include <hal_spi.h>
+#endif
+
+#ifdef RT_USING_DEVICE
+#include <rtdevice.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _Error_Handler(char *s, int num);
+
+#ifndef Error_Handler
+#define Error_Handler() _Error_Handler(__FILE__, __LINE__)
+#endif
+
+#define DMA_NOT_AVAILABLE ((DMA_INSTANCE_TYPE *)0xFFFFFFFFU)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/mm32/libraries/HAL_Drivers/drv_config.h

+/*
+ * Copyright (c) 2020-2022, CQ 100ask Development Team
+ *
+ * Change Logs:
+ *   Date           Author          Notes
+ * 2022-05-29        Alen       first version
+ */
+
+#ifndef __DRV_CONFIG_H__
+#define __DRV_CONFIG_H__
+
+#include <board.h>
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(SOC_SERIES_MM32F3277)
+#include "mm32f3277g8p/dma_config.h"
+#include "mm32f3277g8p/uart_config.h"
+#include "mm32f3277g8p/spi_config.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/mm32/libraries/HAL_Drivers/drv_dma.h

+/**
+ * @file drv_dma.h
+ * @author 100ask development team
+ * @brief 
+ * @version 0.1
+ * @date 2022-06-16
+ * 
+ * @copyright Copyright (c) 2022 Chongqing 100ASK Technology Co., LTD
+ * 
+ */
+
+#ifndef __DRV_DMA_H_
+#define __DRV_DMA_H_
+
+#include <rtthread.h>
+#include "drv_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct dma_config {
+    DMA_Type *dma_port;
+    rt_uint32_t dma_req;
+    IRQn_Type dma_irq;
+    rt_uint32_t dma_rcc;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__DRV_DMA_H_ */

bsp/mm32/libraries/HAL_Drivers/drv_gpio.c

+/*
+ * Copyright (c) 2020-2022, CQ 100ask Development Team
+ *
+ * Change Logs:
+ *   Date           Author          Notes
+ * 2022-05-29        Alen       first version
+ */
+
+#include "drv_gpio.h"
+
+#ifdef RT_USING_PIN
+
+#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu)))
+#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
+#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
+
+#define PIN_STPORT(pin) ((GPIO_Type *)(GPIOA_BASE + (0x400u * PIN_PORT(pin))))
+
+#define PIN_STPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
+
+
+#if defined(GPIOF)
+#define __MM32_PORT_MAX 6u
+#elif defined(GPIOE)
+#define __MM32_PORT_MAX 5u
+#elif defined(GPIOD)
+#define __MM32_PORT_MAX 4u
+#elif defined(GPIOC)
+#define __MM32_PORT_MAX 3u
+#elif defined(GPIOB)
+#define __MM32_PORT_MAX 2u
+#elif defined(GPIOA)
+#define __MM32_PORT_MAX 1u
+#else
+#define __MM32_PORT_MAX 0u
+#error Unsupported MM32 GPIO peripheral.
+#endif
+
+#define PIN_STPORT_MAX __MM32_PORT_MAX
+
+#define GET_EXTI_PORT(PORT) 
+
+static const struct pin_irq_map pin_irq_map[] =
+{
+    {GPIO_PIN_0, EXTI0_IRQn, EXTI_LINE_0, SYSCFG_EXTILine_0},
+    {GPIO_PIN_1, EXTI1_IRQn, EXTI_LINE_1, SYSCFG_EXTILine_1},
+    {GPIO_PIN_2, EXTI2_IRQn, EXTI_LINE_2, SYSCFG_EXTILine_2},
+    {GPIO_PIN_3, EXTI3_IRQn, EXTI_LINE_3, SYSCFG_EXTILine_3},
+    {GPIO_PIN_4, EXTI4_IRQn, EXTI_LINE_4, SYSCFG_EXTILine_4},
+    {GPIO_PIN_5, EXTI9_5_IRQn, EXTI_LINE_5,SYSCFG_EXTILine_5},
+    {GPIO_PIN_6, EXTI9_5_IRQn, EXTI_LINE_6, SYSCFG_EXTILine_6},
+    {GPIO_PIN_7, EXTI9_5_IRQn, EXTI_LINE_7, SYSCFG_EXTILine_7},
+    {GPIO_PIN_8, EXTI9_5_IRQn, EXTI_LINE_8, SYSCFG_EXTILine_8},
+    {GPIO_PIN_9, EXTI9_5_IRQn, EXTI_LINE_9, SYSCFG_EXTILine_9},
+    {GPIO_PIN_10, EXTI15_10_IRQn, EXTI_LINE_10, SYSCFG_EXTILine_10},
+    {GPIO_PIN_11, EXTI15_10_IRQn, EXTI_LINE_11, SYSCFG_EXTILine_11},
+    {GPIO_PIN_12, EXTI15_10_IRQn, EXTI_LINE_12, SYSCFG_EXTILine_12},
+    {GPIO_PIN_13, EXTI15_10_IRQn, EXTI_LINE_13, SYSCFG_EXTILine_13},
+    {GPIO_PIN_14, EXTI15_10_IRQn, EXTI_LINE_14, SYSCFG_EXTILine_14},
+    {GPIO_PIN_15, EXTI15_10_IRQn, EXTI_LINE_15, SYSCFG_EXTILine_15},
+};
+
+static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
+{
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+};
+static uint32_t pin_irq_enable_mask = 0;
+
+#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
+
+static rt_base_t mm32_pin_get(const char *name)
+{
+    rt_base_t pin = 0;
+    int hw_port_num, hw_pin_num = 0;
+    int i, name_len;
+
+    name_len = rt_strlen(name);
+
+    if ((name_len < 4) || (name_len >= 6))
+    {
+        return -RT_EINVAL;
+    }
+    if ((name[0] != 'P') || (name[2] != '.'))
+    {
+        return -RT_EINVAL;
+    }
+
+    if ((name[1] >= 'A') && (name[1] <= 'F'))
+    {
+        hw_port_num = (int)(name[1] - 'A');
+    }
+    else
+    {
+        return -RT_EINVAL;
+    }
+
+    for (i = 3; i < name_len; i++)
+    {
+        hw_pin_num *= 10;
+        hw_pin_num += name[i] - '0';
+    }
+
+    pin = PIN_NUM(hw_port_num, hw_pin_num);
+
+    return pin;
+}
+
+static void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    GPIO_Type *gpio_port;
+    uint16_t gpio_pin;
+
+    if (PIN_PORT(pin) < PIN_STPORT_MAX)
+    {
+        gpio_port = PIN_STPORT(pin);
+        gpio_pin = PIN_STPIN(pin);
+
+        GPIO_WriteBit(gpio_port, gpio_pin, (rt_uint16_t)value);
+    }
+}
+
+static int mm32_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    GPIO_Type *gpio_port;
+    uint16_t gpio_pin;
+    int value = PIN_LOW;
+
+    if (PIN_PORT(pin) < PIN_STPORT_MAX)
+    {
+        gpio_port = PIN_STPORT(pin);
+        gpio_pin = PIN_STPIN(pin);
+        value = GPIO_ReadInDataBit(gpio_port, gpio_pin);
+    }
+
+    return value;
+}
+
+static void mm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    GPIO_Init_Type GPIO_InitStruct;
+
+    if (PIN_PORT(pin) >= PIN_STPORT_MAX)
+    {
+        return;
+    }
+
+    /* Configure GPIO_InitStructure */
+    GPIO_InitStruct.Pins = PIN_STPIN(pin);
+    GPIO_InitStruct.PinMode = GPIO_PinMode_Out_PushPull;
+    GPIO_InitStruct.Speed = GPIO_Speed_50MHz;
+
+    if (mode == PIN_MODE_OUTPUT)
+    {
+        /* output setting */
+        GPIO_InitStruct.PinMode = GPIO_PinMode_Out_PushPull;
+    }
+    else if (mode == PIN_MODE_INPUT)
+    {
+        /* input setting: not pull. */
+        GPIO_InitStruct.PinMode = GPIO_PinMode_In_Floating;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLUP)
+    {
+        /* input setting: pull up. */
+        GPIO_InitStruct.PinMode = GPIO_PinMode_In_PullUp;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLDOWN)
+    {
+        /* input setting: pull down. */
+        GPIO_InitStruct.PinMode = GPIO_PinMode_In_PullDown;
+    }
+    else if (mode == PIN_MODE_OUTPUT_OD)
+    {
+        /* output setting: od. */
+        GPIO_InitStruct.PinMode = GPIO_PinMode_Out_OpenDrain;
+    }
+
+    GPIO_Init(PIN_STPORT(pin), &GPIO_InitStruct);
+}
+
+rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
+{
+    rt_uint8_t i;
+    for (i = 0; i < 32; i++)
+    {
+        if ((0x01 << i) == bit)
+        {
+            return i;
+        }
+    }
+    return -1;
+}
+
+rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
+{
+    rt_int32_t mapindex = bit2bitno(pinbit);
+    if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_NULL;
+    }
+    return &pin_irq_map[mapindex];
+};
+
+static rt_err_t mm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                                     rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+
+    if (PIN_PORT(pin) >= PIN_STPORT_MAX)
+    {
+        return -RT_ENOSYS;
+    }
+
+    irqindex = bit2bitno(PIN_STPIN(pin));
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_ENOSYS;
+    }
+
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == pin &&
+        pin_irq_hdr_tab[irqindex].hdr == hdr &&
+        pin_irq_hdr_tab[irqindex].mode == mode &&
+        pin_irq_hdr_tab[irqindex].args == args)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    if (pin_irq_hdr_tab[irqindex].pin != -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EBUSY;
+    }
+    pin_irq_hdr_tab[irqindex].pin = pin;
+    pin_irq_hdr_tab[irqindex].hdr = hdr;
+    pin_irq_hdr_tab[irqindex].mode = mode;
+    pin_irq_hdr_tab[irqindex].args = args;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t mm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+
+    if (PIN_PORT(pin) >= PIN_STPORT_MAX)
+    {
+        return -RT_ENOSYS;
+    }
+
+    irqindex = bit2bitno(PIN_STPIN(pin));
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_ENOSYS;
+    }
+
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    pin_irq_hdr_tab[irqindex].pin = -1;
+    pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
+    pin_irq_hdr_tab[irqindex].mode = 0;
+    pin_irq_hdr_tab[irqindex].args = RT_NULL;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t mm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
+                                     rt_uint32_t enabled)
+{
+    const struct pin_irq_map *irqmap;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+    GPIO_Init_Type GPIO_InitStruct;
+
+    if (PIN_PORT(pin) >= PIN_STPORT_MAX)
+    {
+        return -RT_ENOSYS;
+    }
+
+    if (enabled == PIN_IRQ_ENABLE)
+    {
+        irqindex = bit2bitno(PIN_STPIN(pin));
+        if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+        {
+            return RT_ENOSYS;
+        }
+
+        level = rt_hw_interrupt_disable();
+
+        if (pin_irq_hdr_tab[irqindex].pin == -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_ENOSYS;
+        }
+
+        irqmap = &pin_irq_map[irqindex];
+
+        /* Configure GPIO_InitStructure */
+        GPIO_InitStruct.Pins = PIN_STPIN(pin);
+        GPIO_InitStruct.Speed = GPIO_Speed_50MHz;
+        GPIO_InitStruct.PinMode = GPIO_PinMode_In_PullUp;
+        GPIO_Init(PIN_STPORT(pin), &GPIO_InitStruct);
+        
+        SYSCFG_SetExtIntMux(SYSCFG_EXTIPort_GPIOA + (0 == (rt_uint32_t)PIN_PORT(pin)?0: PIN_PORT(pin)/GPIOB_BASE), irqmap->syscfg_extiline);
+        switch (pin_irq_hdr_tab[irqindex].mode)
+        {
+        case PIN_IRQ_MODE_RISING:
+            EXTI_SetTriggerIn(EXTI, irqmap->extiline, EXTI_TriggerIn_RisingEdge);
+            break;
+        case PIN_IRQ_MODE_FALLING:
+            EXTI_SetTriggerIn(EXTI, irqmap->extiline, EXTI_TriggerIn_FallingEdge);
+            break;
+        case PIN_IRQ_MODE_RISING_FALLING:
+            EXTI_SetTriggerIn(EXTI, irqmap->extiline, EXTI_TriggerIn_BothEdges);
+            break;
+        }
+        EXTI_EnableLineInterrupt(EXTI, irqmap->extiline, true);
+        
+        NVIC_SetPriority(irqmap->irqno, NVIC_EncodePriority(4, 5, 0));
+        NVIC_EnableIRQ(irqmap->irqno);
+        pin_irq_enable_mask |= irqmap->pinbit;
+
+        rt_hw_interrupt_enable(level);
+    }
+    else if (enabled == PIN_IRQ_DISABLE)
+    {
+        irqmap = get_pin_irq_map(PIN_STPIN(pin));
+        if (irqmap == RT_NULL)
+        {
+            return RT_ENOSYS;
+        }
+
+        level = rt_hw_interrupt_disable();
+
+        pin_irq_enable_mask &= ~irqmap->pinbit;
+
+        if ((irqmap->pinbit >= GPIO_PIN_5) && (irqmap->pinbit <= GPIO_PIN_9))
+        {
+            if (!(pin_irq_enable_mask & (GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9)))
+            {
+                NVIC_DisableIRQ(irqmap->irqno);
+            }
+        }
+        else if ((irqmap->pinbit >= GPIO_PIN_10) && (irqmap->pinbit <= GPIO_PIN_15))
+        {
+            if (!(pin_irq_enable_mask & (GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15)))
+            {
+                NVIC_DisableIRQ(irqmap->irqno);
+            }
+        }
+        else
+        {
+            NVIC_DisableIRQ(irqmap->irqno);
+        }
+
+        rt_hw_interrupt_enable(level);
+    }
+    else
+    {
+        return -RT_ENOSYS;
+    }
+
+    return RT_EOK;
+}
+const static struct rt_pin_ops _mm32_pin_ops =
+{
+    mm32_pin_mode,
+    mm32_pin_write,
+    mm32_pin_read,
+    mm32_pin_attach_irq,
+    mm32_pin_dettach_irq,
+    mm32_pin_irq_enable,
+    mm32_pin_get,
+};
+
+rt_inline void pin_irq_hdr(int irqno)
+{
+    if (pin_irq_hdr_tab[irqno].hdr)
+    {
+        pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
+    }
+}
+
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+    pin_irq_hdr(bit2bitno(GPIO_Pin));
+}
+
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+  /* EXTI line interrupt detected */
+  if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
+  {
+    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+    HAL_GPIO_EXTI_Callback(GPIO_Pin);
+  }
+}
+
+void EXTI0_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
+    rt_interrupt_leave();
+}
+
+void EXTI1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
+    rt_interrupt_leave();
+}
+
+void EXTI2_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);
+    rt_interrupt_leave();
+}
+
+void EXTI3_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3);
+    rt_interrupt_leave();
+}
+
+void EXTI4_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4);
+    rt_interrupt_leave();
+}
+
+void EXTI9_5_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5);
+    HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6);
+    HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7);
+    HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
+    HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);
+    rt_interrupt_leave();
+}
+
+void EXTI15_10_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);
+    HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);
+    HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12);
+    HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
+    HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);
+    HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);
+    rt_interrupt_leave();
+}
+
+int rt_hw_pin_init(void)
+{
+#if defined(RCC_AHB1_PERIPH_GPIOA)
+    RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOA, true);
+#endif
+
+#if defined(RCC_AHB1_PERIPH_GPIOB)
+    RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOB, true);
+#endif
+
+#if defined(RCC_AHB1_PERIPH_GPIOC)
+    RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOC, true);
+#endif
+
+#if defined(RCC_AHB1_PERIPH_GPIOD)
+    RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOD, true);
+#endif
+
+#if defined(RCC_AHB1_PERIPH_GPIOE)
+    RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOE, true);
+#endif
+
+#if defined(RCC_AHB1_PERIPH_GPIOF)
+    RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOF, true);
+#endif
+
+#if defined(RCC_APB2_PERIPH_SYSCFG)
+    RCC_EnableAPB2Periphs(RCC_APB2_PERIPH_SYSCFG, true);
+#endif
+
+    return rt_device_pin_register("pin", &_mm32_pin_ops, RT_NULL);
+}
+
+#endif /* RT_USING_PIN */

bsp/mm32/libraries/HAL_Drivers/drv_gpio.h

+/*
+ * Copyright (c) 2020-2022, CQ 100ask Development Team
+ *
+ * Change Logs:
+ *   Date           Author          Notes
+ * 2022-05-29        Alen       first version
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include <drv_common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define __MM32_PORT(port)  GPIO##port##_BASE
+
+#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__MM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN)
+
+struct pin_irq_map
+{
+    rt_uint16_t pinbit;
+    IRQn_Type irqno;
+    rt_uint32_t extiline;
+    SYSCFG_EXTILine_Type syscfg_extiline;
+};
+
+int rt_hw_pin_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DRV_GPIO_H__ */
+

bsp/mm32/libraries/HAL_Drivers/drv_spi.h

+/**
+ * @file drv_spi.h
+ * @author 100ask development team
+ * @brief 
+ * @version 0.1
+ * @date 2022-06-16
+ * 
+ * @copyright Copyright (c) 2022 Chongqing 100ASK Technology Co., LTD
+ * 
+ */
+
+#ifndef __DRV_SPI_H_
+#define __DRV_SPI_H_
+
+#include <rtthread.h>
+#include "rtdevice.h"
+#include <rthw.h>
+#include "drv_common.h"
+#include "drv_dma.h"
+
+rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef* cs_gpiox, uint16_t cs_gpio_pin);
+
+struct mm32_hw_spi_cs
+{
+    GPIO_Type* GPIOx;
+    uint16_t GPIO_Pin;
+};
+
+struct mm32_spi_config
+{
+    SPI_Type *Instance;
+    char *bus_name;
+    struct dma_config *dma_rx, *dma_tx;
+};
+
+struct stm32_spi_device
+{
+    rt_uint32_t pin;
+    char *bus_name;
+    char *device_name;
+};
+
+#define SPI_USING_RX_DMA_FLAG   (1<<0)
+#define SPI_USING_TX_DMA_FLAG   (1<<1)
+
+/* stm32 spi dirver class */
+struct mm32_spi
+{
+    SPI_Master_Init_Type handle;
+    struct mm32_spi_config *config;
+    struct rt_spi_configuration *cfg;
+
+    struct
+    {
+        rt_uint16_t rx_buf_len;
+        rt_uint8_t *rx_buf;
+        DMA_Channel_Init_Type handle_rx;
+        rt_uint16_t tx_buf_len;
+        rt_uint8_t *tx_buf;
+        DMA_Channel_Init_Type handle_tx;
+    } dma;
+    
+    rt_uint8_t spi_dma_flag;
+    struct rt_spi_bus spi_bus;
+};
+
+#endif /* __DRV_SPI_H_ */

bsp/mm32/libraries/HAL_Drivers/drv_uart.c

+/*
+ * Copyright (c) 2020-2022, CQ 100ask Development Team
+ *
+ * Change Logs:
+ *   Date           Author          Notes
+ * 2022-05-29        Alen       first version
+ */
+
+#include "board.h"
+#include "drv_uart.h"
+#include "drv_config.h"
+
+#ifdef RT_USING_SERIAL
+
+//#define DRV_DEBUG
+#define LOG_TAG             "drv.usart"
+
+#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \
+    !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \
+    !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8)
+#error "Please define at least one BSP_USING_UARTx"
+/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
+#endif
+
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__)       (((__HANDLE__)->CSR & (__FLAG__)) == (__FLAG__))
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__)     ((__HANDLE__)->CSR = ~(__FLAG__))
+#define __HAL_UART_GET_INT_FLAG(__HANDLE__, __FLAG__)   (((__HANDLE__)->ISR & (__FLAG__)) == (__FLAG__))
+#define __HAL_UART_CLEAR_INT_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->ICR &= (__FLAG__))
+
+enum
+{
+#ifdef BSP_USING_UART1
+    UART1_INDEX,
+#endif
+#ifdef BSP_USING_UART2
+    UART2_INDEX,
+#endif
+#ifdef BSP_USING_UART3
+    UART3_INDEX,
+#endif
+#ifdef BSP_USING_UART4
+    UART4_INDEX,
+#endif
+#ifdef BSP_USING_UART5
+    UART5_INDEX,
+#endif
+#ifdef BSP_USING_UART6
+    UART6_INDEX,
+#endif
+#ifdef BSP_USING_UART7
+    UART7_INDEX,
+#endif
+#ifdef BSP_USING_UART8
+    UART8_INDEX,
+#endif
+#ifdef BSP_USING_LPUART1
+    LPUART1_INDEX,
+#endif
+};
+
+static struct mm32_uart_config uart_config[] =
+{
+#ifdef BSP_USING_UART1
+    UART1_CONFIG,
+#endif
+#ifdef BSP_USING_UART2
+    UART2_CONFIG,
+#endif
+#ifdef BSP_USING_UART3
+    UART3_CONFIG,
+#endif
+#ifdef BSP_USING_UART4
+    UART4_CONFIG,
+#endif
+#ifdef BSP_USING_UART5
+    UART5_CONFIG,
+#endif
+#ifdef BSP_USING_UART6
+    UART6_CONFIG,
+#endif
+#ifdef BSP_USING_UART7
+    UART7_CONFIG,
+#endif
+#ifdef BSP_USING_UART8
+    UART8_CONFIG,
+#endif
+#ifdef BSP_USING_LPUART1
+    LPUART1_CONFIG,
+#endif
+};
+
+static struct mm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
+
+static rt_err_t mm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct mm32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    uart = rt_container_of(serial, struct mm32_uart, serial);
+    uart->handle.ClockFreqHz    = HAL_Get_APB2_Clock();
+    uart->handle.BaudRate       = cfg->baud_rate;
+    uart->handle.XferMode       = UART_XferMode_RxTx;
+
+    switch (cfg->flowcontrol)
+    {
+    case RT_SERIAL_FLOWCONTROL_NONE:
+        uart->handle.HwFlowControl = UART_HwFlowControl_None;
+        break;
+    case RT_SERIAL_FLOWCONTROL_CTSRTS:
+        uart->handle.HwFlowControl = UART_HwFlowControl_RTS_CTS;
+        break;
+    default:
+        uart->handle.HwFlowControl = UART_HwFlowControl_None;
+        break;
+    }
+
+    switch (cfg->data_bits)
+    {
+        case DATA_BITS_5:
+            uart->handle.WordLength    = UART_WordLength_5b;
+            break;
+        case DATA_BITS_6:
+            uart->handle.WordLength    = UART_WordLength_6b;
+            break;
+        case DATA_BITS_7:
+            uart->handle.WordLength    = UART_WordLength_7b;
+            break;
+        case DATA_BITS_8:
+            uart->handle.WordLength    = UART_WordLength_8b;
+            break;
+        default:
+            uart->handle.WordLength    = UART_WordLength_8b;
+            break;
+    }
+
+    switch (cfg->stop_bits)
+    {
+        case STOP_BITS_1:
+            uart->handle.StopBits      = UART_StopBits_1;
+            break;
+        case STOP_BITS_2:
+            uart->handle.StopBits      = UART_StopBits_2;
+            break;
+        default:
+            uart->handle.StopBits      = UART_StopBits_1;
+            break;
+    }
+
+    switch (cfg->parity)
+    {
+        case PARITY_NONE:
+            uart->handle.Parity        = UART_Parity_None;
+            break;
+        case PARITY_ODD:
+            uart->handle.Parity        = UART_Parity_Odd;
+            break;
+        case PARITY_EVEN:
+            uart->handle.Parity        = UART_Parity_Even;
+            break;
+        default:
+            uart->handle.Parity        = UART_Parity_None;
+            break;
+    }
+
+#ifdef RT_SERIAL_USING_DMA
+    if (!(serial->parent.open_flag & RT_DEVICE_OFLAG_OPEN)) {
+        uart->dma_rx.last_index = 0;
+    }
+#endif
+    extern void UART_MspInit(UART_Type *muart);
+    UART_MspInit(uart->config->Instance);
+    UART_Init(uart->config->Instance, &uart->handle);
+    UART_Enable(uart->config->Instance, true);
+
+    return RT_EOK;
+}
+
+static rt_err_t mm32_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct mm32_uart *uart;
+    rt_uint32_t prioritygroup = 0x00U;
+#ifdef RT_SERIAL_USING_DMA
+    rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
+#endif
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = rt_container_of(serial, struct mm32_uart, serial);
+
+    switch (cmd)
+    {
+    /* disable interrupt */
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        NVIC_DisableIRQ(uart->config->irq_type);
+
+#ifdef RT_SERIAL_USING_DMA
+        /* disable DMA */
+        if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
+        {
+
+        }
+        else if(ctrl_arg == RT_DEVICE_FLAG_DMA_TX)
+        {
+
+        }
+#endif
+        break;
+
+    /* enable interrupt */
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        UART_EnableInterrupts(uart->config->Instance, UART_INT_RX_DONE, true);
+        prioritygroup = NVIC_GetPriorityGrouping();
+        NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(prioritygroup, 1, 0));
+        NVIC_EnableIRQ(uart->config->irq_type);
+        break;
+
+#ifdef RT_SERIAL_USING_DMA
+    case RT_DEVICE_CTRL_CONFIG:
+        
+        break;
+#endif
+
+    case RT_DEVICE_CTRL_CLOSE:
+        
+        break;
+
+    }
+    return RT_EOK;
+}
+
+rt_uint32_t mm32_uart_get_mask(rt_uint32_t word_length, rt_uint32_t parity)
+{
+    rt_uint32_t mask;
+    if (word_length == UART_WordLength_8b)
+    {
+        if (parity == UART_Parity_None)
+        {
+            mask = 0x00FFU ;
+        }
+        else
+        {
+            mask = 0x007FU ;
+        }
+    }
+
+#ifdef UART_WORDLENGTH_7B
+    else if (word_length == UART_WordLength_7b)
+    {
+        if (parity == UART_Parity_None)
+        {
+            mask = 0x007FU ;
+        }
+        else
+        {
+            mask = 0x003FU ;
+        }
+    }
+    else
+    {
+        mask = 0x0000U;
+    }
+#endif
+    return mask;
+}
+
+static int mm32_putc(struct rt_serial_device *serial, char c)
+{
+    struct mm32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct mm32_uart, serial);
+
+    uart->config->Instance->TDR = c;
+
+    while ( 0u == (UART_STATUS_TX_EMPTY & UART_GetStatus(uart->config->Instance)) )
+    {}
+    return 1;
+}
+
+static int mm32_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct mm32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = rt_container_of(serial, struct mm32_uart, serial);
+
+    ch = -1;
+    if ((UART_STATUS_RX_DONE & UART_GetStatus(uart->config->Instance)) != 0)
+    {
+
+        ch = uart->config->Instance->RDR & mm32_uart_get_mask(uart->handle.WordLength, uart->handle.Parity);
+    }
+    return ch;
+}
+
+/**
+ * Uart common interrupt process. This need add to uart ISR.
+ *
+ * @param serial serial device
+ */
+static void uart_isr(struct rt_serial_device *serial)
+{
+    struct mm32_uart *uart;
+#ifdef RT_SERIAL_USING_DMA
+    rt_size_t recv_total_index, recv_len;
+    rt_base_t level;
+#endif
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = rt_container_of(serial, struct mm32_uart, serial);
+
+    /* UART in mode Receiver -------------------------------------------------*/
+    if (   (0u != __HAL_UART_GET_INT_FLAG(uart->config->Instance, UART_INT_RX_DONE))
+        && (0u != __HAL_UART_GET_FLAG(uart->config->Instance, UART_STATUS_RX_DONE)) )
+    {
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    }
+#ifdef RT_SERIAL_USING_DMA
+
+#endif
+    else
+    {
+        if (__HAL_UART_GET_FLAG(uart->config->Instance, UART_STATUS_RX_DONE) != 0)
+        {
+            __HAL_UART_CLEAR_FLAG(uart->config->Instance, UART_STATUS_RX_DONE);
+        }
+        if (__HAL_UART_GET_FLAG(uart->config->Instance, UART_STATUS_TX_DONE) != 0)
+        {
+            __HAL_UART_CLEAR_FLAG(uart->config->Instance, UART_STATUS_TX_DONE);
+        }
+        if (__HAL_UART_GET_FLAG(uart->config->Instance, UART_STATUS_TX_FULL) != 0)
+        {
+            __HAL_UART_CLEAR_FLAG(uart->config->Instance, UART_STATUS_TX_FULL);
+        }
+        if (__HAL_UART_GET_FLAG(uart->config->Instance, UART_STATUS_TX_EMPTY) != 0)
+        {
+            __HAL_UART_CLEAR_FLAG(uart->config->Instance, UART_STATUS_TX_EMPTY);
+        }
+        
+        if (__HAL_UART_GET_INT_FLAG(uart->config->Instance, UART_INT_RX_DONE) != 0)
+        {
+            __HAL_UART_CLEAR_INT_FLAG(uart->config->Instance, UART_INT_RX_DONE);
+        }
+        if (__HAL_UART_GET_INT_FLAG(uart->config->Instance, UART_INT_TX_DONE) != 0)
+        {
+            __HAL_UART_CLEAR_INT_FLAG(uart->config->Instance, UART_INT_TX_DONE);
+        }
+        if (__HAL_UART_GET_INT_FLAG(uart->config->Instance, UART_INT_TX_EMPTY) != 0)
+        {
+            __HAL_UART_CLEAR_INT_FLAG(uart->config->Instance, UART_INT_TX_EMPTY);
+        }
+    }
+}
+
+#if defined(BSP_USING_UART1)
+void UART1_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&(uart_obj[UART1_INDEX].serial));
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+
+#if defined(BSP_USING_UART2)
+void UART2_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&(uart_obj[UART2_INDEX].serial));
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_UART3)
+void UART3_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&(uart_obj[UART3_INDEX].serial));
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+static const struct rt_uart_ops mm32_uart_ops =
+{
+    .configure = mm32_configure,
+    .control = mm32_control,
+    .putc = mm32_putc,
+    .getc = mm32_getc,
+    .dma_transmit = RT_NULL
+};
+
+int rt_hw_uart_init(void)
+{
+    rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct mm32_uart);
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+    rt_err_t result = 0;
+
+    for (int i = 0; i < obj_num; i++)
+    {
+        /* init UART object */
+        uart_obj[i].config = &uart_config[i];
+        uart_obj[i].serial.ops    = &mm32_uart_ops;
+        uart_obj[i].serial.config = config;
+
+        /* register UART device */
+        result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
+                                       RT_DEVICE_FLAG_RDWR
+                                       | RT_DEVICE_FLAG_INT_RX
+                                       | RT_DEVICE_FLAG_INT_TX
+                                       | uart_obj[i].uart_dma_flag
+                                       , NULL);
+        RT_ASSERT(result == RT_EOK);
+    }
+
+    return result;
+}
+
+#endif /* RT_USING_SERIAL */

bsp/mm32/libraries/HAL_Drivers/drv_uart.h

+/*
+ * Copyright (c) 2020-2022, CQ 100ask Development Team
+ *
+ * Change Logs:
+ *   Date           Author          Notes
+ * 2022-05-29        Alen       first version
+ */
+
+#ifndef __DRV_USART_H__
+#define __DRV_USART_H__
+
+#include <rtthread.h>
+#include "rtdevice.h"
+#include <rthw.h>
+#include <drv_common.h>
+
+int rt_hw_uart_init(void);
+
+#define DMA_INSTANCE_TYPE               MA_Channel_TypeDef
+
+#define UART_INSTANCE_CLEAR_FUNCTION    __HAL_UART_CLEAR_FLAG
+
+
+/* stm32 config class */
+struct mm32_uart_config
+{
+    const char *name;
+    UART_Type *Instance;
+    IRQn_Type irq_type;
+    struct dma_config *dma_rx;
+    struct dma_config *dma_tx;
+};
+
+/* stm32 uart dirver class */
+struct mm32_uart
+{
+    UART_Init_Type handle;
+    struct mm32_uart_config *config;
+
+#ifdef RT_SERIAL_USING_DMA
+    struct
+    {
+        DMA_Type handle;
+        rt_size_t last_index;
+    } dma_rx;
+#endif
+    rt_uint16_t uart_dma_flag;
+    struct rt_serial_device serial;
+};
+
+#endif  /* __DRV_USART_H__ */

bsp/mm32/libraries/Kconfig

+config SOC_FAMILY_MM32
+    bool
+
+config SOC_SERIES_MM32F3277
+    bool
+    select ARCH_ARM_CORTEX_M3
+    select SOC_FAMILY_MM32
\ No newline at end of file

bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Device/MM32/MM32F3277/Include/hal_device_registers.h

+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef __HAL_DEVICE_REGISTER_H__
+#define __HAL_DEVICE_REGISTER_H__
+
+//#include "./mm32f327x/mm32_device.h"
+
+#include "mm32f3277g.h"
+#include "mm32f3277g_features.h"
+#include "system_mm32f3277g.h"
+
+#endif /* __HAL_DEVICE_REGISTER_H__ */

bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Device/MM32/MM32F3277/Include/system_mm32f3277g.h

+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef __SYSTEM_MM32F327X_H__
+#define __SYSTEM_MM32F327X_H__
+
+void SystemInit(void);
+
+#endif /* __SYSTEM_MM32F327X_H__ */

bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Device/MM32/MM32F3277/Source/Templates/arm/linker/mm32f3277g_flash.sct

+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+  RW_IRAM1 0x20000000 0x00020000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+