修改了BSP包中不合理的地方和不符合RTThread规范的地方

bsp/imxrt/Libraries/MIMXRT1064/SConscript

@@ -12,13 +12,10 @@ MIMXRT1064/drivers/fsl_cache.c
 
 if rtconfig.CROSS_TOOL == 'gcc':
     src += ['MIMXRT1064/gcc/startup_MIMXRT1064.S']
-    path.append(cwd + '/MIMXRT1064/gcc')
 elif rtconfig.CROSS_TOOL == 'keil':
     src += ['MIMXRT1064/arm/startup_MIMXRT1064.s']
-    path.append(cwd + '/MIMXRT1064/arm')
 elif rtconfig.CROSS_TOOL == 'iar':
     src += ['MIMXRT1064/iar/startup_MIMXRT1064.s']
-    path.append(cwd + '/MIMXRT1064/iar')
 
 if GetDepend(['BSP_USING_GPIO']):
     src += ['MIMXRT1064/drivers/fsl_gpio.c']
@@ -75,7 +72,10 @@ if GetDepend(['BSP_USING_DMA']):
     src += ['MIMXRT1064/drivers/fsl_edma.c']
 
 if GetDepend(['RT_SERIAL_USING_DMA']):
+    src += ['MIMXRT1064/drivers/fsl_dmamux.c']
+    src += ['MIMXRT1064/drivers/fsl_edma.c']
     src += ['MIMXRT1064/drivers/fsl_lpuart_edma.c']
+    src += ['MIMXRT1064/drivers/fsl_lpspi_edma.c']
 
 group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path)
 

bsp/imxrt/Libraries/templates/imxrt1064xxx/.config

+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_MEMHEAP=y
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_SMALL_MEM is not set
+# CONFIG_RT_USING_SLAB is not set
+CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40001
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+CONFIG_FINSH_USING_MSH_ONLY=y
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+CONFIG_RT_USING_CPUTIME=y
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_MTD is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+
+#
+# Using WiFi
+#
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# Modbus master and slave stack
+#
+# CONFIG_RT_USING_MODBUS is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_LOGTRACE is not set
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTKIT is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+
+#
+# Hardware Drivers Config
+#
+# CONFIG_BSP_USING_HYPERFLASH is not set
+CONFIG_BSP_USING_4MFLASH=y
+CONFIG_SOC_MIMXRT1064DVL6A=y
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_LPUART=y
+CONFIG_BSP_USING_LPUART1=y
+
+#
+# Onboard Peripheral Drivers
+#
+
+#
+# Board extended module Drivers
+#

bsp/imxrt/Libraries/templates/imxrt1064xxx/Kconfig

+mainmenu "RT-Thread Configuration"
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"

bsp/imxrt/Libraries/templates/imxrt1064xxx/README.md

+# BSP README 模板
+
+## 简介
+
+本文档为 MIMXRT1064-EVK 开发板的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 开发板介绍
+
+【此处简单介绍一下开发板】
+
+开发板外观如下图所示：
+
+![board](MIMXRT1064EVK-TOP.jpg)
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：MIMXRT1064DVL6A，主频 600MHz，4096KB FLASH ，1024KB RAM
+- 外部 RAM：型号IS42S16160J-6BLI，32MB
+- 外部 FLASH：型号S26KS512SDPBHI02，64MB
+- 常用外设
+  - LED：1个，D18（绿色） 
+  - 按键：1个
+- 常用接口：USB 转串口、SD 卡接口、以太网接口、LCD 接口等
+- 调试接口，标准 JTAG/SWD
+
+开发板更多详细信息请参考【NXP】 [MIMXRT1064-EVK开发板介绍](https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/i.mx-evaluation-and-development-boards/mimxrt1064-evk-i.mx-rt1064-evaluation-kit:MIMXRT1064-EVK)。
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设**      | **支持情况** | **备注**                              |
+| :----------------- | :----------: | :------------------------------------- |
+| USB 转串口        |     支持     |                                       |
+| SPI Flash         |     支持     |                                       |
+| 以太网            |   暂不支持    |                                       |
+| SD卡              |   暂不支持   |                                       |
+| CAN               |   暂不支持   |                                       |
+| **片上外设**      | **支持情况** | **备注**                              |
+| GPIO              |     支持     | PA0, PA1... PK15 ---> PIN: 0, 1...176 |
+| UART              |     支持     | UART1                                 |
+| SPI               |   暂不支持     | 即将支持                              |
+| I2C               |   暂不支持   | 即将支持                               |
+| SDIO              |   暂不支持   | 即将支持                              |
+| RTC               |   暂不支持   | 即将支持                              |
+| PWM               |   暂不支持   | 即将支持                              |
+| USB Device        |   暂不支持   | 即将支持                              |
+| USB Host          |   暂不支持   | 即将支持                              |
+| IWG               |   暂不支持   | 即将支持                              |
+| **扩展模块**      | **支持情况** | **备注**                              |
+|     xxx 模块      |   支持   |                                      |
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+    本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+    本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，暂不支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用数据线连接开发板到 PC，打开电源开关。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 CMSIS-DAP 仿真器下载程序，在通过 USB 连接开发板的基础上，点击下载按钮即可下载程序到开发板
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，【这里写开发板运行起来之后的现象，如：LED 闪烁等】。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     3.1.1 build Nov 19 2018
+ 2006 - 2018 Copyright by rt-thread team
+msh >
+```
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置(暂时还不支持，等待第二阶段)，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk/iar` 命令重新生成工程。
+
+本章节更多详细的介绍请参考 [IMXRT 系列 BSP 外设驱动使用教程](../docs/IMXRT系列BSP外设驱动使用教程.md)。
+
+## 注意事项
+
+- 
+
+## 联系人信息
+
+维护人:
+
+-  [王强](https://github.com/xfwangqiang), 邮箱：<164877907@qq.com>
\ No newline at end of file

bsp/imxrt/Libraries/templates/imxrt1064xxx/SConscript

+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/imxrt/Libraries/templates/imxrt1064xxx/SConstruct

+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+if rtconfig.PLATFORM == 'armcc':
+    env = Environment(tools = ['mingw'],
+        AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+        CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+        CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+        AR = rtconfig.AR, ARFLAGS = '-rc',
+        LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
+        # overwrite cflags, because cflags has '--C99'
+        CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES')
+else:
+    env = Environment(tools = ['mingw'],
+        AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+        CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+        CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+        AR = rtconfig.AR, ARFLAGS = '-rc',
+        LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
+        CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES')
+
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+objs = objs + SConscript('../Libraries/drivers/SConscript')
+objs = objs + SConscript('../Libraries/MIMXRT1064/SConscript')
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/imxrt/Libraries/templates/imxrt1064xxx/applications/SConscript

+import rtconfig
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+# add for startup script 
+if rtconfig.CROSS_TOOL == 'gcc':
+    CPPDEFINES = ['__START=entry']
+else:
+    CPPDEFINES = []
+    
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
+
+Return('group')

bsp/imxrt/Libraries/templates/imxrt1064xxx/applications/main.c

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-04-29     tyustli      first version
+ */
+
+#include "MIMXRT1064.h"
+#include <rtdevice.h>
+#include "drv_gpio.h"
+#include "core_cm7.h"
+
+/* defined the LED pin: GPIO1_IO9 */
+#define LED0_PIN               GET_PIN(1, 9)
+
+int main(void)
+{
+    /* set LED0 pin mode to output */
+    rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
+
+    while (1)
+    {
+        rt_pin_write(LED0_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED0_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+}
+
+void reboot(void)
+{
+    NVIC_SystemReset();
+}
+MSH_CMD_EXPORT(reboot, reset system)

bsp/imxrt/Libraries/templates/imxrt1064xxx/board/Kconfig

+menu "Hardware Drivers Config"
+
+
+config BSP_USING_HYPERFLASH
+    bool
+    default n
+
+config BSP_USING_4MFLASH
+    bool
+    default n
+
+config SOC_MIMXRT1064DVL6A
+    bool
+    select SOC_MIMXRT1064_SERIES
+    select BSP_USING_4MFLASH
+    default y
+
+menu "On-chip Peripheral Drivers"
+
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN
+        default y
+
+    menuconfig BSP_USING_LPUART
+        bool "Enable UART"
+        select RT_USING_SERIAL
+        default y
+        if BSP_USING_LPUART
+            config BSP_USING_LPUART1
+                bool "Enable LPUART1"
+                default y
+        endif
+
+endmenu
+
+menu "Onboard Peripheral Drivers"
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu

bsp/imxrt/Libraries/templates/imxrt1064xxx/board/MCUX_Config/clock_config.h

+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             600000000U  /*!< Core clock frequency: 600000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               600000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT               40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT               12000000UL
+#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK               2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK             1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK               1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK              2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK           1200000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT          264000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           261818181UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               150000000UL
+#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT             9642857UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_LVDS1_CLK                  1200000000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            75000000UL
+#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK              24000000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              75000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             117333333UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                0UL
+#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK                0UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            198000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            198000000UL
+
+/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+

bsp/imxrt/Libraries/templates/imxrt1064xxx/board/MCUX_Config/pin_mux.c

+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v5.0
+processor: MIMXRT1064xxxxA
+package_id: MIMXRT1064DVL6A
+mcu_data: ksdk2_0
+processor_version: 5.0.1
+pin_labels:
+- {pin_num: G11, pin_signal: GPIO_AD_B0_03, label: BSP_BEEP}
+- {pin_num: L13, pin_signal: GPIO_AD_B1_10, label: BSP_RS485_RE, identifier: CSI_D7}
+- {pin_num: J13, pin_signal: GPIO_AD_B1_11, label: BSP_DS18B20, identifier: CSI_D6}
+- {pin_num: K12, pin_signal: GPIO_AD_B1_05, label: BSP_AP3216C_INT, identifier: CSI_MCLK}
+- {pin_num: A11, pin_signal: GPIO_B1_00, label: HEART_LED, identifier: HEART_LED}
+- {pin_num: K11, pin_signal: GPIO_AD_B1_01, label: TJA1043_STB, identifier: TJA1043_STB}
+- {pin_num: L12, pin_signal: GPIO_AD_B1_04, label: TJA1043_EN, identifier: TJA1043_EN}
+- {pin_num: B11, pin_signal: GPIO_B1_01, label: TJA1043_WAKE, identifier: TJA1043_WAKE}
+- {pin_num: A12, pin_signal: GPIO_B1_08, label: MCU_PMIC_EN, identifier: SOC_POWER;MCU_PMIC_EN}
+- {pin_num: D11, pin_signal: GPIO_B1_03, label: RSTBTN_N, identifier: SOC_RSTBTN_N;RSTBTN_N}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ * 
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ * 
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void) {
+}
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13}
+  - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12}
+  - {pin_num: F14, peripheral: GPIO1, signal: 'gpio_io, 09', pin_signal: GPIO_AD_B0_09}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) {
+  CLOCK_EnableClock(kCLOCK_Iomuxc);           /* iomuxc clock (iomuxc_clk_enable): 0x03U */
+
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,        /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_B0_12_LPUART1_TX,        /* GPIO_AD_B0_12 is configured as LPUART1_TX */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_SetPinMux(
+      IOMUXC_GPIO_AD_B0_13_LPUART1_RX,        /* GPIO_AD_B0_13 is configured as LPUART1_RX */
+      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+  IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
+    (~(IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK))) /* Mask bits to zero which are setting */
+      | IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U) /* GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: 0x00U */
+    );
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/

bsp/imxrt/Libraries/templates/imxrt1064xxx/board/MCUX_Config/pin_mux.h

+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*! @brief Direction type  */
+typedef enum _pin_mux_direction
+{
+  kPIN_MUX_DirectionInput = 0U,         /* Input direction */
+  kPIN_MUX_DirectionOutput = 1U,        /* Output direction */
+  kPIN_MUX_DirectionInputOrOutput = 2U  /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/

bsp/imxrt/Libraries/templates/imxrt1064xxx/board/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+board.c
+MCUX_Config/clock_config.c
+MCUX_Config/pin_mux.c
+""")
+
+CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports']
+
+if rtconfig.CROSS_TOOL == 'keil':
+    CPPDEFINES = ['CPU_MIMXRT1064DVL6A', 'STD=C99', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL','XIP_EXTERNAL_FLASH=1', 'XIP_BOOT_HEADER_ENABLE=1', '__CC_ARM', 'NDEBUG', '__FPU_PRESENT=1']
+else:
+    CPPDEFINES = ['CPU_MIMXRT1064DVL6A', 'STD=C99', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL','XIP_EXTERNAL_FLASH=1', 'XIP_BOOT_HEADER_ENABLE=1']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
+
+Return('group')

bsp/imxrt/Libraries/templates/imxrt1064xxx/board/board.c

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "board.h"
+#include "pin_mux.h"
+
+/* MPU configuration. */
+static void BOARD_ConfigMPU(void)
+{
+    /* Disable I cache and D cache */
+    SCB_DisableICache();
+    SCB_DisableDCache();
+
+    /* Disable MPU */
+    ARM_MPU_Disable();
+
+    /* Region 0 setting */
+    MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
+
+    /* Region 1 setting */
+    MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
+
+    /* Region 2 setting */
+    // spi flash: normal type, cacheable, no bufferable, no shareable
+    MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512MB);
+
+    /* Region 3 setting */
+    MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
+
+    /* Region 4 setting */
+    MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
+
+    /* Region 5 setting */
+    MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
+
+    /* Region 6 setting */
+    MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
+
+#if defined(SDRAM_MPU_INIT)
+    /* Region 7 setting */
+    MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
+
+    /* Region 8 setting */
+    MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
+    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
+#endif
+
+    /* Enable MPU */
+    ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
+
+    /* Enable I cache and D cache */
+    SCB_EnableDCache();
+    SCB_EnableICache();
+}
+
+
+/* This is the timer interrupt service routine. */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/* This function will initial STM32 board. */
+void rt_hw_board_init()
+{
+    BOARD_ConfigMPU();
+    BOARD_InitPins();
+    BOARD_BootClockRUN();
+
+    SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+}

bsp/imxrt/Libraries/templates/imxrt1064xxx/board/board.h

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-09-22     Bernard      add board.h to this bsp
+ */
+
+// <<< Use Configuration Wizard in Context Menu >>>
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+#ifdef __CC_ARM
+extern int Image$$RTT_HEAP$$ZI$$Base;
+extern int Image$$RTT_HEAP$$ZI$$Limit;
+#define HEAP_BEGIN          (&Image$$RTT_HEAP$$ZI$$Base)
+#define HEAP_END            (&Image$$RTT_HEAP$$ZI$$Limit)
+
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN          (__segment_end("HEAP"))
+extern void __RTT_HEAP_END;
+#define HEAP_END            (&__RTT_HEAP_END)
+
+#else
+extern int heap_start;
+extern int heap_end;
+#define HEAP_BEGIN          (&heap_start)
+#define HEAP_END            (&heap_end)
+#endif
+
+#define HEAP_SIZE           ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN)
+
+#define SDRAM_MPU_INIT
+#define SDRAM_BEGIN         (0x80000000u)
+#define SDRAM_END           (0x81E00000u)
+
+
+/*! @brief The board flash size */
+#define BOARD_FLASH_SIZE (0x400000U)
+
+void rt_hw_board_init(void);
+
+#endif
+

bsp/imxrt/Libraries/templates/imxrt1064xxx/board/linker_scripts/link.icf

+/*
+** ###################################################################
+**     Processors:          MIMXRT1052CVJ5B
+**                          MIMXRT1052CVL5B
+**                          MIMXRT1052DVJ6B
+**                          MIMXRT1052DVL6B
+**
+**     Compiler:            IAR ANSI C/C++ Compiler for ARM
+**     Reference manual:    IMXRT1050RM Rev.1, 03/2018
+**     Version:             rev. 1.0, 2018-09-21
+**     Build:               b180921
+**
+**     Abstract:
+**         Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+define symbol m_interrupts_start       = 0x70002000;
+define symbol m_interrupts_end         = 0x700023FF;
+
+define symbol m_text_start             = 0x70002400;
+define symbol m_text_end               = 0x73FFFFFF;
+
+define symbol m_data_start             = 0x20000000;
+define symbol m_data_end               = 0x2001FFFF;
+
+define symbol m_data2_start            = 0x20200000;
+define symbol m_data2_end              = 0x2023FFFF;
+
+define exported symbol m_boot_hdr_conf_start = 0x70000000;
+define symbol m_boot_hdr_ivt_start           = 0x70001000;
+define symbol m_boot_hdr_boot_data_start     = 0x70001020;
+define symbol m_boot_hdr_dcd_data_start      = 0x70001030;
+
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+  define symbol __size_cstack__        = __stack_size__;
+} else {
+  define symbol __size_cstack__        = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+  define symbol __size_heap__          = __heap_size__;
+} else {
+  define symbol __size_heap__          = 0x0400;
+}
+
+define exported symbol __VECTOR_TABLE  = m_interrupts_start;
+define exported symbol __VECTOR_RAM    = m_interrupts_start;
+define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
+define exported symbol __RTT_HEAP_END = m_data2_end;
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+                          | mem:[from m_text_start to m_text_end];
+
+define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
+define region DATA2_region = mem:[from m_data2_start to m_data2_end];
+define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
+
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block RW        { readwrite };
+define block ZI        { zi };
+define block NCACHE_VAR    { section NonCacheable , section NonCacheable.init };
+
+initialize by copy { readwrite, section .textrw };
+do not initialize  { section .noinit };
+
+place at address mem: m_interrupts_start    { readonly section .intvec };
+
+place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
+place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
+place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
+place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
+
+keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
+
+place in TEXT_region                        { readonly };
+place in DATA_region                        { block RW };
+place in DATA_region                        { block ZI };
+place in DATA_region                        { last block HEAP };
+place in DATA_region                        { block NCACHE_VAR };
+place in CSTACK_region                      { block CSTACK };
+

bsp/imxrt/Libraries/templates/imxrt1064xxx/board/linker_scripts/link.lds

+/*
+** ###################################################################
+**     Processors:          MIMXRT1052CVL5A
+**                          MIMXRT1052DVL6A
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    IMXRT1050RM Rev.C, 08/2017
+**     Version:             rev. 0.1, 2017-01-10
+**     Build:               b170927
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     1. Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     2. Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     3. Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_boot_data           (RX)  : ORIGIN = 0x70000000, LENGTH = 0x00001000
+  m_image_vertor_table  (RX)  : ORIGIN = 0x70001000, LENGTH = 0x00001000
+
+  m_interrupts          (RX)  : ORIGIN = 0x70002000, LENGTH = 0x00000400
+  m_text                (RX)  : ORIGIN = 0x70002400, LENGTH = 0x003FDC00
+
+  m_itcm                (RW)  : ORIGIN = 0x00000000, LENGTH = 0x00020000
+  m_dtcm                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00020000
+  m_ocram               (RW)  : ORIGIN = 0x20200000, LENGTH = 0x00040000
+
+  m_sdram               (RW)  : ORIGIN = 0x80000000, LENGTH = 0x01E00000
+  m_nocache             (RW)  : ORIGIN = 0x81E00000, LENGTH = 0x00200000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  .boot_data :
+  {
+    . = ALIGN(4);
+    __FLASH_BASE = .;
+    KEEP(* (.boot_hdr.conf))     /* flash config section */
+    . = ALIGN(4);
+  } > m_boot_data
+
+  ivt_begin= ORIGIN(m_boot_data) + LENGTH(m_boot_data);
+
+  .image_vertor_table : AT(ivt_begin)
+  {
+    . = ALIGN(4);
+    KEEP(*(.boot_hdr.ivt))
+    KEEP(*(.boot_hdr.boot_data))
+    KEEP(*(.boot_hdr.dcd_data))
+    . = ALIGN(4);
+  } > m_image_vertor_table
+
+  /* The startup code goes first into internal RAM */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  __VECTOR_RAM = __VECTOR_TABLE;
+  __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;
+
+  /* The program code and other data goes into internal RAM */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+
+    /* section information for finsh shell */
+    . = ALIGN(4);
+    __fsymtab_start = .;
+    KEEP(*(FSymTab))
+    __fsymtab_end = .;
+    . = ALIGN(4);
+    __vsymtab_start = .;
+    KEEP(*(VSymTab))
+    __vsymtab_end = .;
+    . = ALIGN(4);
+
+    /* section information for initial. */
+    . = ALIGN(4);
+    __rt_init_start = .;
+    KEEP(*(SORT(.rti_fn*)))
+    __rt_init_end = .;
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    PROVIDE(__ctors_start__ = .);
+    /* __CTOR_LIST__ = .; */
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    /* __CTOR_END__ = .; */
+    PROVIDE(__ctors_end__ = .);
+  } > m_text
+
+  .dtors :
+  {
+    PROVIDE(__dtors_start__ = .);
+    /* __DTOR_LIST__ = .; */
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /* __DTOR_END__ = .; */
+    PROVIDE(__dtors_end__ = .);
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(m_usb_dma_init_data)
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_dtcm
+
+  __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);
+  .ncache.init : AT(__NDATA_ROM)
+  {
+    __noncachedata_start__ = .;   /* create a global symbol at ncache data start */
+    *(NonCacheable.init)
+    . = ALIGN(4);
+    __noncachedata_init_end__ = .;   /* create a global symbol at initialized ncache data end */
+  } > m_nocache
+  . = __noncachedata_init_end__;
+  .ncache :
+  {
+    *(NonCacheable)
+    . = ALIGN(4);
+    __noncachedata_end__ = .;     /* define a global symbol at ncache data end */
+  } > m_nocache
+
+  __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(m_usb_dma_noninit_data)
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_dtcm
+
+  .stack :
+  {
+    . = ALIGN(8);
+    stack_start = .;
+    . += STACK_SIZE;
+    stack_end = .;
+    __StackTop = .;
+  } > m_dtcm
+  
+  .RTT_HEAP :
+  {
+    heap_start = .;
+    . = ALIGN(8);
+  } > m_dtcm
+
+  PROVIDE(heap_end = ORIGIN(m_dtcm) + LENGTH(m_dtcm));
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+}
+

bsp/imxrt/Libraries/templates/imxrt1064xxx/board/linker_scripts/link.sct

+#! armcc -E
+/*
+** ###################################################################
+**     Processors:          MIMXRT1064DVL6A
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    IMXRT1064RM Rev.C, 08/2017
+**     Version:             rev. 0.1, 2019-05-29
+**     Build:               b190529
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     1. Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     2. Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     3. Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+
+#define m_flash_config_start           0x70000000
+#define m_flash_config_size            0x00001000
+
+#define m_ivt_start                    0x70001000
+#define m_ivt_size                     0x00001000
+
+#define m_interrupts_start             0x70002000
+#define m_interrupts_size              0x00000400
+
+#define m_text_start                   0x70002400
+#define m_text_size                    0x003FDC00
+
+#define m_data_start                   0x20000000       ; DTCM 128KB
+#define m_data_size                    0x00020000
+
+#define m_data2_start                  0x20200000       ; OCRAM2 768KB
+#define m_data2_size                   0x000C0000
+
+#define m_data3_start                  0x00000000       ; ITCM 128KB
+#define m_data3_size                   0x00020000
+
+
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0400
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+#include "../../rtconfig.h"
+
+#if (defined(BSP_USING_4MFLASH))
+LR_m_rom_config m_flash_config_start m_flash_config_size      ; load region size_region
+{   
+    RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address
+    { 
+        * (.boot_hdr.conf, +FIRST)
+    }  
+}
+
+LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region
+{   
+    RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address
+    { 
+        * (.boot_hdr.ivt, +FIRST)
+        * (.boot_hdr.boot_data)
+        * (.boot_hdr.dcd_data)
+    }   
+}
+#endif
+
+#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
+
+; load region size_region
+LR_IROM1 m_text_start m_text_size 
+{   
+    ER_IROM1 m_text_start m_text_size ; load address = execution address
+    { 
+        * (RESET,+FIRST)
+        * (InRoot$$Sections)
+        .ANY (+RO)
+    }
+  
+    RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data
+    { 
+        .ANY (+RW +ZI)
+    }
+    
+    ARM_LIB_HEAP +0 EMPTY Heap_Size{}   ; Heap region growing up
+    ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
+    RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
+
+    ; ncache RW data
+    RW_m_ncache m_data2_start m_data2_size 
+    { 
+        * (NonCacheable.init)
+        * (NonCacheable)
+    }
+;  ITCM 0x400 0xFBFF {
+;        ;drv_flexspi_hyper.o(+RO)
+;        ;fsl_flexspi.o(+RO)
+;        * (*CLOCK_DisableClock)
+;        * (*CLOCK_ControlGate)
+;        * (*CLOCK_EnableClock)
+;        * (*CLOCK_SetDiv)
+;        * (itcm)
+;    }
+}

bsp/imxrt/Libraries/templates/imxrt1064xxx/project.eww

+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\project.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+

bsp/imxrt/Libraries/templates/imxrt1064xxx/settings/project.crun

+<?xml version="1.0" encoding="UTF-8"?>
+<crun>
+    <version>1</version>
+    <filter_entries>
+        <filter index="0" type="default">
+            <type>*</type>
+            <start_file>*</start_file>
+            <end_file>*</end_file>
+            <action_debugger>0</action_debugger>
+            <action_log>1</action_log>
+        </filter>
+    </filter_entries>
+</crun>

bsp/imxrt/Libraries/templates/imxrt1064xxx/settings/project.dbgdt

+<?xml version="1.0"?>
+<Project>
+    <WindowStorage />
+</Project>

bsp/imxrt/Libraries/templates/imxrt1064xxx/settings/project.rtthread.cspy.bat

+@REM This batch file has been generated by the IAR Embedded Workbench
+@REM C-SPY Debugger, as an aid to preparing a command line for running
+@REM the cspybat command line utility using the appropriate settings.
+@REM
+@REM Note that this file is generated every time a new debug session
+@REM is initialized, so you may want to move or rename the file before
+@REM making changes.
+@REM
+@REM You can launch cspybat by typing the name of this batch file followed
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
+@REM
+@REM Read about available command line parameters in the C-SPY Debugging
+@REM Guide. Hints about additional command line parameters that may be
+@REM useful in specific cases:
+@REM   --download_only   Downloads a code image without starting a debug
+@REM                     session afterwards.
+@REM   --silent          Omits the sign-on message.
+@REM   --timeout         Limits the maximum allowed execution time.
+@REM 
+
+
+@echo off 
+
+if not "%~1" == "" goto debugFile 
+
+@echo on 
+
+"D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\common\bin\cspybat" -f "D:\doc\rtthread\git\rt-thread\bsp\imxrt\imxrt1064-nxp-evk\settings\project.rtthread.general.xcl" --backend -f "D:\doc\rtthread\git\rt-thread\bsp\imxrt\imxrt1064-nxp-evk\settings\project.rtthread.driver.xcl" 
+
+@echo off 
+goto end 
+
+:debugFile 
+
+@echo on 
+
+"D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\common\bin\cspybat" -f "D:\doc\rtthread\git\rt-thread\bsp\imxrt\imxrt1064-nxp-evk\settings\project.rtthread.general.xcl" "--debug_file=%~1" --backend -f "D:\doc\rtthread\git\rt-thread\bsp\imxrt\imxrt1064-nxp-evk\settings\project.rtthread.driver.xcl" 
+
+@echo off 
+:end
\ No newline at end of file

bsp/imxrt/Libraries/templates/imxrt1064xxx/settings/project.rtthread.general.xcl

+"D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\arm\bin\armproc.dll" 
+
+"D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\arm\bin\armJET.dll" 
+
+"D:\doc\rtthread\git\rt-thread\bsp\imxrt\imxrt1064-nxp-evk\build\iar\Exe\rtthread.out" 
+
+--plugin="D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\arm\bin\armbat.dll" 
+
+--device_macro="D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\arm\config\debugger\NXP\iMXRT.dmac" 
+
+--device_macro="D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\arm\config\debugger\NXP\iMXRT_Trace.dmac" 
+
+--flash_loader="D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\arm\config\flashloader\NXP\FlashIMXRT1064_SIP.board" 
+
+
+
+