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62f764ed
编写于
4月 09, 2021
作者:
F
fenghuijie
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
add type modifier for immediate data
上级
0b4416f0
变更
1
隐藏空白更改
内联
并排
Showing
1 changed file
with
114 addition
and
113 deletion
+114
-113
libcpu/arm/cortex-a/gic.c
libcpu/arm/cortex-a/gic.c
+114
-113
未找到文件。
libcpu/arm/cortex-a/gic.c
浏览文件 @
62f764ed
...
...
@@ -17,10 +17,6 @@
#include "gic.h"
#include "cp15.h"
#ifdef RT_USING_FINSH
#include <finsh.h>
#endif
struct
arm_gic
{
rt_uint32_t
offset
;
/* the first interrupt index in the vector table */
...
...
@@ -34,33 +30,33 @@ static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
/** Macro to access the Generic Interrupt Controller Interface (GICC)
*/
#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00)
#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04)
#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08)
#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c)
#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10)
#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14)
#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18)
#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFC)
#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00
U
)
#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04
U
)
#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08
U
)
#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c
U
)
#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10
U
)
#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14
U
)
#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18
U
)
#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFC
U
)
/** Macro to access the Generic Interrupt Controller Distributor (GICD)
*/
#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000)
#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004)
#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080
+ ((n)/32) * 4
)
#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100
+ ((n)/32) * 4
)
#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180
+ ((n)/32) * 4
)
#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200
+ ((n)/32) * 4
)
#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280
+ ((n)/32) * 4
)
#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300
+ ((n)/32) * 4
)
#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380
+ ((n)/32) * 4
)
#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400
+ ((n)/4) * 4
)
#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800
+ ((n)/4) * 4
)
#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00
+ ((n)/16) * 4
)
#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00)
#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10
+ ((n)/4) * 4
)
#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20
+ ((n)/4) * 4
)
#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8)
#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000
U
)
#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004
U
)
#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080
U + ((n)/32U) * 4U
)
#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100
U + ((n)/32U) * 4U
)
#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180
U + ((n)/32U) * 4U
)
#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200
U + ((n)/32U) * 4U
)
#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280
U + ((n)/32U) * 4U
)
#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300
U + ((n)/32U) * 4U
)
#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380
U + ((n)/32U) * 4U
)
#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400
U + ((n)/4U) * 4U
)
#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800
U + ((n)/4U) * 4U
)
#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00
U + ((n)/16U) * 4U
)
#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00
U
)
#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10
U + ((n)/4U) * 4U
)
#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20
U + ((n)/4U) * 4U
)
#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8
U
)
static
unsigned
int
_gic_max_irq
;
...
...
@@ -77,12 +73,12 @@ int arm_gic_get_active_irq(rt_uint32_t index)
void
arm_gic_ack
(
rt_uint32_t
index
,
int
irq
)
{
rt_uint32_t
mask
=
1
<<
(
irq
%
32
);
rt_uint32_t
mask
=
1
U
<<
(
irq
%
32U
);
RT_ASSERT
(
index
<
ARM_GIC_MAX_NR
);
irq
=
irq
-
_gic_table
[
index
].
offset
;
RT_ASSERT
(
irq
>=
0
);
RT_ASSERT
(
irq
>=
0
U
);
GIC_DIST_PENDING_CLEAR
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
=
mask
;
GIC_CPU_EOI
(
_gic_table
[
index
].
cpu_hw_base
)
=
irq
;
...
...
@@ -90,24 +86,24 @@ void arm_gic_ack(rt_uint32_t index, int irq)
void
arm_gic_mask
(
rt_uint32_t
index
,
int
irq
)
{
rt_uint32_t
mask
=
1
<<
(
irq
%
32
);
rt_uint32_t
mask
=
1
U
<<
(
irq
%
32U
);
RT_ASSERT
(
index
<
ARM_GIC_MAX_NR
);
irq
=
irq
-
_gic_table
[
index
].
offset
;
RT_ASSERT
(
irq
>=
0
);
RT_ASSERT
(
irq
>=
0
U
);
GIC_DIST_ENABLE_CLEAR
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
=
mask
;
}
void
arm_gic_umask
(
rt_uint32_t
index
,
int
irq
)
{
rt_uint32_t
mask
=
1
<<
(
irq
%
32
);
rt_uint32_t
mask
=
1
U
<<
(
irq
%
32U
);
RT_ASSERT
(
index
<
ARM_GIC_MAX_NR
);
irq
=
irq
-
_gic_table
[
index
].
offset
;
RT_ASSERT
(
irq
>=
0
);
RT_ASSERT
(
irq
>=
0
U
);
GIC_DIST_ENABLE_SET
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
=
mask
;
}
...
...
@@ -119,24 +115,24 @@ rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq)
RT_ASSERT
(
index
<
ARM_GIC_MAX_NR
);
irq
=
irq
-
_gic_table
[
index
].
offset
;
RT_ASSERT
(
irq
>=
0
);
RT_ASSERT
(
irq
>=
0
U
);
if
(
irq
>=
16
)
if
(
irq
>=
16
U
)
{
pend
=
(
GIC_DIST_PENDING_SET
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
>>
(
irq
%
32
))
&
0x1
;
pend
=
(
GIC_DIST_PENDING_SET
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
>>
(
irq
%
32
U
))
&
0x1UL
;
}
else
{
/* INTID 0-15 Software Generated Interrupt */
pend
=
(
GIC_DIST_SPENDSGI
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
>>
((
irq
%
4
)
*
8
))
&
0xFF
;
pend
=
(
GIC_DIST_SPENDSGI
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
>>
((
irq
%
4
U
)
*
8U
))
&
0xFFUL
;
/* No CPU identification offered */
if
(
pend
!=
0
)
if
(
pend
!=
0
U
)
{
pend
=
1
;
pend
=
1
U
;
}
else
{
pend
=
0
;
pend
=
0
U
;
}
}
...
...
@@ -148,17 +144,17 @@ void arm_gic_set_pending_irq(rt_uint32_t index, int irq)
RT_ASSERT
(
index
<
ARM_GIC_MAX_NR
);
irq
=
irq
-
_gic_table
[
index
].
offset
;
RT_ASSERT
(
irq
>=
0
);
RT_ASSERT
(
irq
>=
0
U
);
if
(
irq
>=
16
)
if
(
irq
>=
16
U
)
{
GIC_DIST_PENDING_SET
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
=
1
<<
(
irq
%
32
);
GIC_DIST_PENDING_SET
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
=
1
U
<<
(
irq
%
32U
);
}
else
{
/* INTID 0-15 Software Generated Interrupt */
/* Forward the interrupt to the CPU interface that requested it */
GIC_DIST_SOFTINT
(
_gic_table
[
index
].
dist_hw_base
)
=
(
irq
|
0x02000000
);
GIC_DIST_SOFTINT
(
_gic_table
[
index
].
dist_hw_base
)
=
(
irq
|
0x02000000
U
);
}
}
...
...
@@ -169,16 +165,16 @@ void arm_gic_clear_pending_irq(rt_uint32_t index, int irq)
RT_ASSERT
(
index
<
ARM_GIC_MAX_NR
);
irq
=
irq
-
_gic_table
[
index
].
offset
;
RT_ASSERT
(
irq
>=
0
);
RT_ASSERT
(
irq
>=
0
U
);
if
(
irq
>=
16
)
if
(
irq
>=
16
U
)
{
mask
=
1
<<
(
irq
%
32
);
mask
=
1
U
<<
(
irq
%
32U
);
GIC_DIST_PENDING_CLEAR
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
=
mask
;
}
else
{
mask
=
1
<<
((
irq
%
4
)
*
8
);
mask
=
1
U
<<
((
irq
%
4U
)
*
8U
);
GIC_DIST_CPENDSGI
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
=
mask
;
}
}
...
...
@@ -191,12 +187,12 @@ void arm_gic_set_configuration(rt_uint32_t index, int irq, uint32_t config)
RT_ASSERT
(
index
<
ARM_GIC_MAX_NR
);
irq
=
irq
-
_gic_table
[
index
].
offset
;
RT_ASSERT
(
irq
>=
0
);
RT_ASSERT
(
irq
>=
0
U
);
icfgr
=
GIC_DIST_CONFIG
(
_gic_table
[
index
].
dist_hw_base
,
irq
);
shift
=
(
irq
%
16
)
<<
1
;
shift
=
(
irq
%
16
U
)
<<
1U
;
icfgr
&=
(
~
(
3
<<
shift
));
icfgr
&=
(
~
(
3
U
<<
shift
));
icfgr
|=
(
config
<<
shift
);
GIC_DIST_CONFIG
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
=
icfgr
;
...
...
@@ -207,19 +203,19 @@ rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq)
RT_ASSERT
(
index
<
ARM_GIC_MAX_NR
);
irq
=
irq
-
_gic_table
[
index
].
offset
;
RT_ASSERT
(
irq
>=
0
);
RT_ASSERT
(
irq
>=
0
U
);
return
(
GIC_DIST_CONFIG
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
>>
((
irq
%
16
)
>>
1
));
return
(
GIC_DIST_CONFIG
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
>>
((
irq
%
16
U
)
>>
1U
));
}
void
arm_gic_clear_active
(
rt_uint32_t
index
,
int
irq
)
{
rt_uint32_t
mask
=
1
<<
(
irq
%
32
);
rt_uint32_t
mask
=
1
U
<<
(
irq
%
32U
);
RT_ASSERT
(
index
<
ARM_GIC_MAX_NR
);
irq
=
irq
-
_gic_table
[
index
].
offset
;
RT_ASSERT
(
irq
>=
0
);
RT_ASSERT
(
irq
>=
0
U
);
GIC_DIST_ACTIVE_CLEAR
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
=
mask
;
}
...
...
@@ -232,12 +228,12 @@ void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask)
RT_ASSERT
(
index
<
ARM_GIC_MAX_NR
);
irq
=
irq
-
_gic_table
[
index
].
offset
;
RT_ASSERT
(
irq
>=
0
);
RT_ASSERT
(
irq
>=
0
U
);
old_tgt
=
GIC_DIST_TARGET
(
_gic_table
[
index
].
dist_hw_base
,
irq
);
old_tgt
&=
~
(
0x0FF
<<
((
irq
%
4
)
*
8
));
old_tgt
|=
cpumask
<<
((
irq
%
4
)
*
8
);
old_tgt
&=
~
(
0x0FF
UL
<<
((
irq
%
4U
)
*
8U
));
old_tgt
|=
cpumask
<<
((
irq
%
4
U
)
*
8U
);
GIC_DIST_TARGET
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
=
old_tgt
;
}
...
...
@@ -247,9 +243,9 @@ rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq)
RT_ASSERT
(
index
<
ARM_GIC_MAX_NR
);
irq
=
irq
-
_gic_table
[
index
].
offset
;
RT_ASSERT
(
irq
>=
0
);
RT_ASSERT
(
irq
>=
0
U
);
return
(
GIC_DIST_TARGET
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
>>
((
irq
%
4
)
*
8
))
&
0xFF
;
return
(
GIC_DIST_TARGET
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
>>
((
irq
%
4
U
)
*
8U
))
&
0xFFUL
;
}
void
arm_gic_set_priority
(
rt_uint32_t
index
,
int
irq
,
rt_uint32_t
priority
)
...
...
@@ -259,11 +255,11 @@ void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority)
RT_ASSERT
(
index
<
ARM_GIC_MAX_NR
);
irq
=
irq
-
_gic_table
[
index
].
offset
;
RT_ASSERT
(
irq
>=
0
);
RT_ASSERT
(
irq
>=
0
U
);
mask
=
GIC_DIST_PRI
(
_gic_table
[
index
].
dist_hw_base
,
irq
);
mask
&=
~
(
0xFF
<<
((
irq
%
4
)
*
8
));
mask
|=
((
priority
&
0xFF
)
<<
((
irq
%
4
)
*
8
));
mask
&=
~
(
0xFF
UL
<<
((
irq
%
4U
)
*
8U
));
mask
|=
((
priority
&
0xFF
UL
)
<<
((
irq
%
4U
)
*
8U
));
GIC_DIST_PRI
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
=
mask
;
}
...
...
@@ -272,9 +268,9 @@ rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq)
RT_ASSERT
(
index
<
ARM_GIC_MAX_NR
);
irq
=
irq
-
_gic_table
[
index
].
offset
;
RT_ASSERT
(
irq
>=
0
);
RT_ASSERT
(
irq
>=
0
U
);
return
(
GIC_DIST_PRI
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
>>
((
irq
%
4
)
*
8
))
&
0xFF
;
return
(
GIC_DIST_PRI
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
>>
((
irq
%
4
U
)
*
8U
))
&
0xFFUL
;
}
void
arm_gic_set_interface_prior_mask
(
rt_uint32_t
index
,
rt_uint32_t
priority
)
...
...
@@ -282,7 +278,7 @@ void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority)
RT_ASSERT
(
index
<
ARM_GIC_MAX_NR
);
/* set priority mask */
GIC_CPU_PRIMASK
(
_gic_table
[
index
].
cpu_hw_base
)
=
priority
&
0xFF
;
GIC_CPU_PRIMASK
(
_gic_table
[
index
].
cpu_hw_base
)
=
priority
&
0xFF
UL
;
}
rt_uint32_t
arm_gic_get_interface_prior_mask
(
rt_uint32_t
index
)
...
...
@@ -294,7 +290,7 @@ rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index)
void
arm_gic_set_binary_point
(
rt_uint32_t
index
,
rt_uint32_t
binary_point
)
{
GIC_CPU_BINPOINT
(
_gic_table
[
index
].
cpu_hw_base
)
=
binary_point
&
0x7
;
GIC_CPU_BINPOINT
(
_gic_table
[
index
].
cpu_hw_base
)
=
binary_point
&
0x7
U
;
}
rt_uint32_t
arm_gic_get_binary_point
(
rt_uint32_t
index
)
...
...
@@ -310,12 +306,12 @@ rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq)
RT_ASSERT
(
index
<
ARM_GIC_MAX_NR
);
irq
=
irq
-
_gic_table
[
index
].
offset
;
RT_ASSERT
(
irq
>=
0
);
RT_ASSERT
(
irq
>=
0
U
);
active
=
(
GIC_DIST_ACTIVE_SET
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
>>
(
irq
%
32
))
&
0x1
;
pending
=
(
GIC_DIST_PENDING_SET
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
>>
(
irq
%
32
))
&
0x1
;
active
=
(
GIC_DIST_ACTIVE_SET
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
>>
(
irq
%
32
U
))
&
0x1UL
;
pending
=
(
GIC_DIST_PENDING_SET
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
>>
(
irq
%
32
U
))
&
0x1UL
;
return
((
active
<<
1
)
|
pending
);
return
((
active
<<
1
U
)
|
pending
);
}
void
arm_gic_send_sgi
(
rt_uint32_t
index
,
int
irq
,
rt_uint32_t
target_list
,
rt_uint32_t
filter_list
)
...
...
@@ -323,9 +319,9 @@ void arm_gic_send_sgi(rt_uint32_t index, int irq, rt_uint32_t target_list, rt_ui
RT_ASSERT
(
index
<
ARM_GIC_MAX_NR
);
irq
=
irq
-
_gic_table
[
index
].
offset
;
RT_ASSERT
(
irq
>=
0
);
RT_ASSERT
(
irq
>=
0
U
);
GIC_DIST_SOFTINT
(
_gic_table
[
index
].
dist_hw_base
)
=
((
filter_list
&
0x3
)
<<
24
)
|
((
target_list
&
0xFF
)
<<
16
)
|
(
irq
&
0x0F
);
GIC_DIST_SOFTINT
(
_gic_table
[
index
].
dist_hw_base
)
=
((
filter_list
&
0x3
U
)
<<
24U
)
|
((
target_list
&
0xFFUL
)
<<
16U
)
|
(
irq
&
0x0FUL
);
}
rt_uint32_t
arm_gic_get_high_pending_irq
(
rt_uint32_t
index
)
...
...
@@ -348,15 +344,15 @@ void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group)
uint32_t
shift
;
RT_ASSERT
(
index
<
ARM_GIC_MAX_NR
);
RT_ASSERT
(
group
<=
1
);
RT_ASSERT
(
group
<=
1
U
);
irq
=
irq
-
_gic_table
[
index
].
offset
;
RT_ASSERT
(
irq
>=
0
);
RT_ASSERT
(
irq
>=
0
U
);
igroupr
=
GIC_DIST_IGROUP
(
_gic_table
[
index
].
dist_hw_base
,
irq
);
shift
=
(
irq
%
32
);
igroupr
&=
(
~
(
1
<<
shift
));
igroupr
|=
(
(
group
&
0x1
)
<<
shift
);
shift
=
(
irq
%
32
U
);
igroupr
&=
(
~
(
1
U
<<
shift
));
igroupr
|=
(
(
group
&
0x1
U
)
<<
shift
);
GIC_DIST_IGROUP
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
=
igroupr
;
}
...
...
@@ -366,15 +362,15 @@ rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq)
RT_ASSERT
(
index
<
ARM_GIC_MAX_NR
);
irq
=
irq
-
_gic_table
[
index
].
offset
;
RT_ASSERT
(
irq
>=
0
);
RT_ASSERT
(
irq
>=
0
U
);
return
(
GIC_DIST_IGROUP
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
>>
(
irq
%
32
))
&
0x1
;
return
(
GIC_DIST_IGROUP
(
_gic_table
[
index
].
dist_hw_base
,
irq
)
>>
(
irq
%
32
U
))
&
0x1UL
;
}
int
arm_gic_dist_init
(
rt_uint32_t
index
,
rt_uint32_t
dist_base
,
int
irq_start
)
{
unsigned
int
gic_type
,
i
;
rt_uint32_t
cpumask
=
1
<<
0
;
rt_uint32_t
cpumask
=
1
U
<<
0U
;
RT_ASSERT
(
index
<
ARM_GIC_MAX_NR
);
...
...
@@ -383,50 +379,50 @@ int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start)
/* Find out how many interrupts are supported. */
gic_type
=
GIC_DIST_TYPE
(
dist_base
);
_gic_max_irq
=
((
gic_type
&
0x1f
)
+
1
)
*
32
;
_gic_max_irq
=
((
gic_type
&
0x1f
U
)
+
1U
)
*
32U
;
/*
* The GIC only supports up to 1020 interrupt sources.
* Limit this to either the architected maximum, or the
* platform maximum.
*/
if
(
_gic_max_irq
>
1020
)
_gic_max_irq
=
1020
;
if
(
_gic_max_irq
>
1020
U
)
_gic_max_irq
=
1020
U
;
if
(
_gic_max_irq
>
ARM_GIC_NR_IRQS
)
/* the platform maximum interrupts */
_gic_max_irq
=
ARM_GIC_NR_IRQS
;
cpumask
|=
cpumask
<<
8
;
cpumask
|=
cpumask
<<
16
;
cpumask
|=
cpumask
<<
24
;
cpumask
|=
cpumask
<<
8
U
;
cpumask
|=
cpumask
<<
16
U
;
cpumask
|=
cpumask
<<
24
U
;
GIC_DIST_CTRL
(
dist_base
)
=
0x0
;
GIC_DIST_CTRL
(
dist_base
)
=
0x0
U
;
/* Set all global interrupts to be level triggered, active low. */
for
(
i
=
32
;
i
<
_gic_max_irq
;
i
+=
16
)
GIC_DIST_CONFIG
(
dist_base
,
i
)
=
0x0
;
for
(
i
=
32
U
;
i
<
_gic_max_irq
;
i
+=
16U
)
GIC_DIST_CONFIG
(
dist_base
,
i
)
=
0x0
U
;
/* Set all global interrupts to this CPU only. */
for
(
i
=
32
;
i
<
_gic_max_irq
;
i
+=
4
)
for
(
i
=
32
U
;
i
<
_gic_max_irq
;
i
+=
4U
)
GIC_DIST_TARGET
(
dist_base
,
i
)
=
cpumask
;
/* Set priority on all interrupts. */
for
(
i
=
0
;
i
<
_gic_max_irq
;
i
+=
4
)
GIC_DIST_PRI
(
dist_base
,
i
)
=
0xa0a0a0a0
;
for
(
i
=
0
U
;
i
<
_gic_max_irq
;
i
+=
4U
)
GIC_DIST_PRI
(
dist_base
,
i
)
=
0xa0a0a0a0
U
;
/* Disable all interrupts. */
for
(
i
=
0
;
i
<
_gic_max_irq
;
i
+=
32
)
GIC_DIST_ENABLE_CLEAR
(
dist_base
,
i
)
=
0xffffffff
;
for
(
i
=
0
U
;
i
<
_gic_max_irq
;
i
+=
32U
)
GIC_DIST_ENABLE_CLEAR
(
dist_base
,
i
)
=
0xffffffff
U
;
#if 0
/* All interrupts defaults to IGROUP1(IRQ). */
for (i = 0; i < _gic_max_irq; i += 32)
GIC_DIST_IGROUP(dist_base, i) = 0xffffffff;
#endif
for
(
i
=
0
;
i
<
_gic_max_irq
;
i
+=
32
)
GIC_DIST_IGROUP
(
dist_base
,
i
)
=
0
;
for
(
i
=
0
U
;
i
<
_gic_max_irq
;
i
+=
32U
)
GIC_DIST_IGROUP
(
dist_base
,
i
)
=
0
U
;
/* Enable group0 and group1 interrupt forwarding. */
GIC_DIST_CTRL
(
dist_base
)
=
0x01
;
GIC_DIST_CTRL
(
dist_base
)
=
0x01
U
;
return
0
;
}
...
...
@@ -437,10 +433,10 @@ int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base)
_gic_table
[
index
].
cpu_hw_base
=
cpu_base
;
GIC_CPU_PRIMASK
(
cpu_base
)
=
0xf0
;
GIC_CPU_BINPOINT
(
cpu_base
)
=
0x7
;
GIC_CPU_PRIMASK
(
cpu_base
)
=
0xf0
U
;
GIC_CPU_BINPOINT
(
cpu_base
)
=
0x7
U
;
/* Enable CPU interrupt */
GIC_CPU_CTRL
(
cpu_base
)
=
0x01
;
GIC_CPU_CTRL
(
cpu_base
)
=
0x01
U
;
return
0
;
}
...
...
@@ -451,10 +447,10 @@ void arm_gic_dump_type(rt_uint32_t index)
gic_type
=
GIC_DIST_TYPE
(
_gic_table
[
index
].
dist_hw_base
);
rt_kprintf
(
"GICv%d on %p, max IRQs: %d, %s security extension(%08x)
\n
"
,
(
GIC_DIST_ICPIDR2
(
_gic_table
[
index
].
dist_hw_base
)
>>
4
)
&
0xf
,
(
GIC_DIST_ICPIDR2
(
_gic_table
[
index
].
dist_hw_base
)
>>
4
U
)
&
0xfUL
,
_gic_table
[
index
].
dist_hw_base
,
_gic_max_irq
,
gic_type
&
(
1
<<
10
)
?
"has"
:
"no"
,
gic_type
&
(
1
U
<<
10U
)
?
"has"
:
"no"
,
gic_type
);
}
...
...
@@ -465,30 +461,35 @@ void arm_gic_dump(rt_uint32_t index)
k
=
GIC_CPU_HIGHPRI
(
_gic_table
[
index
].
cpu_hw_base
);
rt_kprintf
(
"--- high pending priority: %d(%08x)
\n
"
,
k
,
k
);
rt_kprintf
(
"--- hw mask ---
\n
"
);
for
(
i
=
0
;
i
<
_gic_max_irq
/
32
;
i
++
)
for
(
i
=
0
U
;
i
<
_gic_max_irq
/
32U
;
i
++
)
{
rt_kprintf
(
"0x%08x, "
,
GIC_DIST_ENABLE_SET
(
_gic_table
[
index
].
dist_hw_base
,
i
*
32
));
i
*
32
U
));
}
rt_kprintf
(
"
\n
--- hw pending ---
\n
"
);
for
(
i
=
0
;
i
<
_gic_max_irq
/
32
;
i
++
)
for
(
i
=
0
U
;
i
<
_gic_max_irq
/
32U
;
i
++
)
{
rt_kprintf
(
"0x%08x, "
,
GIC_DIST_PENDING_SET
(
_gic_table
[
index
].
dist_hw_base
,
i
*
32
));
i
*
32
U
));
}
rt_kprintf
(
"
\n
--- hw active ---
\n
"
);
for
(
i
=
0
;
i
<
_gic_max_irq
/
32
;
i
++
)
for
(
i
=
0
U
;
i
<
_gic_max_irq
/
32U
;
i
++
)
{
rt_kprintf
(
"0x%08x, "
,
GIC_DIST_ACTIVE_SET
(
_gic_table
[
index
].
dist_hw_base
,
i
*
32
));
i
*
32
U
));
}
rt_kprintf
(
"
\n
"
);
}
#ifdef RT_USING_FINSH
FINSH_FUNCTION_EXPORT_ALIAS
(
arm_gic_dump
,
gic
,
show
gic
status
);
#endif
long
gic_dump
(
void
)
{
arm_gic_dump_type
(
0
);
arm_gic_dump
(
0
);
return
0
;
}
MSH_CMD_EXPORT
(
gic_dump
,
show
gic
status
);
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