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574492a2
编写于
1月 08, 2019
作者:
S
SummerGift
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
[bsp][stm32] Modify the DMA implementation
上级
d023fb47
变更
18
展开全部
隐藏空白更改
内联
并排
Showing
18 changed file
with
1172 addition
and
751 deletion
+1172
-751
bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h
bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h
+32
-20
bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h
bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h
+87
-40
bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h
bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h
+92
-51
bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h
bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h
+157
-84
bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h
bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h
+97
-56
bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h
bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h
+3
-6
bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h
bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h
+154
-101
bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h
bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h
+97
-56
bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h
bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h
+2
-5
bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h
bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h
+33
-19
bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h
bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h
+41
-27
bsp/stm32/libraries/HAL_Drivers/drv_config.h
bsp/stm32/libraries/HAL_Drivers/drv_config.h
+5
-0
bsp/stm32/libraries/HAL_Drivers/drv_dma.h
bsp/stm32/libraries/HAL_Drivers/drv_dma.h
+2
-3
bsp/stm32/libraries/HAL_Drivers/drv_qspi.c
bsp/stm32/libraries/HAL_Drivers/drv_qspi.c
+11
-3
bsp/stm32/libraries/HAL_Drivers/drv_spi.c
bsp/stm32/libraries/HAL_Drivers/drv_spi.c
+283
-204
bsp/stm32/libraries/HAL_Drivers/drv_spi.h
bsp/stm32/libraries/HAL_Drivers/drv_spi.h
+8
-6
bsp/stm32/libraries/HAL_Drivers/drv_usart.c
bsp/stm32/libraries/HAL_Drivers/drv_usart.c
+64
-36
bsp/stm32/libraries/HAL_Drivers/drv_usart.h
bsp/stm32/libraries/HAL_Drivers/drv_usart.h
+4
-34
未找到文件。
bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h
浏览文件 @
574492a2
...
...
@@ -15,34 +15,46 @@
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
.dma.Instance = DMA1_Channel3, \
.dma_rcc = RCC_AHBENR_DMA1EN, \
.dma_irq = DMA1_Ch2_3_DMA2_Ch1_2_IRQn, \
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
}
#define USART1_RX_DMA_ISR DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
#endif
/* UART1_CONFIG */
#endif
/* BSP_USING_UART1 */
#if defined(BSP_UART1_RX_USING_DMA)
#ifndef UART1_DMA_CONFIG
#define UART1_DMA_CONFIG \
{ \
.Instance = USART1_RX_DMA_INSTANCE, \
.dma_rcc = USART1_RX_DMA_RCC, \
.dma_irq = USART1_RX_DMA_IRQ, \
}
#endif
/* UART1_DMA_CONFIG */
#endif
/* BSP_UART1_RX_USING_DMA */
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
.dma.Instance = DMA1_Channel3, \
.dma_rcc = RCC_AHBENR_DMA1EN, \
.dma_irq = DMA1_Ch2_3_DMA2_Ch1_2_IRQn, \
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
}
#define USART2_RX_DMA_ISR DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
#endif
/* UART2_CONFIG */
#endif
/* BSP_USING_UART2 */
#if defined(BSP_UART2_RX_USING_DMA)
#ifndef UART2_DMA_CONFIG
#define UART2_DMA_CONFIG \
{ \
.Instance = USART2_RX_DMA_INSTANCE, \
.dma_rcc = USART2_RX_DMA_RCC, \
.dma_irq = USART2_RX_DMA_IRQ, \
}
#endif
/* UART2_DMA_CONFIG */
#endif
/* BSP_UART2_RX_USING_DMA */
#endif
/* __UART_CONFIG_H__ */
bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h
浏览文件 @
574492a2
...
...
@@ -5,7 +5,8 @@
*
* Change Logs:
* Date Author Notes
* 2018-11-06 SummerGift change to new framework
* 2018-11-06 SummerGift first version
* 2019-01-05 SummerGift modify DMA support
*/
#ifndef __SPI_CONFIG_H__
...
...
@@ -14,55 +15,101 @@
#include <rtthread.h>
#ifdef BSP_USING_SPI1
#define SPI1_BUS_CONFIG \
{ \
.Instance = SPI1, \
.bus_name = "spi1", \
.dma_rx.dma_rcc = RCC_AHBENR_DMA1EN, \
.dma_tx.dma_rcc = RCC_AHBENR_DMA1EN, \
.dma_rx.Instance = DMA1_Channel2, \
.dma_rx.dma_irq = DMA1_Channel2_IRQn, \
.dma_tx.Instance = DMA1_Channel3, \
.dma_tx.dma_irq = DMA1_Channel3_IRQn, \
#ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \
{ \
.Instance = SPI1, \
.bus_name = "spi1", \
}
#endif
/* SPI1_BUS_CONFIG */
#endif
/* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI1_TX_DMA_RCC, \
.Instance = SPI1_TX_DMA_INSTANCE, \
.dma_irq = SPI1_TX_DMA_IRQ, \
}
#endif
/* SPI1_TX_DMA_CONFIG */
#endif
/* BSP_SPI1_TX_USING_DMA */
#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler
#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler
#endif
#ifdef BSP_SPI1_RX_USING_DMA
#ifndef SPI1_RX_DMA_CONFIG
#define SPI1_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI1_RX_DMA_RCC, \
.Instance = SPI1_RX_DMA_INSTANCE, \
.dma_irq = SPI1_RX_DMA_IRQ, \
}
#endif
/* SPI1_RX_DMA_CONFIG */
#endif
/* BSP_SPI1_RX_USING_DMA */
#ifdef BSP_USING_SPI2
#define SPI2_BUS_CONFIG \
{ \
.Instance = SPI2, \
.bus_name = "spi2", \
.dma_rx.dma_rcc = RCC_AHBENR_DMA1EN, \
.dma_tx.dma_rcc = RCC_AHBENR_DMA1EN, \
.dma_rx.Instance = DMA1_Channel4, \
.dma_rx.dma_irq = DMA1_Channel4_IRQn, \
.dma_tx.Instance = DMA1_Channel5, \
.dma_tx.dma_irq = DMA1_Channel5_IRQn, \
#ifndef SPI2_BUS_CONFIG
#define SPI2_BUS_CONFIG \
{ \
.Instance = SPI2, \
.bus_name = "spi2", \
}
#endif
/* SPI2_BUS_CONFIG */
#endif
/* BSP_USING_SPI2 */
#define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler
#define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler
#endif
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI2_TX_DMA_RCC, \
.Instance = SPI2_TX_DMA_INSTANCE, \
.dma_irq = SPI2_TX_DMA_IRQ, \
}
#endif
/* SPI2_TX_DMA_CONFIG */
#endif
/* BSP_SPI2_TX_USING_DMA */
#ifdef BSP_SPI2_RX_USING_DMA
#ifndef SPI2_RX_DMA_CONFIG
#define SPI2_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI2_RX_DMA_RCC, \
.Instance = SPI2_RX_DMA_INSTANCE, \
.dma_irq = SPI2_RX_DMA_IRQ, \
}
#endif
/* SPI2_RX_DMA_CONFIG */
#endif
/* BSP_SPI2_RX_USING_DMA */
#ifdef BSP_USING_SPI3
#define SPI3_BUS_CONFIG \
{ \
.Instance = SPI3, \
.bus_name = "spi3", \
.dma_rx.dma_rcc = RCC_AHBENR_DMA2EN, \
.dma_tx.dma_rcc = RCC_AHBENR_DMA2EN, \
.dma_rx.Instance = DMA2_Channel1, \
.dma_rx.dma_irq = DMA2_Channel1_IRQn, \
.dma_tx.Instance = DMA2_Channel2, \
.dma_tx.dma_irq = DMA2_Channel2_IRQn, \
#ifndef SPI3_BUS_CONFIG
#define SPI3_BUS_CONFIG \
{ \
.Instance = SPI3, \
.bus_name = "spi3", \
}
#endif
/* SPI3_BUS_CONFIG */
#endif
/* BSP_USING_SPI3 */
#define SPI3_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler
#define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler
#endif
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI3_TX_DMA_RCC, \
.Instance = SPI3_TX_DMA_INSTANCE, \
.dma_irq = SPI3_TX_DMA_IRQ, \
}
#endif
/* SPI3_TX_DMA_CONFIG */
#endif
/* BSP_SPI3_TX_USING_DMA */
#ifdef BSP_SPI3_RX_USING_DMA
#ifndef SPI3_RX_DMA_CONFIG
#define SPI3_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI3_RX_DMA_RCC, \
.Instance = SPI3_RX_DMA_INSTANCE, \
.dma_irq = SPI3_RX_DMA_IRQ, \
}
#endif
/* SPI3_RX_DMA_CONFIG */
#endif
/* BSP_SPI3_RX_USING_DMA */
#endif
/*__SPI_CONFIG_H__ */
...
...
bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h
浏览文件 @
574492a2
...
...
@@ -5,81 +5,122 @@
*
* Change Logs:
* Date Author Notes
* 2018-10-30 BalanceTWK change to new framework
* 2018-10-30 BalanceTWK first version
* 2019-01-05 SummerGift modify DMA support
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
#include <rtthread.h>
#include "dma_config.h"
#if defined(BSP_USING_UART1)
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
.dma.channel.Instance = DMA1_Channel5, \
.dma_rcc = RCC_AHBENR_DMA1EN, \
.dma_irq = DMA1_Channel5_IRQn, \
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
}
#endif
/* UART1_CONFIG */
#endif
/* BSP_USING_UART1 */
#define USART1_RX_DMA_ISR DMA1_Channel5_IRQHandler
#endif
#if defined(BSP_UART1_RX_USING_DMA)
#ifndef UART1_DMA_CONFIG
#define UART1_DMA_CONFIG \
{ \
.Instance = USART1_RX_DMA_INSTANCE, \
.dma_rcc = USART1_RX_DMA_RCC, \
.dma_irq = USART1_RX_DMA_IRQ, \
}
#endif
/* UART1_DMA_CONFIG */
#endif
/* BSP_UART1_RX_USING_DMA */
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
}
#endif
/* UART2_CONFIG */
#endif
/* BSP_USING_UART2 */
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
.dma.channel.Instance = DMA1_Channel6, \
.dma_rcc = RCC_AHBENR_DMA1EN, \
.dma_irq = DMA1_Channel6_IRQn, \
#if defined(BSP_UART2_RX_USING_DMA)
#ifndef UART2_DMA_CONFIG
#define UART2_DMA_CONFIG \
{ \
.Instance = USART2_RX_DMA_INSTANCE, \
.dma_rcc = USART2_RX_DMA_RCC, \
.dma_irq = USART2_RX_DMA_IRQ, \
}
#endif
/* UART2_DMA_CONFIG */
#endif
/* BSP_UART2_RX_USING_DMA */
#define USART2_RX_DMA_ISR DMA1_Channel6_IRQHandler
#endif
#if defined(BSP_USING_UART3)
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = USART3, \
.irq_type = USART3_IRQn, \
.dma.channel.Instance = DMA1_Channel3, \
.dma_rcc = RCC_AHBENR_DMA1EN, \
.dma_irq = DMA1_Channel3_IRQn, \
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = USART3, \
.irq_type = USART3_IRQn, \
}
#endif
/* UART3_CONFIG */
#endif
/* BSP_USING_UART3 */
#define USART3_RX_DMA_ISR DMA1_Channel3_IRQHandler
#endif
#if defined(BSP_UART3_RX_USING_DMA)
#ifndef UART3_DMA_CONFIG
#define UART3_DMA_CONFIG \
{ \
.Instance = USART3_RX_DMA_INSTANCE, \
.dma_rcc = USART3_RX_DMA_RCC, \
.dma_irq = USART3_RX_DMA_IRQ, \
}
#endif
/* UART3_DMA_CONFIG */
#endif
/* BSP_UART3_RX_USING_DMA */
#if defined(BSP_USING_UART4)
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = UART4, \
.irq_type = UART4_IRQn, \
.dma.channel.Instance = DMA2_Channel3, \
.dma_rcc = RCC_AHBENR_DMA2EN, \
.dma_irq = DMA2_Channel3_IRQn, \
#ifndef UART4_CONFIG
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = UART4, \
.irq_type = UART4_IRQn, \
}
#endif
/* UART4_CONFIG */
#endif
/* BSP_USING_UART4 */
#define USART4_RX_DMA_ISR DMA2_Channel3_IRQHandler
#endif
#if defined(BSP_UART4_RX_USING_DMA)
#ifndef UART4_DMA_CONFIG
#define UART4_DMA_CONFIG \
{ \
.Instance = USART4_RX_DMA_INSTANCE, \
.dma_rcc = USART4_RX_DMA_RCC, \
.dma_irq = USART4_RX_DMA_IRQ, \
}
#endif
/* UART4_DMA_CONFIG */
#endif
/* BSP_UART4_RX_USING_DMA */
#if defined(BSP_USING_UART5)
#ifndef UART5_CONFIG
#define UART5_CONFIG \
{ \
.name = "uart5", \
.Instance = UART5, \
.irq_type = UART5_IRQn, \
}
#endif
/* UART5_CONFIG */
#endif
/* BSP_USING_UART5 */
#define UART5_CONFIG \
{ \
.name = "uart5", \
.Instance = UART5, \
.irq_type = UART5_IRQn, \
.dma.channel.Instance = DMA_NOT_AVAILABLE, \
#if defined(BSP_UART5_RX_USING_DMA)
#ifndef UART5_DMA_CONFIG
#define UART5_DMA_CONFIG \
{ \
.Instance = DMA_NOT_AVAILABLE, \
}
#endif
#endif
/* UART5_DMA_CONFIG */
#endif
/* BSP_UART5_RX_USING_DMA */
#endif
bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h
浏览文件 @
574492a2
...
...
@@ -5,7 +5,8 @@
*
* Change Logs:
* Date Author Notes
* 2018-11-06 SummerGift change to new framework
* 2018-11-06 SummerGift first version
* 2019-01-03 zylx modify DMA support
*/
#ifndef __SPI_CONFIG_H__
...
...
@@ -14,101 +15,173 @@
#include <rtthread.h>
#ifdef BSP_USING_SPI1
#define SPI1_BUS_CONFIG \
{ \
.Instance = SPI1, \
.bus_name = "spi1", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_rx.Instance = DMA2_Stream2, \
.dma_rx.channel = DMA_CHANNEL_3, \
.dma_rx.dma_irq = DMA2_Stream2_IRQn, \
.dma_tx.Instance = DMA2_Stream3, \
.dma_tx.channel = DMA_CHANNEL_3, \
.dma_tx.dma_irq = DMA2_Stream3_IRQn, \
#ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \
{ \
.Instance = SPI1, \
.bus_name = "spi1", \
}
#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler
#endif
#endif
/* SPI1_BUS_CONFIG */
#endif
/* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI1_TX_DMA_RCC, \
.Instance = SPI1_TX_DMA_INSTANCE, \
.channel = SPI1_TX_DMA_CHANNEL, \
.dma_irq = SPI1_TX_DMA_IRQ, \
}
#endif
/* SPI1_TX_DMA_CONFIG */
#endif
/* BSP_SPI1_TX_USING_DMA */
#ifdef BSP_SPI1_RX_USING_DMA
#ifndef SPI1_RX_DMA_CONFIG
#define SPI1_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI1_RX_DMA_RCC, \
.Instance = SPI1_RX_DMA_INSTANCE, \
.channel = SPI1_RX_DMA_CHANNEL, \
.dma_irq = SPI1_RX_DMA_IRQ, \
}
#endif
/* SPI1_RX_DMA_CONFIG */
#endif
/* BSP_SPI1_RX_USING_DMA */
#ifdef BSP_USING_SPI2
#define SPI2_BUS_CONFIG \
{ \
.Instance = SPI2, \
.bus_name = "spi2", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_rx.Instance = DMA1_Stream3, \
.dma_rx.channel = DMA_CHANNEL_0, \
.dma_rx.dma_irq = DMA1_Stream3_IRQn, \
.dma_tx.Instance = DMA1_Stream4, \
.dma_tx.channel = DMA_CHANNEL_0, \
.dma_tx.dma_irq = DMA1_Stream4_IRQn, \
#ifndef SPI2_BUS_CONFIG
#define SPI2_BUS_CONFIG \
{ \
.Instance = SPI2, \
.bus_name = "spi2", \
}
#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler
#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler
#endif
#endif
/* SPI2_BUS_CONFIG */
#endif
/* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI2_TX_DMA_RCC, \
.Instance = SPI2_TX_DMA_INSTANCE, \
.channel = SPI2_TX_DMA_CHANNEL, \
.dma_irq = SPI2_TX_DMA_IRQ, \
}
#endif
/* SPI2_TX_DMA_CONFIG */
#endif
/* BSP_SPI2_TX_USING_DMA */
#ifdef BSP_SPI2_RX_USING_DMA
#ifndef SPI2_RX_DMA_CONFIG
#define SPI2_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI2_RX_DMA_RCC, \
.Instance = SPI2_RX_DMA_INSTANCE, \
.channel = SPI2_RX_DMA_CHANNEL, \
.dma_irq = SPI2_RX_DMA_IRQ, \
}
#endif
/* SPI2_RX_DMA_CONFIG */
#endif
/* BSP_SPI2_RX_USING_DMA */
#ifdef BSP_USING_SPI3
#define SPI3_BUS_CONFIG \
{ \
.Instance = SPI3, \
.bus_name = "spi3", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_rx.Instance = DMA1_Stream0, \
.dma_rx.channel = DMA_CHANNEL_0, \
.dma_rx.dma_irq = DMA1_Stream0_IRQn, \
.dma_tx.Instance = DMA1_Stream5, \
.dma_tx.channel = DMA_CHANNEL_0, \
.dma_tx.dma_irq = DMA1_Stream5_IRQn, \
#ifndef SPI3_BUS_CONFIG
#define SPI3_BUS_CONFIG \
{ \
.Instance = SPI3, \
.bus_name = "spi3", \
}
#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler
#endif
#endif
/* SPI3_BUS_CONFIG */
#endif
/* BSP_USING_SPI3 */
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI3_TX_DMA_RCC, \
.Instance = SPI3_TX_DMA_INSTANCE, \
.channel = SPI3_TX_DMA_CHANNEL, \
.dma_irq = SPI3_TX_DMA_IRQ, \
}
#endif
/* SPI3_TX_DMA_CONFIG */
#endif
/* BSP_SPI3_TX_USING_DMA */
#ifdef BSP_SPI3_RX_USING_DMA
#ifndef SPI3_RX_DMA_CONFIG
#define SPI3_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI3_RX_DMA_RCC, \
.Instance = SPI3_RX_DMA_INSTANCE, \
.channel = SPI3_RX_DMA_CHANNEL, \
.dma_irq = SPI3_RX_DMA_IRQ, \
}
#endif
/* SPI3_RX_DMA_CONFIG */
#endif
/* BSP_SPI3_RX_USING_DMA */
#ifdef BSP_USING_SPI4
#define SPI4_BUS_CONFIG \
{ \
.Instance = SPI4, \
.bus_name = "spi4", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_rx.Instance = DMA2_Stream0, \
.dma_rx.channel = DMA_CHANNEL_4, \
.dma_rx.dma_irq = DMA2_Stream0_IRQn, \
.dma_tx.Instance = DMA2_Stream1, \
.dma_tx.channel = DMA_CHANNEL_4, \
.dma_tx.dma_irq = DMA2_Stream1_IRQn, \
#ifndef SPI4_BUS_CONFIG
#define SPI4_BUS_CONFIG \
{ \
.Instance = SPI4, \
.bus_name = "spi4", \
}
#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler
#endif
#endif
/* SPI4_BUS_CONFIG */
#endif
/* BSP_USING_SPI4 */
#ifdef BSP_SPI4_TX_USING_DMA
#ifndef SPI4_TX_DMA_CONFIG
#define SPI4_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI4_TX_DMA_RCC, \
.Instance = SPI4_TX_DMA_INSTANCE, \
.channel = SPI4_TX_DMA_CHANNEL, \
.dma_irq = SPI4_TX_DMA_IRQ, \
}
#endif
/* SPI4_TX_DMA_CONFIG */
#endif
/* BSP_SPI4_TX_USING_DMA */
#ifdef BSP_SPI4_RX_USING_DMA
#ifndef SPI4_RX_DMA_CONFIG
#define SPI4_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI4_RX_DMA_RCC, \
.Instance = SPI4_RX_DMA_INSTANCE, \
.channel = SPI4_RX_DMA_CHANNEL, \
.dma_irq = SPI4_RX_DMA_IRQ, \
}
#endif
/* SPI4_RX_DMA_CONFIG */
#endif
/* BSP_SPI4_RX_USING_DMA */
#ifdef BSP_USING_SPI5
#define SPI5_BUS_CONFIG \
{ \
.Instance = SPI5, \
.bus_name = "spi5", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_rx.Instance = DMA2_Stream3, \
.dma_rx.channel = DMA_CHANNEL_2, \
.dma_rx.dma_irq = DMA2_Stream3_IRQn, \
.dma_tx.Instance = DMA2_Stream4, \
.dma_tx.channel = DMA_CHANNEL_2, \
.dma_tx.dma_irq = DMA2_Stream4_IRQn, \
#ifndef SPI5_BUS_CONFIG
#define SPI5_BUS_CONFIG \
{ \
.Instance = SPI5, \
.bus_name = "spi5", \
}
#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
#endif
#endif
/* SPI5_BUS_CONFIG */
#endif
/* BSP_USING_SPI5 */
#ifdef BSP_SPI5_TX_USING_DMA
#ifndef SPI5_TX_DMA_CONFIG
#define SPI5_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI5_TX_DMA_RCC, \
.Instance = SPI5_TX_DMA_INSTANCE, \
.channel = SPI5_TX_DMA_CHANNEL, \
.dma_irq = SPI5_TX_DMA_IRQ, \
}
#endif
/* SPI5_TX_DMA_CONFIG */
#endif
/* BSP_SPI5_TX_USING_DMA */
#ifdef BSP_SPI5_RX_USING_DMA
#ifndef SPI5_RX_DMA_CONFIG
#define SPI5_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI5_RX_DMA_RCC, \
.Instance = SPI5_RX_DMA_INSTANCE, \
.channel = SPI5_RX_DMA_CHANNEL, \
.dma_irq = SPI5_RX_DMA_IRQ, \
}
#endif
/* SPI5_RX_DMA_CONFIG */
#endif
/* BSP_SPI5_RX_USING_DMA */
#endif
/*__SPI_CONFIG_H__ */
bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h
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@@ -5,7 +5,8 @@
*
* Change Logs:
* Date Author Notes
* 2018-10-30 SummerGift change to new framework
* 2018-10-30 SummerGift first version
* 2019-01-03 zylx modify dma support
*/
#ifndef __UART_CONFIG_H__
...
...
@@ -14,78 +15,118 @@
#include <rtthread.h>
#if defined(BSP_USING_UART1)
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
.dma.stream_channel.Instance = DMA2_Stream5, \
.dma.stream_channel.channel = DMA_CHANNEL_4, \
.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_irq = DMA2_Stream5_IRQn, \
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
}
#endif
/* UART1_CONFIG */
#endif
/* BSP_USING_UART1 */
#define USART1_RX_DMA_ISR DMA2_Stream5_IRQHandler
#endif
#if defined(BSP_UART1_RX_USING_DMA)
#ifndef UART1_DMA_CONFIG
#define UART1_DMA_CONFIG \
{ \
.Instance = USART1_RX_DMA_INSTANCE, \
.channel = USART1_RX_DMA_CHANNEL, \
.dma_rcc = USART1_RX_DMA_RCC, \
.dma_irq = USART1_RX_DMA_IRQ, \
}
#endif
/* UART1_DMA_CONFIG */
#endif
/* BSP_UART1_RX_USING_DMA */
#if defined(BSP_USING_UART2)
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
.dma.stream_channel.Instance = DMA1_Stream5, \
.dma.stream_channel.channel = DMA_CHANNEL_4, \
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_irq = DMA1_Stream5_IRQn, \
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
}
#endif
/* UART2_CONFIG */
#endif
/* BSP_USING_UART2 */
#define USART2_RX_DMA_ISR DMA1_Stream5_IRQHandler
#endif
#if defined(BSP_UART2_RX_USING_DMA)
#ifndef UART2_DMA_CONFIG
#define UART2_DMA_CONFIG \
{ \
.Instance = USART2_RX_DMA_INSTANCE, \
.channel = USART2_RX_DMA_CHANNEL, \
.dma_rcc = USART2_RX_DMA_RCC, \
.dma_irq = USART2_RX_DMA_IRQ, \
}
#endif
/* UART2_DMA_CONFIG */
#endif
/* BSP_UART2_RX_USING_DMA */
#if defined(BSP_USING_UART3)
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = USART3, \
.irq_type = USART3_IRQn, \
.dma.stream_channel.Instance = DMA1_Stream1, \
.dma.stream_channel.channel = DMA_CHANNEL_4, \
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_irq = DMA1_Stream1_IRQn, \
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = USART3, \
.irq_type = USART3_IRQn, \
}
#endif
/* UART3_CONFIG */
#endif
/* BSP_USING_UART3 */
#define USART3_RX_DMA_ISR DMA1_Stream1_IRQHandler
#endif
#if defined(BSP_UART3_RX_USING_DMA)
#ifndef UART3_DMA_CONFIG
#define UART3_DMA_CONFIG \
{ \
.Instance = USART3_RX_DMA_INSTANCE, \
.channel = USART3_RX_DMA_CHANNEL, \
.dma_rcc = USART3_RX_DMA_RCC, \
.dma_irq = USART3_RX_DMA_IRQ, \
}
#endif
/* UART3_DMA_CONFIG */
#endif
/* BSP_UART3_RX_USING_DMA */
#if defined(BSP_USING_UART4)
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = UART4, \
.irq_type = UART4_IRQn, \
.dma.stream_channel.Instance = DMA1_Stream2, \
.dma.stream_channel.channel = DMA_CHANNEL_4, \
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_irq = DMA1_Stream2_IRQn, \
#ifndef UART4_CONFIG
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = UART4, \
.irq_type = UART4_IRQn, \
}
#endif
/* UART4_CONFIG */
#endif
/* BSP_USING_UART4 */
#define USART4_RX_DMA_ISR DMA1_Stream2_IRQHandler
#endif
#if defined(BSP_UART4_RX_USING_DMA)
#ifndef UART4_DMA_CONFIG
#define UART4_DMA_CONFIG \
{ \
.Instance = USART4_RX_DMA_INSTANCE, \
.channel = USART4_RX_DMA_CHANNEL, \
.dma_rcc = USART4_RX_DMA_RCC, \
.dma_irq = USART4_RX_DMA_IRQ, \
}
#endif
/* UART4_DMA_CONFIG */
#endif
/* BSP_UART4_RX_USING_DMA */
#if defined(BSP_USING_UART5)
#define UART5_CONFIG \
{ \
.name = "uart5", \
.Instance = UART5, \
.irq_type = UART5_IRQn, \
.dma.stream_channel.Instance = DMA1_Stream0, \
.dma.stream_channel.channel = DMA_CHANNEL_4, \
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_irq = DMA1_Stream0_IRQn, \
#ifndef UART5_CONFIG
#define UART5_CONFIG \
{ \
.name = "uart5", \
.Instance = UART5, \
.irq_type = UART5_IRQn, \
}
#endif
/* UART5_CONFIG */
#endif
/* BSP_USING_UART5 */
#define USART5_RX_DMA_ISR DMA1_Stream0_IRQHandler
#endif
#if defined(BSP_UART5_RX_USING_DMA)
#ifndef UART5_DMA_CONFIG
#define UART5_DMA_CONFIG \
{ \
.Instance = USART5_RX_DMA_INSTANCE, \
.channel = USART5_RX_DMA_CHANNEL, \
.dma_rcc = USART5_RX_DMA_RCC, \
.dma_irq = USART5_RX_DMA_IRQ, \
}
#endif
/* UART5_DMA_CONFIG */
#endif
/* BSP_UART5_RX_USING_DMA */
#endif
bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h
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@@ -24,13 +24,13 @@
}
#endif
/* QSPI_BUS_CONFIG */
#endif
/* BSP_USING_QSPI */
#ifdef BSP_QSPI_USING_DMA
#ifndef QSPI_DMA_CONFIG
#define QSPI_DMA_CONFIG \
{ \
.Instance =
DMA2_Stream7,
\
.Init.Channel =
DMA_CHANNEL_3,
\
.Instance =
QSPI_DMA_INSTANCE,
\
.Init.Channel =
QSPI_DMA_CHANNEL,
\
.Init.Direction = DMA_PERIPH_TO_MEMORY, \
.Init.PeriphInc = DMA_PINC_DISABLE, \
.Init.MemInc = DMA_MINC_ENABLE, \
...
...
@@ -42,10 +42,7 @@
#endif
/* QSPI_DMA_CONFIG */
#endif
/* BSP_QSPI_USING_DMA */
#define QSPI_DMA_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE()
#define QSPI_IRQn QUADSPI_IRQn
#define QSPI_DMA_IRQn DMA2_Stream7_IRQn
#define QSPI_IRQHandler QUADSPI_IRQHandler
#define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler
#endif
/* __QSPI_CONFIG_H__ */
bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h
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#include <rtthread.h>
#ifdef BSP_USING_SPI1
#define SPI1_BUS_CONFIG \
{ \
.Instance = SPI1, \
.bus_name = "spi1", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_rx.Instance = DMA2_Stream2, \
.dma_rx.channel = DMA_CHANNEL_3, \
.dma_rx.dma_irq = DMA2_Stream2_IRQn, \
.dma_tx.Instance = DMA2_Stream3, \
.dma_tx.channel = DMA_CHANNEL_3, \
.dma_tx.dma_irq = DMA2_Stream3_IRQn, \
#ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \
{ \
.Instance = SPI1, \
.bus_name = "spi1", \
}
#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler
#endif
#endif
/* SPI1_BUS_CONFIG */
#endif
/* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI1_TX_DMA_RCC, \
.Instance = SPI1_TX_DMA_INSTANCE, \
.channel = SPI1_TX_DMA_CHANNEL, \
.dma_irq = SPI1_TX_DMA_IRQ, \
}
#endif
/* SPI1_TX_DMA_CONFIG */
#endif
/* BSP_SPI1_TX_USING_DMA */
#ifdef BSP_SPI1_RX_USING_DMA
#ifndef SPI1_RX_DMA_CONFIG
#define SPI1_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI1_RX_DMA_RCC, \
.Instance = SPI1_RX_DMA_INSTANCE, \
.channel = SPI1_RX_DMA_CHANNEL, \
.dma_irq = SPI1_RX_DMA_IRQ, \
}
#endif
/* SPI1_RX_DMA_CONFIG */
#endif
/* BSP_SPI1_RX_USING_DMA */
#ifdef BSP_USING_SPI2
#define SPI2_BUS_CONFIG \
{ \
.Instance = SPI2, \
.bus_name = "spi2", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_rx.Instance = DMA1_Stream3, \
.dma_rx.channel = DMA_CHANNEL_0, \
.dma_rx.dma_irq = DMA1_Stream3_IRQn, \
.dma_tx.Instance = DMA1_Stream4, \
.dma_tx.channel = DMA_CHANNEL_0, \
.dma_tx.dma_irq = DMA1_Stream4_IRQn, \
#ifndef SPI2_BUS_CONFIG
#define SPI2_BUS_CONFIG \
{ \
.Instance = SPI2, \
.bus_name = "spi2", \
}
#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler
#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler
#endif
#endif
/* SPI2_BUS_CONFIG */
#endif
/* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI2_TX_DMA_RCC, \
.Instance = SPI2_TX_DMA_INSTANCE, \
.channel = SPI2_TX_DMA_CHANNEL, \
.dma_irq = SPI2_TX_DMA_IRQ, \
}
#endif
/* SPI2_TX_DMA_CONFIG */
#endif
/* BSP_SPI2_TX_USING_DMA */
#ifdef BSP_SPI2_RX_USING_DMA
#ifndef SPI2_RX_DMA_CONFIG
#define SPI2_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI2_RX_DMA_RCC, \
.Instance = SPI2_RX_DMA_INSTANCE, \
.channel = SPI2_RX_DMA_CHANNEL, \
.dma_irq = SPI2_RX_DMA_IRQ, \
}
#endif
/* SPI2_RX_DMA_CONFIG */
#endif
/* BSP_SPI2_RX_USING_DMA */
#ifdef BSP_USING_SPI3
#define SPI3_BUS_CONFIG \
{ \
.Instance = SPI3, \
.bus_name = "spi3", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_rx.Instance = DMA1_Stream0, \
.dma_rx.channel = DMA_CHANNEL_0, \
.dma_rx.dma_irq = DMA1_Stream0_IRQn, \
.dma_tx.Instance = DMA1_Stream7, \
.dma_tx.channel = DMA_CHANNEL_0, \
.dma_tx.dma_irq = DMA1_Stream7_IRQn, \
#ifndef SPI3_BUS_CONFIG
#define SPI3_BUS_CONFIG \
{ \
.Instance = SPI3, \
.bus_name = "spi3", \
}
#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler
#endif
#endif
/* SPI3_BUS_CONFIG */
#endif
/* BSP_USING_SPI3 */
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI3_TX_DMA_RCC, \
.Instance = SPI3_TX_DMA_INSTANCE, \
.channel = SPI3_TX_DMA_CHANNEL, \
.dma_irq = SPI3_TX_DMA_IRQ, \
}
#endif
/* SPI3_TX_DMA_CONFIG */
#endif
/* BSP_SPI3_TX_USING_DMA */
#ifdef BSP_SPI3_RX_USING_DMA
#ifndef SPI3_RX_DMA_CONFIG
#define SPI3_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI3_RX_DMA_RCC, \
.Instance = SPI3_RX_DMA_INSTANCE, \
.channel = SPI3_RX_DMA_CHANNEL, \
.dma_irq = SPI3_RX_DMA_IRQ, \
}
#endif
/* SPI3_RX_DMA_CONFIG */
#endif
/* BSP_SPI3_RX_USING_DMA */
#ifdef BSP_USING_SPI4
#define SPI4_BUS_CONFIG \
{ \
.Instance = SPI4, \
.bus_name = "spi4", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_rx.Instance = DMA2_Stream0, \
.dma_rx.channel = DMA_CHANNEL_4, \
.dma_rx.dma_irq = DMA2_Stream0_IRQn, \
.dma_tx.Instance = DMA2_Stream1, \
.dma_tx.channel = DMA_CHANNEL_4, \
.dma_tx.dma_irq = DMA2_Stream1_IRQn, \
#ifndef SPI4_BUS_CONFIG
#define SPI4_BUS_CONFIG \
{ \
.Instance = SPI4, \
.bus_name = "spi4", \
}
#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler
#endif
#endif
/* SPI4_BUS_CONFIG */
#endif
/* BSP_USING_SPI4 */
#ifdef BSP_SPI4_TX_USING_DMA
#ifndef SPI4_TX_DMA_CONFIG
#define SPI4_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI4_TX_DMA_RCC, \
.Instance = SPI4_TX_DMA_INSTANCE, \
.channel = SPI4_TX_DMA_CHANNEL, \
.dma_irq = SPI4_TX_DMA_IRQ, \
}
#endif
/* SPI4_TX_DMA_CONFIG */
#endif
/* BSP_SPI4_TX_USING_DMA */
#ifdef BSP_SPI4_RX_USING_DMA
#ifndef SPI4_RX_DMA_CONFIG
#define SPI4_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI4_RX_DMA_RCC, \
.Instance = SPI4_RX_DMA_INSTANCE, \
.channel = SPI4_RX_DMA_CHANNEL, \
.dma_irq = SPI4_RX_DMA_IRQ, \
}
#endif
/* SPI4_RX_DMA_CONFIG */
#endif
/* BSP_SPI4_RX_USING_DMA */
#ifdef BSP_USING_SPI5
#define SPI5_BUS_CONFIG \
{ \
.Instance = SPI5, \
.bus_name = "spi5", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_rx.Instance = DMA2_Stream3, \
.dma_rx.channel = DMA_CHANNEL_2, \
.dma_rx.dma_irq = DMA2_Stream3_IRQn, \
.dma_tx.Instance = DMA2_Stream4, \
.dma_tx.channel = DMA_CHANNEL_2, \
.dma_tx.dma_irq = DMA2_Stream4_IRQn, \
#ifndef SPI5_BUS_CONFIG
#define SPI5_BUS_CONFIG \
{ \
.Instance = SPI5, \
.bus_name = "spi5", \
}
#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
#endif
#ifdef BSP_USING_SPI6
#define SPI5_BUS_CONFIG \
{ \
.Instance = SPI6, \
.bus_name = "spi6", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_rx.Instance = DMA2_Stream6, \
.dma_rx.channel = DMA_CHANNEL_1, \
.dma_rx.dma_irq = DMA2_Stream6_IRQn, \
.dma_tx.Instance = DMA2_Stream5, \
.dma_tx.channel = DMA_CHANNEL_1, \
.dma_tx.dma_irq = DMA2_Stream5_IRQn, \
#endif
/* SPI5_BUS_CONFIG */
#endif
/* BSP_USING_SPI5 */
#ifdef BSP_SPI5_TX_USING_DMA
#ifndef SPI5_TX_DMA_CONFIG
#define SPI5_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI5_TX_DMA_RCC, \
.Instance = SPI5_TX_DMA_INSTANCE, \
.channel = SPI5_TX_DMA_CHANNEL, \
.dma_irq = SPI5_TX_DMA_IRQ, \
}
#define SPI6_DMA_RX_IRQHandler DMA2_Stream6_IRQHandler
#define SPI6_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler
#endif
#endif
/* SPI5_TX_DMA_CONFIG */
#endif
/* BSP_SPI5_TX_USING_DMA */
#ifdef BSP_SPI5_RX_USING_DMA
#ifndef SPI5_RX_DMA_CONFIG
#define SPI5_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI5_RX_DMA_RCC, \
.Instance = SPI5_RX_DMA_INSTANCE, \
.channel = SPI5_RX_DMA_CHANNEL, \
.dma_irq = SPI5_RX_DMA_IRQ, \
}
#endif
/* SPI5_RX_DMA_CONFIG */
#endif
/* BSP_SPI5_RX_USING_DMA */
#endif
/*__SPI_CONFIG_H__ */
bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h
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@@ -5,7 +5,8 @@
*
* Change Logs:
* Date Author Notes
* 2018-10-30 SummerGift change to new framework
* 2018-10-30 SummerGift first version
* 2019-01-05 zylx modify dma support
*/
#ifndef __UART_CONFIG_H__
...
...
@@ -14,78 +15,118 @@
#include <rtthread.h>
#if defined(BSP_USING_UART1)
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
.dma.stream_channel.Instance = DMA2_Stream5, \
.dma.stream_channel.channel = DMA_CHANNEL_4, \
.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_irq = DMA2_Stream5_IRQn, \
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
}
#endif
/* UART1_CONFIG */
#endif
/* BSP_USING_UART1 */
#define USART1_RX_DMA_ISR DMA2_Stream5_IRQHandler
#endif
#if defined(BSP_UART1_RX_USING_DMA)
#ifndef UART1_DMA_CONFIG
#define UART1_DMA_CONFIG \
{ \
.Instance = USART1_RX_DMA_INSTANCE, \
.channel = USART1_RX_DMA_CHANNEL, \
.dma_rcc = USART1_RX_DMA_RCC, \
.dma_irq = USART1_RX_DMA_IRQ, \
}
#endif
/* UART1_DMA_CONFIG */
#endif
/* BSP_UART1_RX_USING_DMA */
#if defined(BSP_USING_UART2)
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
.dma.stream_channel.Instance = DMA1_Stream5, \
.dma.stream_channel.channel = DMA_CHANNEL_4, \
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_irq = DMA1_Stream5_IRQn, \
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
}
#endif
/* UART2_CONFIG */
#endif
/* BSP_USING_UART2 */
#define USART2_RX_DMA_ISR DMA1_Stream5_IRQHandler
#endif
#if defined(BSP_UART2_RX_USING_DMA)
#ifndef UART2_DMA_CONFIG
#define UART2_DMA_CONFIG \
{ \
.Instance = USART2_RX_DMA_INSTANCE, \
.channel = USART2_RX_DMA_CHANNEL, \
.dma_rcc = USART2_RX_DMA_RCC, \
.dma_irq = USART2_RX_DMA_IRQ, \
}
#endif
/* UART2_DMA_CONFIG */
#endif
/* BSP_UART2_RX_USING_DMA */
#if defined(BSP_USING_UART3)
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = USART3, \
.irq_type = USART3_IRQn, \
.dma.stream_channel.Instance = DMA1_Stream1, \
.dma.stream_channel.channel = DMA_CHANNEL_4, \
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_irq = DMA1_Stream1_IRQn, \
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = USART3, \
.irq_type = USART3_IRQn, \
}
#endif
/* UART3_CONFIG */
#endif
/* BSP_USING_UART3 */
#define USART3_RX_DMA_ISR DMA1_Stream1_IRQHandler
#endif
#if defined(BSP_UART3_RX_USING_DMA)
#ifndef UART3_DMA_CONFIG
#define UART3_DMA_CONFIG \
{ \
.Instance = USART3_RX_DMA_INSTANCE, \
.channel = USART3_RX_DMA_CHANNEL, \
.dma_rcc = USART3_RX_DMA_RCC, \
.dma_irq = USART3_RX_DMA_IRQ, \
}
#endif
/* UART3_DMA_CONFIG */
#endif
/* BSP_UART3_RX_USING_DMA */
#if defined(BSP_USING_UART4)
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = UART4, \
.irq_type = UART4_IRQn, \
.dma.stream_channel.Instance = DMA1_Stream2, \
.dma.stream_channel.channel = DMA_CHANNEL_4, \
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_irq = DMA1_Stream2_IRQn, \
#ifndef UART4_CONFIG
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = UART4, \
.irq_type = UART4_IRQn, \
}
#endif
/* UART4_CONFIG */
#endif
/* BSP_USING_UART4 */
#define USART4_RX_DMA_ISR DMA1_Stream2_IRQHandler
#endif
#if defined(BSP_UART4_RX_USING_DMA)
#ifndef UART4_DMA_CONFIG
#define UART4_DMA_CONFIG \
{ \
.Instance = USART4_RX_DMA_INSTANCE, \
.channel = USART4_RX_DMA_CHANNEL, \
.dma_rcc = USART4_RX_DMA_RCC, \
.dma_irq = USART4_RX_DMA_IRQ, \
}
#endif
/* UART4_DMA_CONFIG */
#endif
/* BSP_UART4_RX_USING_DMA */
#if defined(BSP_USING_UART5)
#define UART5_CONFIG \
{ \
.name = "uart5", \
.Instance = UART5, \
.irq_type = UART5_IRQn, \
.dma.stream_channel.Instance = DMA1_Stream0, \
.dma.stream_channel.channel = DMA_CHANNEL_4, \
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_irq = DMA1_Stream0_IRQn, \
#ifndef UART5_CONFIG
#define UART5_CONFIG \
{ \
.name = "uart5", \
.Instance = UART5, \
.irq_type = UART5_IRQn, \
}
#endif
/* UART5_CONFIG */
#endif
/* BSP_USING_UART5 */
#define USART5_RX_DMA_ISR DMA1_Stream0_IRQHandler
#endif
#if defined(BSP_UART5_RX_USING_DMA)
#ifndef UART5_DMA_CONFIG
#define UART5_DMA_CONFIG \
{ \
.Instance = USART5_RX_DMA_INSTANCE, \
.channel = USART5_RX_DMA_CHANNEL, \
.dma_rcc = USART5_RX_DMA_RCC, \
.dma_irq = USART5_RX_DMA_IRQ, \
}
#endif
/* UART5_DMA_CONFIG */
#endif
/* BSP_UART5_RX_USING_DMA */
#endif
bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h
浏览文件 @
574492a2
...
...
@@ -29,8 +29,8 @@
#ifndef QSPI_DMA_CONFIG
#define QSPI_DMA_CONFIG \
{ \
.Instance =
DMA1_Channel5,
\
.Init.Request =
DMA_REQUEST_5,
\
.Instance =
QSPI_DMA_INSTANCE,
\
.Init.Request =
QSPI_DMA_CHANNEL,
\
.Init.Direction = DMA_PERIPH_TO_MEMORY, \
.Init.PeriphInc = DMA_PINC_DISABLE, \
.Init.MemInc = DMA_MINC_ENABLE, \
...
...
@@ -42,10 +42,7 @@
#endif
/* QSPI_DMA_CONFIG */
#endif
/* BSP_QSPI_USING_DMA */
#define QSPI_DMA_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE()
#define QSPI_IRQn QUADSPI_IRQn
#define QSPI_DMA_IRQn DMA1_Channel5_IRQn
#define QSPI_IRQHandler QUADSPI_IRQHandler
#define QSPI_DMA_IRQHandler DMA1_Channel5_IRQHandler
#endif
/* __QSPI_CONFIG_H__ */
bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h
浏览文件 @
574492a2
...
...
@@ -14,22 +14,38 @@
#include <rtthread.h>
#ifdef BSP_USING_SPI1
#define SPI1_BUS_CONFIG \
{ \
.Instance = SPI1, \
.bus_name = "spi1", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_rx.Instance = DMA1_Channel2, \
.dma_rx.request = DMA_REQUEST_1, \
.dma_rx.dma_irq = DMA1_Channel2_IRQn, \
.dma_tx.Instance = DMA1_Channel3, \
.dma_tx.request = DMA_REQUEST_1, \
.dma_tx.dma_irq = DMA1_Channel3_IRQn, \
#ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \
{ \
.Instance = SPI1, \
.bus_name = "spi1", \
}
#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler
#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler
#endif
#endif
/* SPI1_BUS_CONFIG */
#endif
/* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI1_TX_DMA_RCC, \
.Instance = SPI1_TX_DMA_INSTANCE, \
.request = SPI1_TX_DMA_REQUEST, \
.dma_irq = SPI1_TX_DMA_IRQ, \
}
#endif
/* SPI1_TX_DMA_CONFIG */
#endif
/* BSP_SPI1_TX_USING_DMA */
#ifdef BSP_SPI1_RX_USING_DMA
#ifndef SPI1_RX_DMA_CONFIG
#define SPI1_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI1_RX_DMA_RCC, \
.Instance = SPI1_RX_DMA_INSTANCE, \
.request = SPI1_RX_DMA_REQUEST, \
.dma_irq = SPI1_RX_DMA_IRQ, \
}
#endif
/* SPI1_RX_DMA_CONFIG */
#endif
/* BSP_SPI1_RX_USING_DMA */
#ifdef BSP_USING_SPI2
#define SPI2_BUS_CONFIG \
...
...
@@ -45,8 +61,7 @@
.dma_tx.request = DMA_REQUEST_1, \
.dma_tx.dma_irq = DMA1_Channel5_IRQn, \
}
#define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler
#define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler
#endif
#ifdef BSP_USING_SPI3
...
...
@@ -63,8 +78,7 @@
.dma_tx.request = DMA_REQUEST_3, \
.dma_tx.dma_irq = DMA2_Channel2_IRQn, \
}
#define SPI3_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler
#define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler
#endif
#endif
/*__SPI_CONFIG_H__ */
bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h
浏览文件 @
574492a2
...
...
@@ -14,35 +14,49 @@
#include <rtthread.h>
#if defined(BSP_USING_UART1)
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
.dma.channel_request.Instance = DMA2_Channel7, \
.dma.channel_request.request = DMA_REQUEST_2, \
.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_irq = DMA2_Channel7_IRQn, \
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
}
#define USART1_RX_DMA_ISR DMA2_Channel7_IRQHandler
#endif
#endif
/* UART1_CONFIG */
#endif
/* BSP_USING_UART1 */
#if defined(BSP_UART1_RX_USING_DMA)
#ifndef UART1_DMA_CONFIG
#define UART1_DMA_CONFIG \
{ \
.Instance = USART1_RX_DMA_INSTANCE, \
.request = USART1_RX_DMA_REQUEST, \
.dma_rcc = USART1_RX_DMA_RCC, \
.dma_irq = USART1_RX_DMA_IRQ, \
}
#endif
/* UART1_DMA_CONFIG */
#endif
/* BSP_UART1_RX_USING_DMA */
#if defined(BSP_USING_UART2)
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
.dma.channel_request.Instance = DMA1_Channel6, \
.dma.channel_request.request = DMA_REQUEST_2, \
.dma_rcc = RCC_AHB1SMENR_DMA1SMEN, \
.dma_irq = DMA1_Channel6_IRQn, \
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
}
#define USART2_RX_DMA_ISR DMA1_Channel6_IRQHandler
#endif
#endif
/* UART2_CONFIG */
#endif
/* BSP_USING_UART2 */
#if defined(BSP_UART2_RX_USING_DMA)
#ifndef UART2_DMA_CONFIG
#define UART2_DMA_CONFIG \
{ \
.Instance = USART2_RX_DMA_INSTANCE, \
.request = USART2_RX_DMA_REQUEST, \
.dma_rcc = USART2_RX_DMA_RCC, \
.dma_irq = USART2_RX_DMA_IRQ, \
}
#endif
/* UART2_DMA_CONFIG */
#endif
/* BSP_UART2_RX_USING_DMA */
#endif
bsp/stm32/libraries/HAL_Drivers/drv_config.h
浏览文件 @
574492a2
...
...
@@ -15,12 +15,14 @@
#include <rtthread.h>
#if defined(SOC_SERIES_STM32F0)
#include "f0/dma_config.h"
#include "f0/uart_config.h"
#include "f0/spi_config.h"
#include "f0/tim_config.h"
#include "f0/pwm_config.h"
#include "f0/adc_config.h"
#elif defined(SOC_SERIES_STM32F1)
#include "f1/dma_config.h"
#include "f1/uart_config.h"
#include "f1/spi_config.h"
#include "f1/adc_config.h"
...
...
@@ -28,6 +30,7 @@
#include "f1/sdio_config.h"
#include "f1/pwm_config.h"
#elif defined(SOC_SERIES_STM32F4)
#include "f4/dma_config.h"
#include "f4/uart_config.h"
#include "f4/spi_config.h"
#include "f4/adc_config.h"
...
...
@@ -35,6 +38,7 @@
#include "f4/sdio_config.h"
#include "f4/pwm_config.h"
#elif defined(SOC_SERIES_STM32F7)
#include "f7/dma_config.h"
#include "f7/uart_config.h"
#include "f7/spi_config.h"
#include "f7/qspi_config.h"
...
...
@@ -43,6 +47,7 @@
#include "f7/sdio_config.h"
#include "f7/pwm_config.h"
#elif defined(SOC_SERIES_STM32L4)
#include "l4/dma_config.h"
#include "l4/uart_config.h"
#include "l4/spi_config.h"
#include "l4/qspi_config.h"
...
...
bsp/stm32/libraries/HAL_Drivers/drv_dma.h
浏览文件 @
574492a2
...
...
@@ -5,7 +5,7 @@
*
* Change Logs:
* Date Author Notes
* 2018-11-10
SummerGift change to new framework
* 2018-11-10
SummerGift first version
*/
#ifndef __DRV_DMA_H_
...
...
@@ -16,7 +16,7 @@
#include <rthw.h>
#include <drv_common.h>
#if defined(SOC_SERIES_STM32F0) || (SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
#if defined(SOC_SERIES_STM32F0) ||
defined
(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
#define DMA_INSTANCE_TYPE DMA_Stream_TypeDef
...
...
@@ -36,5 +36,4 @@ struct dma_config {
#endif
};
#endif
/*__DRV_DMA_H_ */
bsp/stm32/libraries/HAL_Drivers/drv_qspi.c
浏览文件 @
574492a2
...
...
@@ -92,11 +92,19 @@ static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configu
/* QSPI interrupts must be enabled when using the HAL_QSPI_Receive_DMA */
HAL_NVIC_SetPriority
(
QSPI_IRQn
,
0
,
0
);
HAL_NVIC_EnableIRQ
(
QSPI_IRQn
);
HAL_NVIC_SetPriority
(
QSPI_DMA_IRQ
n
,
0
,
0
);
HAL_NVIC_EnableIRQ
(
QSPI_DMA_IRQ
n
);
HAL_NVIC_SetPriority
(
QSPI_DMA_IRQ
,
0
,
0
);
HAL_NVIC_EnableIRQ
(
QSPI_DMA_IRQ
);
/* init QSPI DMA */
QSPI_DMA_CLK_ENABLE
;
if
(
QSPI_DMA_RCC
==
RCC_AHB1ENR_DMA1EN
)
{
__HAL_RCC_DMA1_CLK_ENABLE
();
}
else
{
__HAL_RCC_DMA2_CLK_ENABLE
();
}
HAL_DMA_DeInit
(
qspi_bus
->
QSPI_Handler
.
hdma
);
DMA_HandleTypeDef
hdma_quadspi_config
=
QSPI_DMA_CONFIG
;
qspi_bus
->
hdma_quadspi
=
hdma_quadspi_config
;
...
...
bsp/stm32/libraries/HAL_Drivers/drv_spi.c
浏览文件 @
574492a2
此差异已折叠。
点击以展开。
bsp/stm32/libraries/HAL_Drivers/drv_spi.h
浏览文件 @
574492a2
...
...
@@ -5,7 +5,7 @@
*
* Change Logs:
* Date Author Notes
* 2018-11-5 SummerGift
change to new framework
* 2018-11-5 SummerGift
first version
*/
#ifndef __DRV_SPI_H_
...
...
@@ -29,7 +29,7 @@ struct stm32_spi_config
{
SPI_TypeDef
*
Instance
;
char
*
bus_name
;
struct
dma_config
dma_rx
,
dma_tx
;
struct
dma_config
*
dma_rx
,
*
dma_tx
;
};
struct
stm32_spi_device
...
...
@@ -39,21 +39,23 @@ struct stm32_spi_device
char
*
device_name
;
};
#define SPI_USING_RX_DMA_FLAG (1<<0)
#define SPI_USING_TX_DMA_FLAG (1<<1)
/* stm32 spi dirver class */
struct
stm32_spi
{
SPI_HandleTypeDef
handle
;
const
struct
stm32_spi_config
*
config
;
struct
stm32_spi_config
*
config
;
struct
rt_spi_configuration
*
cfg
;
#ifdef BSP_SPI_USING_DMA
struct
{
DMA_HandleTypeDef
handle_rx
;
DMA_HandleTypeDef
handle_tx
;
}
dma
;
#endif
rt_uint8_t
spi_dma_flag
;
struct
rt_spi_bus
spi_bus
;
};
...
...
bsp/stm32/libraries/HAL_Drivers/drv_usart.c
浏览文件 @
574492a2
...
...
@@ -46,7 +46,7 @@ enum
#endif
};
static
const
struct
stm32_uart_config
uart_config
[]
=
static
struct
stm32_uart_config
uart_config
[]
=
{
#ifdef BSP_USING_UART1
UART1_CONFIG
,
...
...
@@ -65,7 +65,7 @@ static const struct stm32_uart_config uart_config[] =
#endif
};
static
struct
stm32_uart
uart_obj
[
sizeof
(
uart_config
)
/
sizeof
(
uart_config
[
0
])];
static
struct
stm32_uart
uart_obj
[
sizeof
(
uart_config
)
/
sizeof
(
uart_config
[
0
])]
=
{
0
}
;
static
rt_err_t
stm32_configure
(
struct
rt_serial_device
*
serial
,
struct
serial_configure
*
cfg
)
{
...
...
@@ -239,7 +239,7 @@ static void uart_isr(struct rt_serial_device *serial)
UART_INSTANCE_CLEAR_FUNCTION
(
&
(
uart
->
handle
),
UART_FLAG_RXNE
);
}
#ifdef RT_SERIAL_USING_DMA
else
if
((
__HAL_UART_GET_FLAG
(
&
(
uart
->
handle
),
UART_FLAG_IDLE
)
!=
RESET
)
&&
else
if
((
uart
->
uart_dma_flag
)
&&
(
__HAL_UART_GET_FLAG
(
&
(
uart
->
handle
),
UART_FLAG_IDLE
)
!=
RESET
)
&&
(
__HAL_UART_GET_IT_SOURCE
(
&
(
uart
->
handle
),
UART_IT_IDLE
)
!=
RESET
))
{
level
=
rt_hw_interrupt_disable
();
...
...
@@ -309,8 +309,8 @@ void USART1_IRQHandler(void)
/* leave interrupt */
rt_interrupt_leave
();
}
#if defined(RT_SERIAL_USING_DMA) && defined(
USART1_RX_DMA_ISR
)
void
USART1_
RX_DMA_ISR
(
void
)
#if defined(RT_SERIAL_USING_DMA) && defined(
BSP_UART1_RX_USING_DMA
)
void
USART1_
DMA_RX_IRQHandler
(
void
)
{
/* enter interrupt */
rt_interrupt_enter
();
...
...
@@ -320,7 +320,7 @@ void USART1_RX_DMA_ISR(void)
/* leave interrupt */
rt_interrupt_leave
();
}
#endif
/* defined(RT_SERIAL_USING_DMA) && defined(
USART1_RX_DMA_ISR
) */
#endif
/* defined(RT_SERIAL_USING_DMA) && defined(
BSP_UART1_RX_USING_DMA
) */
#endif
/* BSP_USING_UART1 */
#if defined(BSP_USING_UART2)
...
...
@@ -334,8 +334,8 @@ void USART2_IRQHandler(void)
/* leave interrupt */
rt_interrupt_leave
();
}
#if defined(RT_SERIAL_USING_DMA) && defined(
USART2_RX_DMA_ISR
)
void
USART2_
RX_DMA_ISR
(
void
)
#if defined(RT_SERIAL_USING_DMA) && defined(
BSP_UART2_RX_USING_DMA
)
void
USART2_
DMA_RX_IRQHandler
(
void
)
{
/* enter interrupt */
rt_interrupt_enter
();
...
...
@@ -345,7 +345,7 @@ void USART2_RX_DMA_ISR(void)
/* leave interrupt */
rt_interrupt_leave
();
}
#endif
/* defined(RT_SERIAL_USING_DMA) && defined(
USART2_RX_DMA_ISR
) */
#endif
/* defined(RT_SERIAL_USING_DMA) && defined(
BSP_UART2_RX_USING_DMA
) */
#endif
/* BSP_USING_UART2 */
#if defined(BSP_USING_UART3)
...
...
@@ -359,8 +359,8 @@ void USART3_IRQHandler(void)
/* leave interrupt */
rt_interrupt_leave
();
}
#if defined(RT_SERIAL_USING_DMA) && defined(
USART3_RX_DMA_ISR
)
void
USART3_
RX_DMA_ISR
(
void
)
#if defined(RT_SERIAL_USING_DMA) && defined(
BSP_UART3_RX_USING_DMA
)
void
USART3_
DMA_RX_IRQHandler
(
void
)
{
/* enter interrupt */
rt_interrupt_enter
();
...
...
@@ -370,7 +370,7 @@ void USART3_RX_DMA_ISR(void)
/* leave interrupt */
rt_interrupt_leave
();
}
#endif
/* defined(BSP_UART_USING_DMA_RX) && defined(
USART3_RX_DMA_ISR
) */
#endif
/* defined(BSP_UART_USING_DMA_RX) && defined(
BSP_UART3_RX_USING_DMA
) */
#endif
/* BSP_USING_UART3*/
#if defined(BSP_USING_UART4)
...
...
@@ -384,8 +384,8 @@ void UART4_IRQHandler(void)
/* leave interrupt */
rt_interrupt_leave
();
}
#if defined(RT_SERIAL_USING_DMA) && defined(
USART1_RX_DMA_ISR
)
void
USART4_
RX_DMA_ISR
(
void
)
#if defined(RT_SERIAL_USING_DMA) && defined(
BSP_UART4_RX_USING_DMA
)
void
USART4_
DMA_RX_IRQHandler
(
void
)
{
/* enter interrupt */
rt_interrupt_enter
();
...
...
@@ -395,7 +395,7 @@ void USART4_RX_DMA_ISR(void)
/* leave interrupt */
rt_interrupt_leave
();
}
#endif
/* defined(BSP_UART_USING_DMA_RX) && defined(
USART4_RX_DMA_ISR
) */
#endif
/* defined(BSP_UART_USING_DMA_RX) && defined(
BSP_UART4_RX_USING_DMA
) */
#endif
/* BSP_USING_UART4*/
#if defined(BSP_USING_UART5)
...
...
@@ -409,8 +409,8 @@ void UART5_IRQHandler(void)
/* leave interrupt */
rt_interrupt_leave
();
}
#if defined(RT_SERIAL_USING_DMA) && defined(
USART5_RX_DMA_ISR
)
void
USART5_
RX_DMA_ISR
(
void
)
#if defined(RT_SERIAL_USING_DMA) && defined(
BSP_UART5_RX_USING_DMA
)
void
USART5_
DMA_RX_IRQHandler
(
void
)
{
/* enter interrupt */
rt_interrupt_enter
();
...
...
@@ -420,7 +420,7 @@ void USART5_RX_DMA_ISR(void)
/* leave interrupt */
rt_interrupt_leave
();
}
#endif
/* defined(RT_SERIAL_USING_DMA) && defined(
USART5_RX_DMA_ISR
) */
#endif
/* defined(RT_SERIAL_USING_DMA) && defined(
BSP_UART5_RX_USING_DMA
) */
#endif
/* BSP_USING_UART5*/
#ifdef RT_SERIAL_USING_DMA
...
...
@@ -437,12 +437,12 @@ static void stm32_dma_config(struct rt_serial_device *serial)
rt_uint32_t
tmpreg
=
0x00U
;
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT
(
RCC
->
AHBENR
,
uart
->
config
->
dma_rcc
);
tmpreg
=
READ_BIT
(
RCC
->
AHBENR
,
uart
->
config
->
dma_rcc
);
SET_BIT
(
RCC
->
AHBENR
,
uart
->
config
->
dma_r
x
->
dma_r
cc
);
tmpreg
=
READ_BIT
(
RCC
->
AHBENR
,
uart
->
config
->
dma_r
x
->
dma_r
cc
);
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT
(
RCC
->
AHB1ENR
,
uart
->
config
->
dma_rcc
);
tmpreg
=
READ_BIT
(
RCC
->
AHB1ENR
,
uart
->
config
->
dma_rcc
);
SET_BIT
(
RCC
->
AHB1ENR
,
uart
->
config
->
dma_r
x
->
dma_r
cc
);
tmpreg
=
READ_BIT
(
RCC
->
AHB1ENR
,
uart
->
config
->
dma_r
x
->
dma_r
cc
);
#endif
UNUSED
(
tmpreg
);
/* To avoid compiler warnings */
}
...
...
@@ -450,13 +450,13 @@ static void stm32_dma_config(struct rt_serial_device *serial)
__HAL_LINKDMA
(
&
(
uart
->
handle
),
hdmarx
,
uart
->
dma
.
handle
);
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0)
uart
->
dma
.
handle
.
Instance
=
uart
->
config
->
dma
.
Instance
;
uart
->
dma
.
handle
.
Instance
=
uart
->
config
->
dma
_rx
->
Instance
;
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
uart
->
dma
.
handle
.
Instance
=
uart
->
config
->
dma
.
Instance
;
uart
->
dma
.
handle
.
Init
.
Channel
=
uart
->
config
->
dma
.
stream_channel
.
channel
;
uart
->
dma
.
handle
.
Instance
=
uart
->
config
->
dma
_rx
->
Instance
;
uart
->
dma
.
handle
.
Init
.
Channel
=
uart
->
config
->
dma
_rx
->
channel
;
#elif defined(SOC_SERIES_STM32L4)
uart
->
dma
.
handle
.
Instance
=
uart
->
config
->
dma
.
Instance
;
uart
->
dma
.
handle
.
Init
.
Request
=
uart
->
config
->
dma
.
channel_request
.
request
;
uart
->
dma
.
handle
.
Instance
=
uart
->
config
->
dma
_rx
->
Instance
;
uart
->
dma
.
handle
.
Init
.
Request
=
uart
->
config
->
dma
_rx
->
request
;
#endif
uart
->
dma
.
handle
.
Init
.
Direction
=
DMA_PERIPH_TO_MEMORY
;
uart
->
dma
.
handle
.
Init
.
PeriphInc
=
DMA_PINC_DISABLE
;
...
...
@@ -491,8 +491,8 @@ static void stm32_dma_config(struct rt_serial_device *serial)
__HAL_UART_ENABLE_IT
(
&
(
uart
->
handle
),
UART_IT_IDLE
);
/* enable rx irq */
HAL_NVIC_SetPriority
(
uart
->
config
->
dma_irq
,
0
,
0
);
HAL_NVIC_EnableIRQ
(
uart
->
config
->
dma_irq
);
HAL_NVIC_SetPriority
(
uart
->
config
->
dma_
rx
->
dma_
irq
,
0
,
0
);
HAL_NVIC_EnableIRQ
(
uart
->
config
->
dma_
rx
->
dma_
irq
);
HAL_NVIC_SetPriority
(
uart
->
config
->
irq_type
,
1
,
0
);
HAL_NVIC_EnableIRQ
(
uart
->
config
->
irq_type
);
...
...
@@ -547,31 +547,59 @@ void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
}
#endif
/* RT_SERIAL_USING_DMA */
static
void
stm32_uart_get_dma_config
(
void
)
{
#ifdef BSP_UART1_RX_USING_DMA
uart_obj
[
UART1_INDEX
].
uart_dma_flag
=
1
;
static
struct
dma_config
uart1_dma_rx
=
UART1_DMA_CONFIG
;
uart_config
[
UART1_INDEX
].
dma_rx
=
&
uart1_dma_rx
;
#endif
#ifdef BSP_UART2_RX_USING_DMA
uart_obj
[
UART2_INDEX
].
uart_dma_flag
=
1
;
static
struct
dma_config
uart2_dma_rx
=
UART2_DMA_CONFIG
;
uart_config
[
UART2_INDEX
].
dma_rx
=
&
uart2_dma_rx
;
#endif
#ifdef BSP_UART3_RX_USING_DMA
uart_obj
[
UART3_INDEX
].
uart_dma_flag
=
1
;
static
struct
dma_config
uart3_dma_rx
=
UART3_DMA_CONFIG
;
uart_config
[
UART3_INDEX
].
dma_rx
=
&
uart3_dma_rx
;
#endif
#ifdef BSP_UART4_RX_USING_DMA
uart_obj
[
UART4_INDEX
].
uart_dma_flag
=
1
;
static
struct
dma_config
uart4_dma_rx
=
UART4_DMA_CONFIG
;
uart_config
[
UART4_INDEX
].
dma_rx
=
&
uart4_dma_rx
;
#endif
#ifdef BSP_UART5_RX_USING_DMA
uart_obj
[
UART5_INDEX
].
uart_dma_flag
=
1
;
static
struct
dma_config
uart5_dma_rx
=
UART5_DMA_CONFIG
;
uart_config
[
UART5_INDEX
].
dma_rx
=
&
uart5_dma_rx
;
#endif
}
int
rt_hw_usart_init
(
void
)
{
rt_size_t
obj_num
=
sizeof
(
uart_obj
)
/
sizeof
(
struct
stm32_uart
);
struct
serial_configure
config
=
RT_SERIAL_CONFIG_DEFAULT
;
rt_err_t
result
=
0
;
stm32_uart_get_dma_config
();
for
(
int
i
=
0
;
i
<
obj_num
;
i
++
)
{
uart_obj
[
i
].
config
=
&
uart_config
[
i
];
uart_obj
[
i
].
serial
.
ops
=
&
stm32_uart_ops
;
uart_obj
[
i
].
serial
.
config
=
config
;
/* Determines whether a serial instance supports DMA */
if
(
uart_obj
[
i
].
config
->
dma
.
Instance
!=
DMA_NOT_AVAILABLE
)
#if defined(RT_SERIAL_USING_DMA)
if
(
uart_obj
[
i
].
uart_dma_flag
)
{
/* register UART device */
result
=
rt_hw_serial_register
(
&
uart_obj
[
i
].
serial
,
uart_obj
[
i
].
config
->
name
,
RT_DEVICE_FLAG_RDWR
|
RT_DEVICE_FLAG_INT_RX
#if defined(RT_SERIAL_USING_DMA)
|
RT_DEVICE_FLAG_DMA_RX
#endif
RT_DEVICE_FLAG_RDWR
|
RT_DEVICE_FLAG_INT_RX
|
RT_DEVICE_FLAG_DMA_RX
,
&
uart_obj
[
i
]);
}
else
#endif
{
/* register UART device */
result
=
rt_hw_serial_register
(
&
uart_obj
[
i
].
serial
,
uart_obj
[
i
].
config
->
name
,
...
...
bsp/stm32/libraries/HAL_Drivers/drv_usart.h
浏览文件 @
574492a2
...
...
@@ -15,10 +15,10 @@
#include "rtdevice.h"
#include <rthw.h>
#include <drv_common.h>
#include "drv_dma.h"
int
rt_hw_usart_init
(
void
);
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
...
...
@@ -37,45 +37,15 @@ struct stm32_uart_config
const
char
*
name
;
USART_TypeDef
*
Instance
;
IRQn_Type
irq_type
;
union
{
DMA_INSTANCE_TYPE
*
Instance
;
#if defined(SOC_SERIES_STM32F1)
/* the DMA config has channel only, such as on STM32F1xx */
struct
{
DMA_INSTANCE_TYPE
*
Instance
;
}
channel
;
#endif
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
/* the DMA config has stream and channel, such as on STM32F4xx */
struct
{
DMA_INSTANCE_TYPE
*
Instance
;
rt_uint32_t
channel
;
}
stream_channel
;
#endif
#if defined(SOC_SERIES_STM32L4)
/* the DMA config has channel and request, such as on STM32L4xx */
struct
{
DMA_INSTANCE_TYPE
*
Instance
;
rt_uint32_t
request
;
}
channel_request
;
#endif
}
dma
;
rt_uint32_t
dma_rcc
;
IRQn_Type
dma_irq
;
struct
dma_config
*
dma_rx
;
};
/* stm32 uart dirver class */
struct
stm32_uart
{
UART_HandleTypeDef
handle
;
const
struct
stm32_uart_config
*
config
;
struct
stm32_uart_config
*
config
;
#ifdef RT_SERIAL_USING_DMA
struct
{
...
...
@@ -83,7 +53,7 @@ struct stm32_uart
rt_size_t
last_index
;
}
dma
;
#endif
rt_uint8_t
uart_dma_flag
;
struct
rt_serial_device
serial
;
};
...
...
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