imports.yml

---
group:
  name: 'liuqidev'
  description: ''
  projects:
  - name: '8-bits-RISC-CPU-Verilog'
    description: ''
    mirrorRelease: false
    topic: ''
  - name: '8-bits-risc-cpu-verilog'
    description: ''
    mirrorRelease: false
    topic: ''