Merge branch 'xiangshan' into 'master'

OpenXiangShan

See merge request !351

projects/OpenXiangShan/imports.yml

+---
+group:
+  name: 'OpenXiangShan'
+  description: 'Open-source high-performance RISC-V processor'
+  projects:
+  - name: 'openxiangshan.github.io'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+  - name: 'NEMU'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+  - name: 'XiangShan'
+    description: 'Open-source high-performance RISC-V processor'
+    mirrorRelease: false
+    topic: 'chisel3,risc-v,microarchitecture'
+  - name: 'nexus-am'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+  - name: 'env-scripts'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+  - name: 'riscv-linux'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+  - name: 'riscv-pk'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+  - name: 'riscv-rootfs'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+  - name: 'chisel-playground'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+  - name: 'DRAMsim3'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+  - name: 'block-inclusivecache-sifive'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+  - name: 'ns-bbl'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+  - name: 'opensbi'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+  - name: 'u-boot'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+  - name: 'riscv-isa-sim'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+  - name: 'berkeley-hardfloat'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+  - name: 'coremark-pro'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+  - name: 'rust-xs-evaluation'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+  - name: 'rust-xs-test'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+  - name: 'timingScripts'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+  - name: 'rocket-chip'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+  - name: 'riscv-torture'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+  - name: 'riscv-compliance'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+  
\ No newline at end of file