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提交 fe24ae7c 编写于 作者: W Watson Zeng
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[bsp][synopsys] add basic new embarc bsp support 

* the initial support of synopsys designware ARC processor
  using embARC_BSP, all synopsys ARC-based boards are
  supported:
  -ARC Software Development Platform
  -ARC EM Starter Kit
  -ARC EM Software Development Platform
  -ARC HS Development Kit
  -ARC IoT Development Kit

* The embARC BSP is a new generation embARC software development
  package.  ​It is designed to be the inter-layer between hardware and
  operating system. ​ BSP could hide the difference of hardware/boards,
  provide a unified interface to upper-layer.

* the initial support of synopsys MWDT toolchain.
  The DesignWare® ARC® MetaWare Development Toolkit builds upon
  a 25-year legacy of industry-leading compiler and debugger products.
  It is a complete solution that contains all the components needed to
  support the development, debugging and tuning of embedded applications
  for the DesignWare ARC processors.

* for detailed board information, pls go embarc.org.
Signed-off-by: NWatson Zeng <zhiwei@synopsys.com>
上级 54814c42
展开全部 隐藏空白更改
内联 并排
Showing with 1618 addition and 14625 deletion
bsp/synopsys/emsk_em9d/.config → bsp/synopsys/boards/.config
浏览文件 @ fe24ae7c
......@@ -6,7 +6,8 @@
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
CONFIG_RT_NAME_MAX=16
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
......@@ -18,11 +19,14 @@ CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
CONFIG_IDLE_THREAD_STACK_SIZE=1024
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
CONFIG_RT_DEBUG_INIT_CONFIG=y
CONFIG_RT_DEBUG_INIT=1
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
......@@ -47,10 +51,11 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_MEMHEAP is not set
CONFIG_RT_USING_MEMHEAP=y
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
......@@ -63,7 +68,8 @@ CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x40000
CONFIG_RT_VER_NUM=0x40002
CONFIG_RT_USING_CPU_FFS=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
......@@ -99,47 +105,39 @@ CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=2
CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_UFFS is not set
# CONFIG_RT_USING_DFS_JFFS2 is not set
# CONFIG_RT_USING_DFS_NFS is not set
# CONFIG_RT_USING_DFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
CONFIG_RT_PIPE_BUFSZ=1024
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=4096
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=8
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_SERIAL_USING_DMA=y
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ=1024
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_PIN is not set
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_MTD is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
#
# Using WiFi
#
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
......@@ -151,10 +149,9 @@ CONFIG_RT_USING_PIN=y
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_LIBC is not set
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_POSIX is not set
# CONFIG_RT_USING_MODULE is not set
# CONFIG_RT_LIBC_USING_TIME is not set
#
# Network
......@@ -163,88 +160,22 @@ CONFIG_RT_USING_LIBC=y
#
# Socket abstraction layer
#
CONFIG_RT_USING_SAL=y
# CONFIG_RT_USING_SAL is not set
#
# protocol stack implement
# Network interface device
#
CONFIG_SAL_USING_LWIP=y
CONFIG_SAL_USING_AT=y
# CONFIG_SAL_USING_POSIX is not set
CONFIG_SAL_SOCKETS_NUM=16
CONFIG_SAL_PROTO_FAMILIES_NUM=4
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP141 is not set
CONFIG_RT_USING_LWIP202=y
# CONFIG_RT_USING_LWIP210 is not set
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_IGMP=y
CONFIG_RT_LWIP_ICMP=y
# CONFIG_RT_LWIP_SNMP is not set
CONFIG_RT_LWIP_DNS=y
CONFIG_RT_LWIP_DHCP=y
CONFIG_IP_SOF_BROADCAST=1
CONFIG_IP_SOF_BROADCAST_RECV=1
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.1.30"
CONFIG_RT_LWIP_GWADDR="192.168.1.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
# CONFIG_RT_LWIP_RAW is not set
# CONFIG_RT_LWIP_PPP is not set
CONFIG_RT_MEMP_NUM_NETCONN=8
CONFIG_RT_LWIP_PBUF_NUM=16
CONFIG_RT_LWIP_RAW_PCB_NUM=4
CONFIG_RT_LWIP_UDP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_SEG_NUM=40
CONFIG_RT_LWIP_TCP_SND_BUF=8196
CONFIG_RT_LWIP_TCP_WND=8196
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_SO_REUSE=1
CONFIG_LWIP_SO_RCVTIMEO=1
CONFIG_LWIP_SO_SNDTIMEO=1
CONFIG_LWIP_SO_RCVBUF=1
# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_RT_LWIP_STATS is not set
# CONFIG_RT_LWIP_DEBUG is not set
#
# Modbus master and slave stack
#
# CONFIG_RT_USING_MODBUS is not set
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
CONFIG_RT_USING_AT=y
# CONFIG_AT_DEBUG is not set
# CONFIG_AT_USING_SERVER is not set
CONFIG_AT_USING_CLIENT=y
CONFIG_AT_CLIENT_NUM_MAX=1
CONFIG_AT_USING_SOCKET=y
CONFIG_AT_USING_CLI=y
# CONFIG_AT_PRINT_RAW_CMD is not set
CONFIG_AT_SW_VERSION_NUM=0x10200
# CONFIG_LWIP_USING_DHCPD is not set
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
......@@ -254,7 +185,6 @@ CONFIG_AT_SW_VERSION_NUM=0x10200
#
# Utilities
#
# CONFIG_RT_USING_LOGTRACE is not set
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
......@@ -268,10 +198,14 @@ CONFIG_AT_SW_VERSION_NUM=0x10200
#
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
......@@ -289,25 +223,14 @@ CONFIG_AT_SW_VERSION_NUM=0x10200
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
CONFIG_PKG_USING_AT_DEVICE=y
CONFIG_PKG_AT_DEVICE_PATH="/packages/iot/at_device"
CONFIG_PKG_AT_INIT_BY_THREAD=y
# CONFIG_AT_DEVICE_M26 is not set
# CONFIG_AT_DEVICE_EC20 is not set
CONFIG_AT_DEVICE_ESP8266=y
# CONFIG_AT_DEVICE_NOT_SELECTED is not set
CONFIG_AT_DEVICE_SOCKETS_NUM=5
CONFIG_AT_DEVICE_NAME="uart0"
CONFIG_AT_DEVICE_RECV_BUFF_LEN=512
CONFIG_AT_DEVICE_WIFI_SSID="embarc"
CONFIG_AT_DEVICE_WIFI_PASSWORD="qazwsxedc"
CONFIG_PKG_USING_AT_DEVICE_LATEST_VERSION=y
# CONFIG_PKG_USING_AT_DEVICE_V100 is not set
# CONFIG_PKG_USING_AT_DEVICE_V110 is not set
CONFIG_PKG_AT_DEVICE_VER="latest"
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
#
# IoT Cloud
......@@ -316,6 +239,25 @@ CONFIG_PKG_AT_DEVICE_VER="latest"
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
#
# security packages
......@@ -336,6 +278,9 @@ CONFIG_PKG_AT_DEVICE_VER="latest"
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
#
# tools packages
......@@ -344,6 +289,16 @@ CONFIG_PKG_AT_DEVICE_VER="latest"
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
#
# system packages
......@@ -357,17 +312,50 @@ CONFIG_PKG_AT_DEVICE_VER="latest"
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
CONFIG_PKG_USING_EMBARC_BSP=y
CONFIG_PKG_EMBARC_BSP_PATH="/packages/system/embARC_bsp"
CONFIG_PKG_USING_EMBARC_BSP_UPSTREAM_VERSION=y
# CONFIG_PKG_USING_EMBARC_BSP_MASTER_VERSION is not set
CONFIG_PKG_EMBARC_BSP_VER="upstream"
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_STM32F4_HAL is not set
# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_AHT10 is not set
# CONFIG_PKG_USING_AP3216C is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
#
# miscellaneous packages
......@@ -378,13 +366,15 @@ CONFIG_PKG_AT_DEVICE_VER="latest"
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
#
# sample package
#
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
#
# samples: kernel and components samples
......@@ -393,11 +383,15 @@ CONFIG_PKG_AT_DEVICE_VER="latest"
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
CONFIG_SOC_EMSK=y
CONFIG_EMSK_USING_UART0=y
CONFIG_EMSK_USING_UART1=y
bsp/synopsys/emsk_em9d/Kconfig → bsp/synopsys/boards/Kconfig
浏览文件 @ fe24ae7c
......@@ -23,6 +23,7 @@ config SOC_EMSK
select ARCH_ARC_EM
select RT_USING_COMPONENTS_INIT
# select RT_USING_USER_MAIN
select RT_USING_CPU_FFS
default y
source "$BSP_DIR/drivers/Kconfig"
bsp/synopsys/boards/README.md 0 → 100644
浏览文件 @ fe24ae7c
# Synopsys ARC Boards support with embARC_BSP
## embARC_BSP
The embARC Board support Package (BSP) is a software distributions aimed at facilitating
the development and evaluation of embedded systems based on ARCv2 processors, which is
designed to provide a minimal board support package for ARC users by defining
consistent and simple software interfaces to the processors and onboard devices.
The embARC BSP is a new generation embARC software development package. ​
It is designed to be the inter-layer between hardware and operating system. ​
BSP could hide the difference of hardware/boards, provide a unified interface to upper-layer. ​
In the scenarios that no OS is required, embARC BSP can also standalone and work in baremetal.
embARC_BSP features:
* Support MetaWare & GNU toolchains​
* Support all development boards and tcf​
* Support various build systems and compiling environments,
such as ARC MetaWare & GNU IDE, makefile​
* Designware and Subsystem drivers, including UART and GPIO, I2C, SPI, etc. ​
* No middleware, no OS​
* Easy to port to different platform / OS​
* One example (UART, GPIO, timer)​
* Code coverage reach 100% in test. ​
* MISRA-C compliance​
* C & C++ support, assembly support
## Supported Boards
* [ARC Software Development Platform](https://www.synopsys.com/dw/ipdir.php?ds=arc-software-development-platform)
* [ARC EM Starter Kit](https://www.synopsys.com/dw/ipdir.php?ds=arc_em_starter_kit)
* [ARC EM Software Development Platform](https://www.synopsys.com/dw/ipdir.php?ds=arc-em-software-development-platform)
* [ARC HS Development Kit](https://www.synopsys.com/dw/ipdir.php?ds=arc-hs-development-kit)
* [ARC IoT Development Kit](https://www.synopsys.com/dw/ipdir.php?ds=arc_iot_development_kit)
## Software Requirement
### embarc_bsp
There are two ways to get embarc_bsp:
#### use RT-Thread ENV tool:
embARC_BSP has been configured as package module, you can just run the command `pkgs --update` in <RTT_ROOT>/bsp/synopsys/boards
folder using ENV tool.
#### without RT-Thread ENV tool:
We can get it from github: [embarc_bsp](https://github.com/foss-for-synopsys-dwc-arc-processors)
The default path for embarc_bsp is <RTT_ROOT>/bsp/synopsys/boards/packages/embARC_bsp-upstream,
when you use other path, please set the environment variable `EMBARC_BSP_ROOT`.
### Toolchain
Now both GNU and MetaWare Toolchain are supported, set the System environment variable RTT_CC select the toolchain.
GNU:
set RTT_CC=gnu
MetaWare:
set RTT_CC=mw
#### GNU
The ARC GNU Toolchain offers all of the benefits of open source tools, including complete source code and a large install base. The ARC GNU IDE Installer consists of Eclipse IDE with [ARC GNU plugin for Eclipse](https://github.com/foss-for-synopsys-dwc-arc-processors/arc_gnu_eclipse/releases), [ARC GNU prebuilt toolchain](https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases) and [OpenOCD for ARC](https://github.com/foss-for-synopsys-dwc-arc-processors/openocd>)
Here, the ARC GNU toolchain is installed to `c:\arc_gnu`. If not, please change the path configuration in rtconfig.py.
When you use GNU Toolchain, you need to install [Zadig](http://zadig.akeo.ie) to replace the default FTDI driver with WinUSB driver. See [How to Use OpenOCD on Windows](https://github.com/foss-for-synopsys-dwc-arc-processors/arc_gnu_eclipse/wiki/How-to-Use-OpenOCD-on-Windows>) for more information.
#### MetaWare
The [DesignWare ARC MetaWare Development Toolkit](https://www.synopsys.com/dw/ipdir.php?ds=sw_metaware) builds on a long legacy of industry-leading compiler and debugger products for embedded applications. It is a complete solution that contains all the components needed to support the development, debugging, and tuning of embedded applications for the DesignWare® ARC® processors.
Here, the ARC MetaWare toolchain is installed to `C:\ARC\MetaWare`. If not, please change the path configuration in rtconfig.py.
## Build & Debug
### Build embarc_lib
please run the following cmds to build embarc_lib
cd <rt-thread-root>/bsp/synopsys/boards
scons --embarc_build
### Build
please run the following cmds to build
cd <rt-thread-root>/bsp/synopsys/boards
scons
### Debug
After compile, please use the following cmds to debug
scons --gdb #use gdb debugger
scons --mdb #use mdb debugger
### How to choose different boards
There are some parameters we can use in scons, for example:
scons --BOARD=emsk --BD_VER=23 --CUR_CORE=arcem9d --TOOLCHAIN=mw --OLEVEL=O2
* BOARD: choose the board, we can set: `emsk, iotdk, emsdp, hsdk, axs`.
* BD_VER: choose the board version, some boards have different versions, for example,
we can set: `10, 22, 23` for emsk board.
* CUR_CORE: choose the arc cores, some boards have different cores, for example,
we can set: `arcem7d, arcem9d, arcem11d` for emsk board.
* TOOLCHAIN: choose the toolchain to build embarc_lib, we can set: `mw, gnu`.
* OLEVEL: choose the build optimize level, we can set: `O0, O2, Os`.
For more information, you can run the command `scons -h`.
## Maintainer
- [vonhust](https://github.com/vonhust)
- [IRISZZW](https://github.com/IRISZZW)
bsp/synopsys/emsk_em9d/SConscript → bsp/synopsys/boards/SConscript
浏览文件 @ fe24ae7c
......@@ -8,7 +8,6 @@ list = os.listdir(cwd)
ASFLAGS = ' -I' + cwd
objs = objs + SConscript(os.path.join(cwd, '../embarc/SConscript'))
for d in list:
path = os.path.join(cwd, d)
......
bsp/synopsys/boards/SConstruct 0 → 100644
浏览文件 @ fe24ae7c
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
if os.getenv('EMBARC_BSP_ROOT'):
EMBARC_BSP_ROOT = os.getenv('EMBARC_BSP_ROOT')
else:
EMBARC_BSP_ROOT = RTT_ROOT + '/bsp/synopsys/boards/packages/embARC_bsp-upstream'
if not os.path.isdir(EMBARC_BSP_ROOT):
print('Cannot found embarc_bsp root directory, please check EMBARC_BSP_ROOT')
print(EMBARC_BSP_ROOT)
exit(-1)
SUPPORTED_BOARD_DIR = EMBARC_BSP_ROOT + '/board'
SUPPORTED_BOARD = [d for d in os.listdir(SUPPORTED_BOARD_DIR) if os.path.isdir(os.path.join(SUPPORTED_BOARD_DIR,d))]
print 'supported BOARD = ' + str(SUPPORTED_BOARD)
AddOption('--BOARD',
dest = 'BOARD',
type='string',
nargs=1,
action = 'store',
default = 'emsk',
help = 'select board')
AddOption('--BD_VER',
dest = 'BD_VER',
type='string',
nargs=1,
action = 'store',
default = '23',
help = 'select bd_ver')
AddOption('--CUR_CORE',
dest = 'CUR_CORE',
type='string',
nargs=1,
action = 'store',
default = 'arcem9d',
help = 'select cur_core')
AddOption('--TOOLCHAIN',
dest = 'TOOLCHAIN',
type='string',
nargs=1,
action = 'store',
default = 'gnu',
help = 'select toolchain')
AddOption('--OLEVEL',
dest = 'OLEVEL',
type='string',
nargs=1,
action = 'store',
default = 'O2',
help = 'select optimize level')
AddOption('--mdb',
dest = 'mdb',
action = 'store_true',
default = False,
help = 'use mdb to debug the elf')
AddOption('--gdb',
dest = 'gdb',
action = 'store_true',
default = False,
help = 'use gdb to debug the elf')
AddOption('--embarc_build',
dest = 'embarc_build',
action = 'store_true',
default = False,
help = 'to generate embarc_lib')
AddOption('--embarc_clean',
dest = 'embarc_clean',
action = 'store_true',
default = False,
help = 'to clean embarc_lib')
if GetOption('BOARD'):
board = GetOption('BOARD')
if board not in SUPPORTED_BOARD:
print 'board %s not supported, available boards:' % board
print SUPPORTED_BOARD
exit(0)
else:
BOARD = board
print 'get BOARD = [%s]' % board
if BOARD == 'emsdp':
SUPPORTED_BD_VER = ['rev2']
else:
SUPPORTED_BD_VER_DIR = SUPPORTED_BOARD_DIR + '/' + BOARD + '/configs'
SUPPORTED_BD_VER = [d for d in os.listdir(SUPPORTED_BD_VER_DIR) if os.path.isdir(os.path.join(SUPPORTED_BD_VER_DIR,d))]
print 'supported BD_VER = ' + str(SUPPORTED_BD_VER)
if GetOption('BD_VER'):
bd_ver = GetOption('BD_VER')
if bd_ver not in SUPPORTED_BD_VER:
print 'bd_ver %s not supported, available bd_ver:' % bd_ver
print SUPPORTED_BD_VER
exit(0)
else:
BD_VER = bd_ver
print 'get BD_VER = [%s]' % BD_VER
if BOARD == 'emsdp':
SUPPORTED_CORE_DIR = SUPPORTED_BOARD_DIR + '/' + BOARD + '/rev2/configs'
SUPPORTED_CORE = [d for d in os.listdir(SUPPORTED_CORE_DIR) if os.path.isdir(os.path.join(SUPPORTED_CORE_DIR,d))]
else:
SUPPORTED_CORE_DIR = SUPPORTED_BD_VER_DIR + '/' + BD_VER + '/tcf'
SUPPORTED_CORE = [os.path.splitext(d)[0] for d in os.listdir(SUPPORTED_CORE_DIR)]
print 'supported CUR_CORE = ' + str(SUPPORTED_CORE)
if GetOption('CUR_CORE'):
cur_core = GetOption('CUR_CORE')
if cur_core not in SUPPORTED_CORE:
print 'cur_core %s not supported, available cur_core:' % cur_core
print SUPPORTED_CORE
exit(0)
else:
CUR_CORE = cur_core
print 'get CUR_CORE = [%s]' % CUR_CORE
SUPPORTED_TOOLCHAIN = ['mw', 'gnu']
print 'supported TOOLCHAIN = ' + str(SUPPORTED_TOOLCHAIN)
if GetOption('TOOLCHAIN'):
toolchain = GetOption('TOOLCHAIN')
if toolchain not in SUPPORTED_TOOLCHAIN:
print 'toolchain %s not supported, available toolchain:' % toolchain
print SUPPORTED_TOOLCHAIN
exit(0)
else:
TOOLCHAIN = toolchain
print 'get TOOLCHAIN = [%s]' % TOOLCHAIN
SUPPORTED_OLEVEL = ['O0', 'O2', 'Os']
print 'supported OLEVEL = ' + str(SUPPORTED_OLEVEL)
if GetOption('OLEVEL'):
olevel = GetOption('OLEVEL')
if olevel not in SUPPORTED_OLEVEL:
print 'olevel %s not supported, available olevel:' % toolchain
print SUPPORTED_OLEVEL
exit(0)
else:
OLEVEL = olevel
print 'get OLEVEL = [%s]' % olevel
EMBARC_LIB_PATH = EMBARC_BSP_ROOT + '/obj_%s_%s/%s_%s'%(BOARD, BD_VER, TOOLCHAIN, CUR_CORE)
# print 'EMBARC_LIB_PATH = %s'%EMBARC_LIB_PATH
TARGET = 'rtthread_snps_embarc.elf'
# print 'TARGET = %s'%TARGET
# ip_ph_dir = EMBARC_BSP_ROOT + '/device/peripheral'
# ip_ph_path = [os.path.join(ip_ph_dir,d) for d in os.listdir(ip_ph_dir) if os.path.isdir(os.path.join(ip_ph_dir,d))]
if BOARD == 'emsdp':
board_inc_path = [SUPPORTED_CORE_DIR, SUPPORTED_CORE_DIR + '/%s/include'%CUR_CORE]
else:
board_inc_path = [EMBARC_BSP_ROOT + '/board/%s/configs/%s'%(BOARD, BD_VER)]
# print 'board_inc_path = %s' % board_inc_path
# print 'ip_dw_path = %s' % ip_dw_path
# print 'ip_ss_path = %s' % ip_ss_path
# print 'ip_ph_path = %s' % ip_ph_path
EMBARC_CPPPATH = [ EMBARC_BSP_ROOT,
EMBARC_BSP_ROOT + '/include',
EMBARC_BSP_ROOT + '/board',
EMBARC_LIB_PATH + '/embARC_generated',
] + board_inc_path
#print "EMBARC_CPPPATH: %s"%EMBARC_CPPPATH
if TOOLCHAIN == 'mw':
EXEC_PATH = 'C:/ARC/MetaWare/arc/bin'
MAKE = 'gmake'
PREFIX = ''
CC = 'ccac'
CXX = 'ccac'
AS = 'ccac'
AR = 'arac'
LINK = 'ccac'
TARGET_EXT = 'elf'
SIZE = 'sizeac'
OBJDUMP = 'elfdumpac'
OBJCPY = 'elf2bin'
DBG = 'mdb'
OPT_ARG_FILE = ' @' + EMBARC_LIB_PATH + '/embARC_generated/ccac.arg '
MDB_ARG_FILE = ' @' + EMBARC_LIB_PATH + '/embARC_generated/mdb.arg '
COMMON_COMPILE_OPT = ' -Hnoccm -Hnosdata -Wincompatible-pointer-types -Hnocopyr -Hpurge -fdata-sections -g -%s '%(OLEVEL)
COMMON_DEFINES = ' -DBOARD_%s -D__MW__ -DEMBARC_TCF_GENERATED ' % BOARD.upper()
CFLAGS = OPT_ARG_FILE + COMMON_COMPILE_OPT + COMMON_DEFINES + ' -Hnocplus '
CXXFLAGS = OPT_ARG_FILE + COMMON_COMPILE_OPT + COMMON_DEFINES
AFLAGS = ' -c' + OPT_ARG_FILE + COMMON_COMPILE_OPT + COMMON_DEFINES + ' -Hasmcpp -I%s -I%s/embARC_generated -I%s/include '%(EMBARC_BSP_ROOT, EMBARC_LIB_PATH, EMBARC_BSP_ROOT)
LINKER_SCRIPT_FILE = RTT_ROOT + '/bsp/synopsys/boards/linker_template_mw.ld'
LINK_SCRIPT = EMBARC_LIB_PATH + '/linker_mw.ldf'
LFLAGS = ' -Hhostlink ' + OPT_ARG_FILE + ' -Hnocopyr -Hnosdata -Hnocrt -Hldopt=-Coutput=rtthread_snps_embarc.map -Hldopt=-Csections -Hldopt=-Ccrossfunc -Hldopt=-Csize -zstdout %s' % LINK_SCRIPT
elif TOOLCHAIN == 'gnu':
EXEC_PATH = 'C:/arc_gnu/bin'
MAKE = 'make'
PREFIX = 'arc-elf32-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DBG = PREFIX + 'gdb'
OPT_ARG_FILE = ' @' + EMBARC_LIB_PATH + '/embARC_generated/gcc.arg '
MDB_ARG_FILE = ' @' + EMBARC_LIB_PATH + '/embARC_generated/mdb.arg '
COMMON_COMPILE_OPT = ' -ffunction-sections -fdata-sections -mno-sdata -g -%s '%(OLEVEL)
COMMON_DEFINES = ' -DBOARD_%s -D__GNU__ -DEMBARC_TCF_GENERATED ' % BOARD.upper()
CFLAGS = OPT_ARG_FILE + COMMON_COMPILE_OPT + COMMON_DEFINES + ' -std=gnu99 '
CXXFLAGS = OPT_ARG_FILE + COMMON_COMPILE_OPT + COMMON_DEFINES
AFLAGS = ' -c ' + OPT_ARG_FILE + COMMON_COMPILE_OPT + COMMON_DEFINES + ' -x assembler-with-cpp -I%s -I%s/embARC_generated -I%s/include '%(EMBARC_BSP_ROOT, EMBARC_LIB_PATH, EMBARC_BSP_ROOT)
LINKER_SCRIPT_FILE = RTT_ROOT + '/bsp/synopsys/boards/linker_template_gnu.ld'
LINK_SCRIPT = EMBARC_LIB_PATH + '/linker_gnu.ldf'
LFLAGS = ' --specs=nsim.specs ' + OPT_ARG_FILE + ' -mno-sdata -nostartfiles -Wl,--gc-sections,-Map=rtthread_snps_embarc.map,-cref,-u,system_vectors -T %s ' % LINK_SCRIPT
OPENOCD_SCRIPT_ROOT = EXEC_PATH + '/../share/openocd/scripts'
OPENOCD_CFG_FILE = OPENOCD_SCRIPT_ROOT + '/board/snps_em_sk_v2.2.cfg'
OPENOCD_OPTIONS = '-s %s -f %s' % (OPENOCD_SCRIPT_ROOT, OPENOCD_CFG_FILE)
DBG_HW_FLAGS = ''' -ex "target remote | openocd --pipe %s" -ex "load" ''' % OPENOCD_OPTIONS
else :
print 'TOOLCHAIN %s is not supported, available toolchain:' % TOOLCHAIN
print SUPPORTED_TOOLCHAIN
exit(-1)
env = Environment(ENV = os.environ, tools = ['mingw'],
AS = AS, ASFLAGS = AFLAGS,
CC = CC, CCFLAGS = CFLAGS,
AR = AR, ARFLAGS = '-rc',
LINK = LINK, LINKFLAGS = LFLAGS,
LIBS = ['embarc'], LIBPATH = EMBARC_LIB_PATH,
CPPPATH = EMBARC_CPPPATH
)
env.PrependENVPath('PATH', EXEC_PATH)
Export('RTT_ROOT')
Export('rtconfig')
embarc_cd_cmd = ' cd %s '%EMBARC_BSP_ROOT
embarc_make_cmd = ' %s -f options/options.mk BOARD=%s BD_VER=%s CUR_CORE=%s TOOLCHAIN=%s V=1 OLEVEL=%s LINKER_SCRIPT_FILE=%s embarc_lib '%(MAKE,BOARD, BD_VER, CUR_CORE, TOOLCHAIN, OLEVEL, LINKER_SCRIPT_FILE)
embarc_clean_cmd = ' %s -f options/options.mk distclean '%MAKE
if GetOption('embarc_build'):
print 'os.system: ' + embarc_cd_cmd + ' && ' + embarc_make_cmd
os.system(embarc_cd_cmd + ' && ' + embarc_make_cmd)
exit(0)
if GetOption('embarc_clean'):
os.system(embarc_cd_cmd + ' && ' + embarc_clean_cmd)
exit(0)
if GetOption('gdb'):
if os.path.isfile(TARGET):
os.system(DBG + DBG_HW_FLAGS + TARGET)
else:
print TARGET + 'not exist, please build first!!'
exit(0)
if GetOption('mdb'):
if os.path.isfile(TARGET):
startup_path = EMBARC_BSP_ROOT + '/arc/startup'
if BOARD == 'nsim':
os.system('mdb -source_path=%s -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim -off=binary_stdin -off=binary_stdout \
-on=load_at_paddr -on=reset_upon_restart -off=flush_pipe -off=cr_for_more -OKN %s '%(startup_path, MDB_ARG_FILE) + rtconfig.TARGET)
else:
os.system('mdb -source_path=%s -nooptions -nogoifmain -toggle=include_local_symbols=1 -hard -digilent '%startup_path + rtconfig.TARGET)
else:
print TARGET + 'not exist, please build first!!'
exit(0)
# os.system(embarc_cd_cmd + ' && ' + embarc_make_cmd)
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT)
# if the linker script changed, relink the target
Depends(TARGET, LINK_SCRIPT)
# make a building
DoBuilding(TARGET, objs)
bsp/synopsys/emsk_em9d/applications/startup.c → bsp/synopsys/boards/applications/startup.c
浏览文件 @ fe24ae7c
......@@ -7,7 +7,12 @@
#include <rthw.h>
#include <rtthread.h>
#include <board.h>
#include <rt_board.h>
#ifdef RT_USING_HEAP
#define rt_system_heap_size 1024*64
static rt_uint32_t rt_system_heap[rt_system_heap_size/4] = {0};
#endif
extern int rt_application_init(void);
......@@ -33,7 +38,7 @@ void rtthread_startup(void)
/* initialize memory system */
#ifdef RT_USING_HEAP
rt_system_heap_init(HEAP_BEGIN, HEAP_END);
rt_system_heap_init((void *)rt_system_heap, (void *)(rt_system_heap+rt_system_heap_size));
#endif
/* initialize scheduler system */
......@@ -58,7 +63,7 @@ void rtthread_startup(void)
return ;
}
int board_main(void)
int main(void)
{
/* disable interrupt first */
rt_hw_interrupt_disable();
......
bsp/synopsys/emsk_em9d/drivers/board.c → bsp/synopsys/boards/drivers/rt_board.c
浏览文件 @ fe24ae7c
......@@ -10,57 +10,11 @@
#include <rtdevice.h>
#include <drivers/serial.h>
#include "board.h"
#include "inc/arc/arc_timer.h"
#include "inc/arc/arc_exception.h"
#include "rt_board.h"
#include "arc/arc_timer.h"
#include "arc/arc_exception.h"
#include "inc/embARC_error.h"
#include "mux.h"
#include "dw_uart_obj.h"
static void rt_hw_timer_isr(int vector, void *param)
{
arc_timer_int_clear(BOARD_OS_TIMER_ID);
rt_tick_increase();
}
static void emsk_mux_init(void)
{
MUX_REG *mux_regs;
mux_regs = (MUX_REG *)(PERIPHERAL_BASE|REL_REGBASE_PINMUX);
mux_init(mux_regs);
/**
* + Please refer to corresponding EMSK User Guide for detailed information
* -> Appendix: A Hardware Functional Description
* -> Pmods Configuration summary
* + Set up pin-multiplexer of all PMOD connections
* - PM1 J1: Upper row as UART 0, lower row as SPI Slave
* - PM2 J2: IIC 0 and run/halt signals
* - PM3 J3: GPIO Port A and Port C
* - PM4 J4: IIC 1 and Port D
* - PM5 J5: Upper row as SPI Master, lower row as Port A
* - PM6 J6: Upper row as SPI Master, lower row as Port A
*/
set_pmod_mux(mux_regs, PM1_UR_UART_0 | PM1_LR_SPI_S \
| PM2_I2C_HRI \
| PM3_GPIO_AC \
| PM4_I2C_GPIO_D \
| PM5_UR_SPI_M1 | PM5_LR_GPIO_A \
| PM6_UR_SPI_M0 | PM6_LR_GPIO_A );
/**
* PM1 upper row as UART
* UM4:RXD, UM3:TXD
* UM2:RTS_N, UM1:CTS_N
*/
set_uart_map(mux_regs, 0xe4);
}
static struct rt_serial_device _emsk_uart0; //abstracted serial for RTT
static struct rt_serial_device _emsk_uart1;
#include "embARC_error.h"
static rt_err_t _configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
......@@ -158,12 +112,7 @@ static int _getc(struct rt_serial_device *serial)
}
static void _emsk_uart0_isr(void *ptr)
{
rt_hw_serial_isr((struct rt_serial_device*)&_emsk_uart0, RT_SERIAL_EVENT_RX_IND);
}
static const struct rt_uart_ops _emsk_uart0_ops =
static const struct rt_uart_ops uart_ops =
{
_configure,
_control,
......@@ -171,18 +120,31 @@ static const struct rt_uart_ops _emsk_uart0_ops =
_getc,
};
static void _emsk_uart1_isr(void *ptr)
static struct rt_serial_device uart0;
static struct rt_serial_device uart1;
static struct rt_serial_device uart2;
static struct rt_serial_device uart3;
static void uart0_isr(void *ptr)
{
rt_hw_serial_isr((struct rt_serial_device*)&_emsk_uart1, RT_SERIAL_EVENT_RX_IND);
rt_hw_serial_isr((struct rt_serial_device*)&uart0, RT_SERIAL_EVENT_RX_IND);
}
static const struct rt_uart_ops _emsk_uart1_ops =
static void uart1_isr(void *ptr)
{
_configure,
_control,
_putc,
_getc,
};
rt_hw_serial_isr((struct rt_serial_device*)&uart1, RT_SERIAL_EVENT_RX_IND);
}
static void uart2_isr(void *ptr)
{
rt_hw_serial_isr((struct rt_serial_device*)&uart2, RT_SERIAL_EVENT_RX_IND);
}
static void uart3_isr(void *ptr)
{
rt_hw_serial_isr((struct rt_serial_device*)&uart3, RT_SERIAL_EVENT_RX_IND);
}
int rt_hw_uart_init(void)
{
......@@ -198,86 +160,165 @@ int rt_hw_uart_init(void)
config.invert = NRZ_NORMAL;
config.bufsz = RT_SERIAL_RB_BUFSZ;
_emsk_uart0.ops = &_emsk_uart0_ops;
_emsk_uart0.config = config;
uart0.ops = &uart_ops;
uart0.config = config;
_emsk_uart1.ops = &_emsk_uart1_ops;
_emsk_uart1.config = config;
uart1.ops = &uart_ops;
uart1.config = config;
/* open UART1 for USB-UART interface */
uart = uart_get_dev(DW_UART_1_ID);
/* default format: 8bits, no parity, 1 stop bits */
ret = uart->uart_open(config.baud_rate);
uart2.ops = &uart_ops;
uart2.config = config;
if (ret != E_OPNED && ret != E_OK) {
return RT_ERROR;
uart3.ops = &uart_ops;
uart3.config = config;
/* uart0 init */
uart = uart_get_dev(0);
if (uart != NULL) {
/* default format: 8bits, no parity, 1 stop bits */
ret = uart->uart_open(config.baud_rate);
if (ret != E_OPNED && ret != E_OK) {
return RT_ERROR;
}
/* enable rx int */
uart->uart_control(UART_CMD_SET_RXINT, (void *)0);
/* use customized int isr */
uart->uart_control(UART_CMD_SET_RXCB, uart0_isr);
uart->uart_control(UART_CMD_SET_RXINT_BUF, NULL);
rt_hw_serial_register(&uart0, "uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
(void *)0);
}
/* uart1 init */
uart = uart_get_dev(1);
if (uart != NULL) {
/* default format: 8bits, no parity, 1 stop bits */
ret = uart->uart_open(config.baud_rate);
if (ret != E_OPNED && ret != E_OK) {
return RT_ERROR;
}
/* enable rx int */
uart->uart_control(UART_CMD_SET_RXINT, (void *)0);
/* use customized int isr */
uart->uart_control(UART_CMD_SET_RXCB, uart1_isr);
uart->uart_control(UART_CMD_SET_RXINT_BUF, NULL);
rt_hw_serial_register(&uart1, "uart1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
(void *)1);
}
/* enable rx int */
uart->uart_control(UART_CMD_SET_RXINT, (void *)1);
/* use customized int isr */
uart->uart_control(UART_CMD_SET_RXCB, _emsk_uart1_isr);
uart->uart_control(UART_CMD_SET_RXINT_BUF, NULL);
/* uart2 init */
uart = uart_get_dev(2);
if (uart != NULL) {
/* default format: 8bits, no parity, 1 stop bits */
ret = uart->uart_open(config.baud_rate);
rt_hw_serial_register(&_emsk_uart1, "uart1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
(void *)DW_UART_1_ID);
if (ret != E_OPNED && ret != E_OK) {
return RT_ERROR;
}
/* open UART0 in PMOD A*/
uart = uart_get_dev(DW_UART_0_ID);
/* default format: 8bits, no parity, 1 stop bits */
ret = uart->uart_open(config.baud_rate);
/* enable rx int */
uart->uart_control(UART_CMD_SET_RXINT, (void *)0);
/* use customized int isr */
uart->uart_control(UART_CMD_SET_RXCB, uart2_isr);
uart->uart_control(UART_CMD_SET_RXINT_BUF, NULL);
if (ret != E_OPNED && ret != E_OK) {
return RT_ERROR;
rt_hw_serial_register(&uart2, "uart2",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
(void *)2);
}
/* enable rx int */
uart->uart_control(UART_CMD_SET_RXINT, (void *)1);
/* use customized int isr */
uart->uart_control(UART_CMD_SET_RXCB, _emsk_uart0_isr);
uart->uart_control(UART_CMD_SET_RXINT_BUF, NULL);
/* uart3 init */
uart = uart_get_dev(3);
rt_hw_serial_register(&_emsk_uart0, "uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
(void *)DW_UART_0_ID);
if (uart != NULL) {
/* default format: 8bits, no parity, 1 stop bits */
ret = uart->uart_open(config.baud_rate);
if (ret != E_OPNED && ret != E_OK) {
return RT_ERROR;
}
/* enable rx int */
uart->uart_control(UART_CMD_SET_RXINT, (void *)0);
/* use customized int isr */
uart->uart_control(UART_CMD_SET_RXCB, uart3_isr);
uart->uart_control(UART_CMD_SET_RXINT_BUF, NULL);
rt_hw_serial_register(&uart3, "uart3",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
(void *)3);
}
return RT_EOK;
}
#if defined BOARD_EMSK
#define CONSOLE_UART "uart1"
struct rt_serial_device *console_uart = &uart1;
#elif defined BOARD_IOTDK || defined BOARD_EMSDP || defined BOARD_NSIM
#define CONSOLE_UART "uart0"
struct rt_serial_device *console_uart = &uart0;
#elif defined BOARD_AXS
#define CONSOLE_UART "uart2"
struct rt_serial_device *console_uart = &uart2;
#elif defined BOARD_HSDK
#define CONSOLE_UART "uart3"
struct rt_serial_device *console_uart = &uart3;
#else
#error "no supported board selected!"
#endif
void rt_hw_console_output(const char *str)
{
while(*str != '\0')
{
if (*str == '\n') {
_putc(&_emsk_uart1,'\r');
_putc(console_uart,'\r');
}
_putc(&_emsk_uart1,*str);
_putc(console_uart,*str);
str++;
}
}
void rt_hw_board_init()
{
rt_hw_uart_init();
rt_components_board_init();
rt_console_set_device(CONSOLE_UART);
}
static void rt_hw_timer_isr(int vector, void *param)
{
timer_int_clear(BOARD_OS_TIMER_ID);
rt_tick_increase();
}
int rt_hw_timer_init(void)
{
unsigned int cyc = BOARD_CPU_CLOCK / RT_TICK_PER_SECOND;
int_disable(BOARD_OS_TIMER_INTNO); /* disable os timer interrupt */
arc_timer_stop(BOARD_OS_TIMER_ID);
arc_timer_start(BOARD_OS_TIMER_ID, TIMER_CTRL_IE | TIMER_CTRL_NH, cyc);
timer_stop(BOARD_OS_TIMER_ID);
timer_start(BOARD_OS_TIMER_ID, TIMER_CTRL_IE | TIMER_CTRL_NH, cyc);
int_handler_install(BOARD_OS_TIMER_INTNO, (INT_HANDLER)rt_hw_timer_isr);
int_handler_install(BOARD_OS_TIMER_INTNO, (INT_HANDLER_T)rt_hw_timer_isr);
int_pri_set(BOARD_OS_TIMER_INTNO, INT_PRI_MIN + 1); /* currently, firq(INT_PRI_MIN) not supported*/
int_enable(BOARD_OS_TIMER_INTNO);
return 0;
}
INIT_BOARD_EXPORT(rt_hw_timer_init);
void rt_hw_board_init()
{
emsk_mux_init();
rt_hw_uart_init();
rt_components_board_init();
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
}
bsp/synopsys/emsk_em9d/drivers/board.h → bsp/synopsys/boards/drivers/rt_board.h
浏览文件 @ fe24ae7c
......@@ -4,22 +4,10 @@
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#ifndef __RT_BOARD_H__
#define __RT_BOARD_H__
#include "emsk_hardware.h"
#define BOARD_OS_TIMER_ID 0
#define BOARD_OS_TIMER_INTNO 16
#define BOARD_CPU_CLOCK 25000000
#if defined(__GNUC__)
extern int __start_heap;
#define HEAP_BEGIN ((void*)&__start_heap)
#endif
extern int __end_heap;
#define HEAP_END (void*)(&__end_heap)
#include "board.h"
void rt_hw_board_init();
......
bsp/synopsys/boards/linker_template_gnu.ld 0 → 100644
浏览文件 @ fe24ae7c
#define __ASSEMBLY__
#include <target_mem_config.h>
MEMORY
{
#if (REGION_ICCM_SIZE != 0)
REGION_ICCM : ORIGIN = REGION_ICCM_START, LENGTH = REGION_ICCM_SIZE
#endif
#if (REGION_DCCM_SIZE !=0)
REGION_DCCM : ORIGIN = REGION_DCCM_START, LENGTH = REGION_DCCM_SIZE
#endif
#if (REGION_XCCM_SIZE != 0)
REGION_XCCM : ORIGIN = REGION_XCCM_START, LENGTH = REGION_XCCM_SIZE
#endif
#if (REGION_YCCM_SIZE != 0)
REGION_YCCM : ORIGIN = REGION_YCCM_START, LENGTH = REGION_YCCM_SIZE
#endif
#if (REGION_EXT_ROM_SIZE != 0)
REGION_EXT_ROM : ORIGIN = REGION_EXT_ROM_START, LENGTH = REGION_EXT_ROM_SIZE
#endif
#if (REGION_EXT_RAM_SIZE != 0)
REGION_EXT_RAM : ORIGIN = REGION_EXT_RAM_START, LENGTH = REGION_EXT_RAM_SIZE
#endif
}
ENTRY(_start)
SECTIONS
{
.init :
{
. = . + IMAGE_HEAD_SIZE;
_f_init = .;
KEEP (*(.init_vector .init_vector.*))
KEEP (*(.init_bootstrap .init_bootstrap.*))
_e_init = .;
} > REGION_ROM
.vector : ALIGN(1024)
{
_f_vector = .;
*(.vector .vector.*)
_e_vector = .;
} > REGION_ROM
#if (REGION_XCCM_SIZE != 0)
.x_ccm (NOLOAD) : ALIGN(8)
{
_f_x_ccm = .;
*(.x_ccm .x_cmm.*)
_e_x_ccm = .;
} > REGION_XCCM
#endif
#if (REGION_YCCM_SIZE != 0)
.y_ccm (NOLOAD) : ALIGN(8)
{
_f_y_ccm = .;
*(.y_ccm .y_ccm.*)
_e_y_ccm = .;
} > REGION_YCCM
#endif
.text : ALIGN(4)
{
_f_text = .;
*(.text .text.* .gnu.linkonce.t.*)
_e_text = .;
} > REGION_ROM
.rodata : ALIGN(4)
{
_f_rodata = .;
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
. = ALIGN(4);
__CTOR_LIST__ = .;
LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
KEEP(*(SORT_BY_NAME(".ctors*")))
LONG(0)
__CTOR_END__ = .;
. = ALIGN(4);
__init_array_start = .;
KEEP(*(SORT_BY_NAME(".init_array*")))
__init_array_end = .;
. = ALIGN(4);
__DTOR_LIST__ = .;
LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
KEEP(*(SORT_BY_NAME(".dtors*")))
LONG(0)
__DTOR_END__ = .;
*(.rodata .rodata.* .gnu.linkonce.r.*)
_e_rodata = .;
} > REGION_ROM
.data : ALIGN(4)
{
_f_data = .;
*(.data .data.* .gnu.linkonce.d.*)
_f_sdata = .;
__SDATA_BEGIN__ = .;
*(.sdata .sdata.* .gnu.linkonce.s.*)
PROVIDE (__sbss_start = .);
PROVIDE (___sbss_start = .);
_f_sbss = .;
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
_e_sbss = .;
PROVIDE (__sbss_end = .);
PROVIDE (___sbss_end = .);
#if defined(EMBARC_UNIT_TEST)
. = ALIGN(8);
_f_embarc_unittest = .;
KEEP(*(.embarc_unittest))
_e_embarc_unittest = .;
#endif
_e_sdata = .;
_e_data = .;
} > REGION_RAM AT > REGION_ROM
.bss (NOLOAD) : ALIGN(8)
{
_f_bss = .;
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
_e_bss = .;
} > REGION_RAM
.stack (NOLOAD) :
{
. = ALIGN(4);
_f_stack = .;
. = . + _STACKSIZE;
_e_stack = .;
} > REGION_RAM
.heap (NOLOAD) :
{
. = ALIGN(4);
__start_heap = . ;
_f_heap = .;
. = . + _HEAPSIZE;
_e_heap = .;
__end_heap = . ;
} > REGION_RAM
_load_addr_text = LOADADDR(.text);
_load_addr_rodata = LOADADDR(.rodata);
_load_addr_data = LOADADDR(.data);
}
bsp/synopsys/boards/linker_template_mw.ld 0 → 100644
浏览文件 @ fe24ae7c
#define __ASSEMBLY__
#include <target_mem_config.h>
MEMORY {
#if (REGION_ICCM_SIZE != 0)
REGION_ICCM : ORIGIN = REGION_ICCM_START, LENGTH = REGION_ICCM_SIZE
#endif
#if (REGION_DCCM_SIZE !=0)
REGION_DCCM : ORIGIN = REGION_DCCM_START, LENGTH = REGION_DCCM_SIZE
#endif
#if (REGION_XCCM_SIZE != 0)
REGION_XCCM : ORIGIN = REGION_XCCM_START, LENGTH = REGION_XCCM_SIZE
#endif
#if (REGION_YCCM_SIZE != 0)
REGION_YCCM : ORIGIN = REGION_YCCM_START, LENGTH = REGION_YCCM_SIZE
#endif
#if (REGION_EXT_ROM_SIZE != 0)
REGION_EXT_ROM : ORIGIN = REGION_EXT_ROM_START, LENGTH = REGION_EXT_ROM_SIZE
#endif
#if (REGION_EXT_RAM_SIZE != 0)
REGION_EXT_RAM : ORIGIN = REGION_EXT_RAM_START, LENGTH = REGION_EXT_RAM_SIZE
#endif
}
ENTRY(_start)
SECTIONS {
GROUP : {
.image_head: {
. = . + IMAGE_HEAD_SIZE;
}
.init_bootstrap:{
_f_init = .;
*(.init_vector .init_vector.*)
*(.init_bootstrap .init_bootstrap.*)
_e_init = .;
}
.vector ALIGN(1024): {
_f_vector = .;
*(.vector .vector.*)
_e_vector = .;
}
} > REGION_ROM
#if (REGION_XCCM_SIZE != 0)
GROUP (NOLOAD): {
.x_ccm ALIGN(8): {
_f_x_ccm = .;
*(.x_ccm)
*(.x_ccm.*)
_e_x_ccm = .;
}
} > REGION_XCCM
#endif
#if (REGION_YCCM_SIZE != 0)
GROUP (NOLOAD): {
.y_ccm ALIGN(8): {
_f_y_ccm = .;
*(.y_ccm)
*(.y_ccm.*)
_e_y_ccm = .;
}
} > REGION_YCCM
#endif
GROUP : {
.text ALIGN(4): {
_f_text = .;
*(TYPE text)
*(.text*)
_e_text = .;
}
.rodata ALIGN(4): {
_f_rodata = .;
_fctors = .;
*(.ctors*)
_ectors = .;
_fdtors = .;
*(.dtors*)
_edtors = .;
_feh_frame = .;
*(.eh_frame*)
_eeh_frame = .;
*(TYPE lit)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
*(FSymTab*)
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
*(VSymTab*)
__vsymtab_end = .;
. = ALIGN(4);
__rt_init_start = .;
*(.rti_fn*)
__rt_init_end = .;
. = ALIGN(4);
_e_rodata = .;
}
} > REGION_ROM
GROUP : {
.data ALIGN(8): {
_f_data = .;
_f_sdata = .;
*(.sdata)
*(.sbss)
_e_sdata = .;
*(TYPE data)
}
#if defined(EMBARC_UNIT_TEST)
.unit_test ALIGN(8): {
_f_embarc_unittest = .;
KEEP(*(".embarc_unittest"))
_e_embarc_unittest = .;
}
#endif
.tls ALIGN(8): {
*(.tls*)
_e_data = .;
}
} > REGION_RAM AT > REGION_ROM
GROUP (NOLOAD) : {
.bss ALIGN(8): {
_f_bss = .;
*(TYPE bss)
_e_bss = .;
}
.stack ALIGN(4) SIZE(_STACKSIZE): {}
.heap? ALIGN(4) SIZE(_HEAPSIZE): {}
} > REGION_RAM
_f_stack = ADDR(.stack);
_e_stack = ADDR(.stack) + SIZEOF(.stack);
_f_heap = ADDR(.heap);
_e_heap = ADDR(.heap) + SIZEOF(.heap);
_load_addr_text = LOADADDR(.text);
_load_addr_rodata = LOADADDR(.rodata);
_load_addr_data = LOADADDR(.data);
}
bsp/synopsys/boards/rtconfig.h 0 → 100644
浏览文件 @ fe24ae7c
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 1024
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_DEBUG
#define RT_DEBUG_COLOR
#define RT_DEBUG_INIT_CONFIG
#define RT_DEBUG_INIT 1
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_MEMHEAP
#define RT_USING_SMALL_MEM
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40002
#define RT_USING_CPU_FFS
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
/* C++ features */
/* Command shell */
#define RT_USING_FINSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_ARG_MAX 10
/* Device virtual file system */
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 1024
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
#define RT_SYSTEM_WORKQUEUE_PRIORITY 8
#define RT_USING_SERIAL
#define RT_SERIAL_RB_BUFSZ 1024
/* Using USB */
/* POSIX layer and C standard library */
/* Network */
/* Socket abstraction layer */
/* Network interface device */
/* light weight TCP/IP stack */
/* AT commands */
/* VBUS(Virtual Software BUS) */
/* Utilities */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* multimedia packages */
/* tools packages */
/* system packages */
#define PKG_USING_EMBARC_BSP
#define PKG_USING_EMBARC_BSP_UPSTREAM_VERSION
/* peripheral libraries and drivers */
/* miscellaneous packages */
/* samples: kernel and components samples */
#define SOC_EMSK
#define EMSK_USING_UART0
#define EMSK_USING_UART1
#endif
bsp/synopsys/emsk_em9d/rtconfig.py → bsp/synopsys/boards/rtconfig.py
浏览文件 @ fe24ae7c
......@@ -8,12 +8,15 @@ CROSS_TOOL='gcc'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
# only support GNU GCC compiler
PLATFORM = 'gcc'
EXEC_PATH = 'C:/arc/gnu/bin'
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = 'C:/arc_gnu/bin'
elif CROSS_TOOL =='mw':
PLATFORM = 'mw'
EXEC_PATH = 'C:/ARC/MetaWare/arc/bin'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
# if os.getenv('RTT_EXEC_PATH'):
# EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
......@@ -30,31 +33,26 @@ if PLATFORM == 'gcc':
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DBG = PREFIX + 'gdb'
DEVICE = ' -mno-sdata -Wall -mcpu=em4_fpus -mlittle-endian -mcode-density -mdiv-rem -mswap -mnorm -mmpy-option=6 -mbarrel-shifter -mfpu=fpus_all'
CFLAGS = DEVICE
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
LINK_SCRIPT = 'emsk_em9d.ld'
LFLAGS = DEVICE + ' -mno-sdata -nostartfiles -Wl,--gc-sections,-Map=emsk_em9d.map,-cref,-u,system_vectors -T %s' % LINK_SCRIPT
OPENOCD_SCRIPT_ROOT = 'C:/arc/gnu/share/openocd/scripts'
OPENOCD_CFG_FILE = OPENOCD_SCRIPT_ROOT + '/board/snps_em_sk_v2.2.cfg'
TARGET = 'rtthread_snps_embarc.elf'
OPENOCD_OPTIONS = '-s %s -f %s' % (OPENOCD_SCRIPT_ROOT, OPENOCD_CFG_FILE)
DBG_HW_FLAGS = ''' -ex "target remote | openocd --pipe %s" -ex "load" ''' % OPENOCD_OPTIONS
TARGET = 'rtthread_snps_emsk_em9d.' + TARGET_EXT
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread_snps_embarc.bin\n' +\
SIZE + ' $TARGET \n'
CPATH = ''
LPATH = ''
elif PLATFORM == 'mw':
# toolchains
CC = 'ccac'
CXX = 'ccac'
AS = 'ccac'
AR = 'arac'
LINK = 'ccac'
TARGET_EXT = 'elf'
SIZE = 'sizeac'
OBJDUMP = 'elfdumpac'
OBJCPY = 'elf2bin'
DBG = 'mdb'
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
TARGET = 'rtthread_snps_embarc.elf'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\
POST_ACTION = OBJCPY + ' $TARGET rtthread_snps_embarc.bin\n' +\
SIZE + ' $TARGET \n'
#POST_ACTION = DBG + DBG_HW_FLAGS + TARGET
bsp/synopsys/embarc/SConscript 已删除 100644 → 0
浏览文件 @ 54814c42
from building import *
cwd = GetCurrentDir()
embarc_arc_hal_SRCS = Split("""
arc/arc_cache.c
arc/arc_exc_asm.S
arc/arc_exception.c
arc/arc_timer.c
arc/startup/arc_cxx_support.c
arc/startup/arc_startup.S
device/designware/uart/dw_uart.c
device/designware/gpio/dw_gpio.c
""")
ASFLAGS = ' -I' + cwd
src = embarc_arc_hal_SRCS
path = [cwd,
cwd + '/arc',
cwd + '/arc/startup'
]
group = DefineGroup('embarc', src, depend = [], CPPPATH = path, ASFLAGS = ASFLAGS)
Return('group')
bsp/synopsys/embarc/arc/arc_cache.c 已删除 100644 → 0
浏览文件 @ 54814c42
/* ------------------------------------------
* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2016.05
* \date 2014-07-15
* \author Wayne Ren(Wei.Ren@synopsys.com)
--------------------------------------------- */
/**
* \file
* \ingroup ARC_HAL_MISC_CACHE
* \brief implementation of cache related functions
*/
#include "inc/arc/arc_cache.h"
#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
struct cache_config {
uint8_t ver; /* version */
uint8_t assoc; /* Cache Associativity */
uint16_t line; /* cache line/block size */
uint32_t capacity; /* capacity */
};
static struct cache_config icache_config, dcache_config;
/**
* \brief invalidate multi instruction cache lines
*
* \param[in] start_addr start address in instruction cache
* \param[in] size the bytes to be invalidated
* \return 0, succeeded, -1, failed
*/
int32_t icache_invalidate_mlines(uint32_t start_addr, uint32_t size)
{
if (!icache_available()) return -1;
if ((size == 0) || (size > icache_config.capacity)) {
return -1;
}
uint32_t end_addr;
uint32_t line_size;
uint32_t status;
line_size = (uint32_t)(icache_config.line);
end_addr = start_addr + size - 1;
start_addr &= (uint32_t)(~(line_size - 1));
status = cpu_lock_save();
do {
_arc_aux_write(AUX_IC_IVIL, start_addr);
Asm("nop_s");
Asm("nop_s");
Asm("nop_s");
start_addr += line_size;
} while (start_addr <= end_addr);
cpu_unlock_restore(status);
return 0;
}
/**
* \brief lock multi lines in instruction cache
*
* \param[in] start_addr start address in instruction cache
* \param[in] size the bytes to be locked
* \return 0, succeeded, -1, failed (cache already locked or other reasons)
*/
int32_t icache_lock_mlines(uint32_t start_addr, uint32_t size)
{
if (!icache_available()) return -1;
if ((size == 0) || (size > icache_config.capacity)) {
return -1;
}
uint32_t end_addr;
uint32_t line_size;
uint32_t status;
int32_t ercd = 0;
line_size = (uint32_t)(icache_config.line);
end_addr = start_addr + size - 1;
start_addr &= (uint32_t)(~(line_size - 1));
status = cpu_lock_save();
do {
_arc_aux_write(AUX_IC_LIL, start_addr);
if(_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_OP_SUCCEEDED) {
start_addr += line_size;
} else {
ercd = -1; /* the operation failed */
break;
}
} while (start_addr <= end_addr);
cpu_unlock_restore(status);
return ercd;
}
/**
* \brief directly write icache internal ram
*
* \param[in] cache_addr, icache internal address(way+index+offset)
* \param[in] tag cache tag to write (tag+lock bit+valid bit)
* \param[in] data cache data to write
* \return 0, succeeded, -1, failed
*/
int32_t icache_direct_write(uint32_t cache_addr, uint32_t tag, uint32_t data)
{
if (!icache_available()) return -1;
if (_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_INDIRECT_ACCESS) {
return -1;
}
_arc_aux_write(AUX_IC_RAM_ADDR, cache_addr);
_arc_aux_write(AUX_IC_TAG, tag );
_arc_aux_write(AUX_IC_DATA, data);
return 0;
}
/**
* \brief directly read icache internal ram
*
* \param[in] cache_addr, icache internal address(way+index+offset)
* \param[out] tag cache tag to read (tag+index+lock bit+valid bit)
* \param[out] data cache data to read
* \return 0, succeeded, -1, failed
*/
int32_t icache_direct_read(uint32_t cache_addr, uint32_t *tag, uint32_t *data)
{
if (!icache_available()) return -1;
if (_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_INDIRECT_ACCESS) {
return -1;
}
_arc_aux_write(AUX_IC_RAM_ADDR, cache_addr);
*tag = _arc_aux_read(AUX_IC_TAG);
*data = _arc_aux_read(AUX_IC_DATA);
return 0;
}
/**
* \brief indirectly read icache internal ram
*
* \param[in] mem_addr, memory address
* \param[out] tag cache tag to read
* \param[out] data cache data to read
* \return 0, succeeded, -1, failed
*/
int32_t icache_indirect_read(uint32_t mem_addr, uint32_t *tag, uint32_t *data)
{
if (!icache_available()) return -1;
if (!(_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_INDIRECT_ACCESS)) {
return -1;
}
_arc_aux_write(AUX_IC_RAM_ADDR, mem_addr);
if(_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_OP_SUCCEEDED) {
*tag = _arc_aux_read(AUX_IC_TAG);
*data = _arc_aux_read(AUX_IC_DATA);
} else {
return -1; /* the specified memory is not in icache */
}
return 0;
}
/**
* \brief invalidate multi data cache lines
*
* \param[in] start_addr start address in data cache
* \param[in] size the bytes to be invalidated
* \return 0, succeeded, -1, failed
*/
int32_t dcache_invalidate_mlines(uint32_t start_addr, uint32_t size)
{
if (!dcache_available()) return -1;
uint32_t end_addr;
uint32_t line_size;
uint32_t status;
if ((size == 0) || (size > dcache_config.capacity)) {
return -1;
}
line_size = (uint32_t)(dcache_config.line);
end_addr = start_addr + size - 1;
start_addr &= (uint32_t)(~(line_size - 1));
status = cpu_lock_save();
do {
_arc_aux_write(AUX_DC_IVDL, start_addr);
Asm("nop_s");
Asm("nop_s");
Asm("nop_s");
/* wait for flush completion */
while (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
start_addr += line_size;
} while (start_addr <= end_addr);
cpu_unlock_restore(status);
return 0;
}
/**
* \brief flush multi lines in data cache
*
* \param[in] start_addr start address
* \param[in] size the bytes to be flushed
* \return 0, succeeded, -1, failed
*/
int32_t dcache_flush_mlines(uint32_t start_addr, uint32_t size)
{
if (!dcache_available()) return -1;
if ((size == 0) || (size > dcache_config.capacity)) {
return -1;
}
uint32_t end_addr;
uint32_t line_size;
uint32_t status;
line_size = (uint32_t)(dcache_config.line);
end_addr = start_addr + size - 1;
start_addr &= (uint32_t)(~(line_size - 1));
status = cpu_lock_save();
do {
_arc_aux_write(AUX_DC_FLDL, start_addr);
Asm("nop_s");
Asm("nop_s");
Asm("nop_s");
/* wait for flush completion */
while (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
start_addr += line_size;
} while (start_addr <= end_addr);
cpu_unlock_restore(status);
return 0;
}
/**
* \brief lock multi lines in data cache
*
* \param[in] start_addr start address in data cache
* \param[in] size the bytes to be locked
* \return 0, succeeded, -1, failed
*/
int32_t dcache_lock_mlines(uint32_t start_addr, uint32_t size)
{
if (!dcache_available()) return -1;
if ((size == 0) || (size > dcache_config.capacity)) {
return -1;
}
uint32_t end_addr;
uint32_t line_size;
uint32_t status;
int32_t ercd = 0;
line_size = (uint32_t)(dcache_config.line);
end_addr = start_addr + size - 1;
start_addr &= (uint32_t)(~(line_size - 1));
status = cpu_lock_save();
do {
_arc_aux_write(AUX_DC_LDL, start_addr);
Asm("nop_s");
if(_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_OP_SUCCEEDED) {
start_addr += line_size;
} else {
ercd = -1; /* the operation failed */
break;
}
} while (start_addr <= end_addr);
cpu_unlock_restore(status);
return ercd;
}
/**
* \brief directly write dcache internal ram
*
* \param[in] cache_addr, dcache internal address(way+index+offset)
* \param[in] tag cache tag to write
* \param[in] data cache data to write
* \return 0, succeeded, -1, failed
*/
int32_t dcache_direct_write(uint32_t cache_addr, uint32_t tag, uint32_t data)
{
if (!dcache_available()) return -1;
if (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_INDIRECT_ACCESS) {
return -1;
}
_arc_aux_write(AUX_DC_RAM_ADDR, cache_addr);
_arc_aux_write(AUX_DC_TAG, tag);
_arc_aux_write(AUX_DC_DATA, data);
return 0;
}
/**
* \brief directly read dcache internal ram
*
* \param[in] cache_addr, dcache internal address(way+index+offset)
* \param[out] tag cache tag to read
* \param[out] data cache data to read
* \return 0, succeeded, -1, failed
*/
int32_t dcache_direct_read(uint32_t cache_addr, uint32_t *tag, uint32_t *data)
{
if (!dcache_available()) return -1;
if (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_INDIRECT_ACCESS) {
return -1;
}
_arc_aux_write(AUX_DC_RAM_ADDR, cache_addr);
*tag = _arc_aux_read(AUX_DC_TAG);
*data = _arc_aux_read(AUX_DC_DATA);
return 0;
}
/**
* \brief indirectly read dcache internal ram
*
* \param[in] mem_addr, memory address(tag+index+offset)
* \param[out] tag cache tag to read
* \param[out] data cache data to read
* \return 0, succeeded, -1, failed
*/
int32_t dcache_indirect_read(uint32_t mem_addr, uint32_t *tag, uint32_t *data)
{
if (!dcache_available()) return -1;
if (!(_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_INDIRECT_ACCESS)) {
return -1;
}
_arc_aux_write(AUX_DC_RAM_ADDR, mem_addr);
if(_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_OP_SUCCEEDED) {
*tag = _arc_aux_read(AUX_DC_TAG);
*data = _arc_aux_read(AUX_DC_DATA);
} else {
return -1; /* the specified memory is not in dcache */
}
return 0;
}
/**
* \brief initialize cache
* 1. invalidate icache and dcache
* 2. Only support ARCv2 cache
*/
void arc_cache_init(void)
{
uint32_t build_cfg;
build_cfg = _arc_aux_read(AUX_BCR_D_CACHE);
dcache_config.ver = build_cfg & 0xff;
if (dcache_config.ver >= 0x04) { /* ARCv2 */
dcache_enable(DC_CTRL_DISABLE_FLUSH_LOCKED |
DC_CTRL_INDIRECT_ACCESS | DC_CTRL_INVALID_FLUSH);
dcache_invalidate();
dcache_config.assoc = 1 << ((build_cfg >> 8) & 0xf);
dcache_config.capacity = 512 << ((build_cfg >> 12) & 0xf);
dcache_config.line = 16 << ((build_cfg >> 16) & 0xf);
}
build_cfg = _arc_aux_read(AUX_BCR_I_CACHE);
icache_config.ver = build_cfg & 0xff;
if (icache_config.ver >= 0x04) { /* ARCv2 */
icache_config.assoc = 1 << ((build_cfg >> 8) & 0xf);
icache_config.capacity = 512 << ((build_cfg >> 12) & 0xf);
icache_config.line = 8 << ((build_cfg >> 16) & 0xf);
icache_enable(IC_CTRL_IC_ENABLE);
icache_invalidate();
}
}
bsp/synopsys/embarc/arc/arc_exc_asm.S 已删除 100644 → 0
浏览文件 @ 54814c42
/* ------------------------------------------
* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2016.05
* \date 2014-07-15
* \author Wayne Ren(Wei.Ren@synopsys.com)
--------------------------------------------- */
/**
* \file
* \ingroup ARC_HAL_EXCEPTION_CPU
* \brief assembly part of exception and interrupt processing
*/
/**
* \addtogroup ARC_HAL_EXCEPTION_CPU
* @{
*/
/* function documentation */
/**
* \fn void exc_entry_cpu(void)
* \brief default entry of CPU exceptions, such as TLB miss and swap.
*
* \fn void exc_entry_int(void)
* \brief normal interrupt exception entry.
* In default, all interrupt exceptions are installed with normal entry.
* If FIRQ is required, exc_entry_firq should be the entry.
*
* \fn void exc_entry_firq(void)
* \brief firq exception entry
*/
/** }@ */
/** @cond EXCEPTION_ASM */
#define __ASSEMBLY__
#include "inc/arc/arc.h"
#include "inc/arc/arc_asm_common.h"
.file "arc_exc_asm.S"
/* entry for cpu exception handling */
.text
.global exc_entry_cpu
.weak exc_entry_cpu
.align 4
exc_entry_cpu:
EXCEPTION_PROLOGUE
mov r3, sp /* as exception handler's para(exc_frame) */
/* exc_nest_count +1 */
ld r0, [exc_nest_count]
add r0, r0, 1
st r0, [exc_nest_count]
/* find the exception cause */
lr r0, [AUX_ECR]
lsr r0, r0, 16
bmsk r0, r0, 7
mov r1, exc_int_handler_table
ld.as r2, [r1, r0]
mov r0, r3
jl [r2] /* jump to exception handler where interrupts are not allowed! */
/* interrupts are not allowed */
exc_return:
/* exc_nest_count -1 */
ld r0, [exc_nest_count]
sub r0, r0, 1
st r0, [exc_nest_count]
EXCEPTION_EPILOGUE
rtie
/****** entry for normal interrupt exception handling ******/
.global exc_entry_int
.weak exc_entry_int
.align 4
exc_entry_int:
clri /* disable interrupt */
#if ARC_FEATURE_FIRQ == 1
#if ARC_FEATURE_RGF_NUM_BANKS > 1
lr r0, [AUX_IRQ_ACT] /* check whether it is P0 interrupt */
btst r0, 0
bnz exc_entry_firq
#else
PUSH r10
lr r10, [AUX_IRQ_ACT]
btst r10, 0
POP r10
bnz exc_entry_firq
#endif
#endif
INTERRUPT_PROLOGUE /* save scratch regs, this will be affected */
/* exc_nest_count +1 */
ld r0, [exc_nest_count]
add r0, r0, 1
st r0, [exc_nest_count]
lr r0, [AUX_IRQ_CAUSE]
mov r1, exc_int_handler_table
ld.as r2, [r1, r0] /* r2 = _kernel_exc_tbl + irqno *4 */
/* for the case of software triggered interrupt */
lr r3, [AUX_IRQ_HINT]
cmp r3, r0
bne.d irq_hint_handled
xor r3, r3, r3
sr r3, [AUX_IRQ_HINT]
irq_hint_handled:
seti /* enable higher priority interrupt */
mov r0, sp
jl [r2] /* jump to interrupt handler */
/* no interrupts are allowed from here */
int_return:
clri /* disable interrupt */
/* exc_nest_count -1 */
ld r0, [exc_nest_count]
sub r0, r0, 1
st r0, [exc_nest_count]
INTERRUPT_EPILOGUE
rtie
/****** entry for fast irq exception handling ******/
.global exc_entry_firq
.weak exc_entry_firq
.align 4
exc_entry_firq:
clri /* disable interrupt */
SAVE_FIQ_EXC_REGS
/* exc_nest_count +1 */
ld r0, [exc_nest_count]
add r0, r0, 1
st r0, [exc_nest_count]
lr r0, [AUX_IRQ_CAUSE]
mov r1, exc_int_handler_table
ld.as r2, [r1, r0] /* r2 = _kernel_exc_tbl + irqno *4 */
/* for the case of software triggered interrupt */
lr r3, [AUX_IRQ_HINT]
cmp r3, r0
bne.d firq_hint_handled
xor r3, r3, r3
sr r3, [AUX_IRQ_HINT]
firq_hint_handled:
jl [r2] /* jump to interrupt handler */
/* no interrupts are allowed from here */
firq_return:
/* exc_nest_count -1 */
ld r0, [exc_nest_count]
sub r0, r0, 1
st r0, [exc_nest_count]
RESTORE_FIQ_EXC_REGS
rtie
/** @endcond */
bsp/synopsys/embarc/arc/arc_exception.c 已删除 100644 → 0
浏览文件 @ 54814c42
/* ------------------------------------------
* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2016.05
* \date 2014-07-15
* \author Wayne Ren(Wei.Ren@synopsys.com)
--------------------------------------------- */
/**
* \file
* \ingroup ARC_HAL_EXCEPTION_CPU ARC_HAL_EXCEPTION_INTERRUPT
* \brief C Implementation of exception and interrupt management
*/
#include "inc/arc/arc_exception.h"
#include "inc/arc/arc_cache.h"
//#define DBG_LESS
//#include "embARC_debug.h"
/**
* \addtogroup ARC_HAL_EXCEPTION_CPU
* @{
* \var exc_entry_table
* \brief exception entry table
*
* install exception entry table to ARC_AUX_INT_VECT_BASE in startup.
* According to ARCv2 ISA, vectors are fetched in instruction space and thus
* may be present in ICCM, Instruction Cache, or
* main memory accessed by instruction fetch logic.
* So it is put into a specific section .vector.
*
* Please note that the exc_entry_table maybe cached in ARC. Some functions is
* defined in .s files.
*
*/
/**
* \ingroup ARC_HAL_EXCEPTION_CPU
* \brief default cpu exception handler
* \param p_excinf pointer to the exception frame
*/
static void exc_handler_default(void *p_excinf)
{
// uint32_t excpt_cause_reg = 0;
// uint32_t excpt_ret_reg = 0;
// uint32_t exc_no = 0;
// excpt_cause_reg = _arc_aux_read(AUX_ECR);
// excpt_ret_reg = _arc_aux_read(AUX_ERRET);
// exc_no = (excpt_cause_reg >> 16) & 0xff;
Asm("kflag 1");
}
/**
* \ingroup ARC_HAL_EXCEPTION_INTERRUPT
* \brief default interrupt handler
* \param[in] p_excinf information for interrupt handler
*/
static void int_handler_default(void *p_excinf)
{
// uint32_t int_cause_reg = 0;
// int_cause_reg = _arc_aux_read(AUX_IRQ_CAUSE);
Asm("kflag 1");
}
__attribute__ ((aligned(1024), section(".vector")))
EXC_ENTRY exc_entry_table[NUM_EXC_ALL] = {
[0] = _arc_reset,
[1 ... NUM_EXC_CPU-1] = exc_entry_cpu,
[NUM_EXC_CPU ... NUM_EXC_ALL-1] = exc_entry_int
};
/**
* \var exc_int_handler_table
* \brief the cpu exception and interrupt exception handler table
* called in exc_entry_default and exc_entry_int
*/
EXC_HANDLER exc_int_handler_table[NUM_EXC_ALL] = {
[0 ... NUM_EXC_CPU-1] = exc_handler_default,
[NUM_EXC_CPU ... NUM_EXC_ALL-1] = int_handler_default
};
/**
* \var exc_nest_count
* \brief the counter for exc/int processing, =0 no int/exc
* >1 in int/exc processing
* @}
*/
uint32_t exc_nest_count;
typedef struct aux_irq_ctrl_field {
/* note: little endian */
uint32_t save_nr_gpr_pairs: 5; /** Indicates number of general-purpose register pairs saved, from 0 to 8/16 */
uint32_t res: 4; /** Reserved */
uint32_t save_blink: 1; /** Indicates whether to save and restore BLINK */
uint32_t save_lp_regs: 1; /** Indicates whether to save and restore loop registers (LP_COUNT, LP_START, LP_END) */
uint32_t save_u_to_u: 1; /** Indicates if user context is saved to user stack */
uint32_t res2: 1; /** Reserved */
uint32_t save_idx_regs: 1; /** Indicates whether to save and restore code-density registers (EI_BASE, JLI_BASE, LDI_BASE) */
uint32_t res3: 18; /** Reserved */
} aux_irq_ctrl_field_t;
typedef union {
aux_irq_ctrl_field_t bits;
uint32_t value;
} aux_irq_ctrl_t;
/**
* \ingroup ARC_HAL_EXCEPTION_CPU ARC_HAL_EXCEPTION_INTERRUPT
* \brief intialize the exception and interrupt handling
*/
void exc_int_init(void)
{
uint32_t i;
uint32_t status;
aux_irq_ctrl_t ictrl;
ictrl.value = 0;
#ifndef ARC_FEATURE_RF16
ictrl.bits.save_nr_gpr_pairs = 6; /* r0 to r11 (r12 saved manually) */
#else
ictrl.bits.save_nr_gpr_pairs = 3; /* r0 to r3, r10, r11 */
#endif
ictrl.bits.save_blink = 1;
ictrl.bits.save_lp_regs = 1; /* LP_COUNT, LP_START, LP_END */
ictrl.bits.save_u_to_u = 0; /* user ctxt saved on kernel stack */
ictrl.bits.save_idx_regs = 1; /* JLI, LDI, EI */
status = arc_lock_save();
for (i = NUM_EXC_CPU; i < NUM_EXC_ALL; i++) {
/* interrupt level triggered, disabled, priority is the lowest */
_arc_aux_write(AUX_IRQ_SELECT, i);
_arc_aux_write(AUX_IRQ_ENABLE, 0);
_arc_aux_write(AUX_IRQ_TRIGGER, 0);
#if defined(ARC_FEATURE_SEC_PRESENT) && (SECURESHIELD_VERSION < 2)
_arc_aux_write(AUX_IRQ_PRIORITY, (1 << AUX_IRQ_PRIORITY_BIT_S)|(INT_PRI_MAX - INT_PRI_MIN));
#else
_arc_aux_write(AUX_IRQ_PRIORITY, INT_PRI_MAX - INT_PRI_MIN);
#endif
}
_arc_aux_write(AUX_IRQ_CTRL, ictrl.value);
arc_unlock_restore(status);
/** ipm should be set after cpu unlock restore to avoid reset of the status32 value */
arc_int_ipm_set((INT_PRI_MAX - INT_PRI_MIN));
}
/**
* \ingroup ARC_HAL_EXCEPTION_CPU
* \brief install a CPU exception entry
* \param[in] excno exception number
* \param[in] entry the entry of exception to install
*/
int32_t exc_entry_install(const uint32_t excno, EXC_ENTRY entry)
{
uint32_t status;
EXC_ENTRY *table = (EXC_ENTRY *)_arc_aux_read(AUX_INT_VECT_BASE);
if (excno < NUM_EXC_ALL && entry != NULL
&& table[excno] != entry) {
status = cpu_lock_save();
/* directly write to mem, as arc gets exception handler from mem not from cache */
/* FIXME, here maybe icache is dirty, need to be invalidated */
table[excno] = entry;
if (_arc_aux_read(AUX_BCR_D_CACHE) > 0x2) {
/* dcache is available */
dcache_flush_line((uint32_t)&table[excno]);
}
if (_arc_aux_read(AUX_BCR_D_CACHE) > 0x2) {
/* icache is available */
icache_invalidate_line((uint32_t)&table[excno]);
}
cpu_unlock_restore(status);
return 0;
}
return -1;
}
/**
* \ingroup ARC_HAL_EXCEPTION_CPU
* \brief get the installed CPU exception entry
* \param[in] excno exception number
* \return the installed CPU exception entry
*/
EXC_ENTRY exc_entry_get(const uint32_t excno)
{
if (excno < NUM_EXC_ALL) {
return exc_entry_table[excno];
}
return NULL;
}
/**
* \ingroup ARC_HAL_EXCEPTION_CPU
* \brief install an exception handler
* \param[in] excno exception number
* \param[in] handler the handler of exception to install
*/
int32_t exc_handler_install(const uint32_t excno, EXC_HANDLER handler)
{
if (excno < NUM_EXC_ALL && handler != NULL) {
exc_int_handler_table[excno] = handler;
return 0;
}
return -1;
}
/**
* \ingroup ARC_HAL_EXCEPTION_CPU
* \brief get the installed exception handler
* \param[in] excno exception number
* \return the installed exception handler or NULL
*/
EXC_HANDLER exc_handler_get(const uint32_t excno)
{
if (excno < NUM_EXC_ALL) {
return exc_int_handler_table[excno];
}
return NULL;
}
#ifndef EMBARC_OVERRIDE_ARC_INTERRUPT_MANAGEMENT
/**
* \brief disable the specific interrupt
*
* \param[in] intno interrupt number
*/
int32_t int_disable(const uint32_t intno)
{
if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
arc_int_disable(intno);
return 0;
}
return -1;
}
/**
* \brief enable the specific int
*
* \param[in] intno interrupt number
*/
int32_t int_enable(const uint32_t intno)
{
if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
arc_int_enable(intno);
return 0;
}
return -1;
}
/**
* \brief check whether the specific int is enabled
*
* \param[in] intno interrupt number
* \return 0 disabled, 1 enabled, < 0 error
*/
int32_t int_enabled(const uint32_t intno)
{
if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
_arc_aux_write(AUX_IRQ_SELECT, intno);
return _arc_aux_read(AUX_IRQ_ENABLE);
}
return -1;
}
/**
* \brief get the interrupt priority mask
*
* \returns interrupt priority mask, negative num
*/
int32_t int_ipm_get(void)
{
return ((int32_t)arc_int_ipm_get() + INT_PRI_MIN);
}
/**
* \brief set the interrupt priority mask
*
* \param[in] intpri interrupt priority
*/
int32_t int_ipm_set(int32_t intpri)
{
if (intpri >= INT_PRI_MIN && intpri <= INT_PRI_MAX) {
intpri = intpri - INT_PRI_MIN;
arc_int_ipm_set(intpri);
return 0;
}
return -1;
}
/**
* \brief get current interrupt priority mask
*
* \param[in] intno interrupt number
* \return <0 interrupt priority, 0 error
*/
int32_t int_pri_get(const uint32_t intno)
{
if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
return (int32_t)arc_int_pri_get(intno) + INT_PRI_MIN;
}
return 0;
}
/**
* \brief set interrupt priority
*
* \param[in] intno interrupt number
* \param[in] intpri interrupt priority
* \return <0 error, 0 ok
*/
int32_t int_pri_set(const uint32_t intno, int32_t intpri)
{
uint32_t status;
if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
status = cpu_lock_save();
intpri = intpri - INT_PRI_MIN;
arc_int_pri_set(intno,(uint32_t)intpri);
cpu_unlock_restore(status);
return 0;
}
return -1;
}
/**
* \brief set interrupt secure or not secure
* This function is valid in secureshield v2
* \param[in] intno interrupt number
* \param[in] secure, 0 for normal, >0 for secure
* \return <0 error, 0 ok
*/
int32_t int_secure_set(const uint32_t intno, uint32_t secure)
{
if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
arc_int_secure_set(intno, secure);
return 0;
}
return -1;
}
/**
* \brief probe the pending status of interrupt
*
* \param[in] intno interrupt number
*
* \returns 1 pending, 0 no pending, -1 error
*/
int32_t int_probe(const uint32_t intno)
{
if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
return arc_int_probe(intno);
}
return -1;
}
/**
* \brief trigger the interrupt in software
*
* \param[in] intno interrupt number
* \return 0 ok, -1 error
*/
int32_t int_sw_trigger(const uint32_t intno)
{
if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
arc_int_sw_trigger(intno);
return 0;
}
return -1;
}
/**
* \brief config the interrupt level triggered or pulse triggered
*
* \param[in] intno interrupt number
* \param[in] level, 0-level trigger, 1-pulse triggered
* \return 0 ok, -1 error
*/
int32_t int_level_config(const uint32_t intno, const uint32_t level)
{
if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) {
arc_int_level_config(intno, level);
return 0;
}
return -1;
}
/**
* \brief lock cpu, disable interrupts
*/
void cpu_lock(void)
{
arc_lock();
}
/**
* \brief unlock cpu, enable interrupts to happen
*/
void cpu_unlock(void)
{
arc_unlock();
}
/**
* \brief lock cpu and return status
*
* \returns cpu status
*/
uint32_t cpu_lock_save(void)
{
return arc_lock_save();
}
/**
* \brief unlock cpu with the specific status
*
* \param[in] status cpu status saved by cpu_lock_save
*/
void cpu_unlock_restore(const uint32_t status)
{
arc_unlock_restore(status);
}
/**
* \ingroup ARC_HAL_EXCEPTION_INTERRUPT
* \brief install an interrupt handler
* \param[in] intno interrupt number
* \param[in] handler interrupt handler to install
*/
int32_t int_handler_install(const uint32_t intno, INT_HANDLER handler)
{
/*!< \todo parameter check ? */
if (intno >= NUM_EXC_CPU) {
return exc_handler_install(intno, handler);
}
return -1;
}
/**
* \ingroup ARC_HAL_EXCEPTION_INTERRUPT
* \brief get the installed an interrupt handler
* \param[in] intno interrupt number
* \return the installed interrupt handler or NULL
*/
INT_HANDLER int_handler_get(const uint32_t intno)
{
if (intno >= NUM_EXC_CPU) {
return exc_handler_get(intno);
}
return NULL;
}
#endif /* EMBARC_OVERRIDE_ARC_INTERRUPT_MANAGEMENT */
bsp/synopsys/embarc/arc/arc_timer.c 已删除 100644 → 0
浏览文件 @ 54814c42
/* ------------------------------------------
* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2016.05
* \date 2014-07-15
* \author Wayne Ren(Wei.Ren@synopsys.com)
--------------------------------------------- */
/**
* \file
* \ingroup ARC_HAL_MISC_TIMER
* \brief implementation of internal timer related functions
* \todo RTC support should be improved if RTC is enabled
*/
#include "inc/arc/arc_timer.h"
#include "inc/arc/arc.h"
#include "inc/arc/arc_builtin.h"
/**
* \brief check whether the specific timer present
* \param[in] no timer number
* \retval 1 present
* \retval 0 not present
*/
int32_t arc_timer_present(const uint32_t no)
{
uint32_t bcr = _arc_aux_read(AUX_BCR_TIMERS);
switch (no) {
case TIMER_0:
bcr = (bcr >> 8) & 1;
break;
case TIMER_1:
bcr = (bcr >> 9) & 1;
break;
case TIMER_RTC:
bcr = (bcr >> 10) & 1;
break;
default:
bcr = 0;
/* illegal argument so return false */
break;
}
return (int)bcr;
}
/**
* \brief start the specific timer
* \param[in] no timer number
* \param[in] mode timer mode
* \param[in] val timer limit value (not for RTC)
* \return 0 success, -1 failure
*/
int32_t arc_timer_start(const uint32_t no, const uint32_t mode, const uint32_t val)
{
if (arc_timer_present(no) == 0) {
return -1;
}
switch (no) {
case TIMER_0:
_arc_aux_write(AUX_TIMER0_CTRL, 0);
_arc_aux_write(AUX_TIMER0_LIMIT, val);
_arc_aux_write(AUX_TIMER0_CTRL, mode);
_arc_aux_write(AUX_TIMER0_CNT, 0);
break;
case TIMER_1:
_arc_aux_write(AUX_TIMER1_CTRL, 0);
_arc_aux_write(AUX_TIMER1_LIMIT, val);
_arc_aux_write(AUX_TIMER1_CTRL, mode);
_arc_aux_write(AUX_TIMER1_CNT, 0);
break;
case TIMER_RTC:
_arc_aux_write(AUX_RTC_CTRL, mode);
break;
default:
return -1;
}
return 0;
}
/**
* \brief stop and clear the specific timer
*
* \param[in] no timer number
* \return 0 success, -1 failure
*/
int32_t arc_timer_stop(const uint32_t no)
{
if (arc_timer_present(no) == 0) {
return -1;
}
switch (no) {
case TIMER_0 :
_arc_aux_write(AUX_TIMER0_CTRL, 0);
_arc_aux_write(AUX_TIMER0_LIMIT,0);
_arc_aux_write(AUX_TIMER0_CNT, 0);
break;
case TIMER_1:
_arc_aux_write(AUX_TIMER1_CTRL, 0);
_arc_aux_write(AUX_TIMER1_LIMIT,0);
_arc_aux_write(AUX_TIMER1_CNT, 0);
break;
case TIMER_RTC:
_arc_aux_write(AUX_RTC_CTRL, TIMER_RTC_CLEAR);
break;
default:
return -1;
}
return 0;
}
/**
* \brief get timer current tick
*
* \param[in] no timer number
* \param[out] val, timer value
* \return 0 success, -1 failure
*/
int32_t arc_timer_current(const uint32_t no, void *val)
{
if (arc_timer_present(no) == 0) {
return -1;
}
switch (no) {
case TIMER_0 :
*((uint32_t *)val) = _arc_aux_read(AUX_TIMER0_CNT);
break;
case TIMER_1 :
*((uint32_t *)val) = _arc_aux_read(AUX_TIMER1_CNT);
break;
case TIMER_RTC:
*((uint64_t *)val) = _arc_aux_read(AUX_RTC_LOW);
break;
default :
return -1;
}
return 0;
}
/**
* \brief clear the interrupt pending bit of timer
*
* \param[in] no timer number
* \return 0 success, -1 failure
*/
int32_t arc_timer_int_clear(const uint32_t no)
{
uint32_t val;
if (arc_timer_present(no) == 0) {
return -1;
}
switch (no) {
case TIMER_0 :
val = _arc_aux_read(AUX_TIMER0_CTRL);
val &= ~TIMER_CTRL_IP;
_arc_aux_write(AUX_TIMER0_CTRL, val);
break;
case TIMER_1 :
val = _arc_aux_read(AUX_TIMER1_CTRL);
val &= ~TIMER_CTRL_IP;
_arc_aux_write(AUX_TIMER1_CTRL, val);
break;
default :
return -1;
}
return 0;
}
/**
* \brief init internal timer
*/
void arc_timer_init(void)
{
arc_timer_stop(TIMER_0);
arc_timer_stop(TIMER_1);
arc_timer_stop(TIMER_RTC);
}
bsp/synopsys/embarc/arc/startup/arc_cxx_support.c 已删除 100644 → 0
浏览文件 @ 54814c42
/*
* Copyright (c) 2012-2014 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* ------------------------------------------
* Copyright (c) 2015, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2016.05
* \date 2016-03-02
* \author Wayne Ren(wei.ren@synopsys.com)
--------------------------------------------- */
#include "embARC_BSP_config.h"
#if defined(__GNU__)
/* embARC's GNU C++ support takes reference from Zephyr (cpp_xxx.c) */
/**
* @file - Constructor module
* @brief
* The ctors section contains a list of function pointers that execute the
* C++ constructors of static global objects. These must be executed before
* the application's main() routine.
*
* NOTE: Not all compilers put those function pointers into the ctors section;
* some put them into the init_array section instead.
*/
/* What a constructor function pointer looks like */
typedef void (*CtorFuncPtr)(void);
/* Constructor function pointer list is generated by the linker script. */
extern CtorFuncPtr __CTOR_LIST__[];
extern CtorFuncPtr __CTOR_END__[];
/**
*
* @brief Invoke all C++ style global object constructors
*
* This routine is invoked before the execution of the
* application's main().
*/
void __do_global_ctors_aux(void)
{
unsigned int nCtors;
nCtors = (unsigned int)__CTOR_LIST__[0];
while (nCtors >= 1) {
__CTOR_LIST__[nCtors--]();
}
}
typedef void (*DtorFuncPtr)(void);
extern DtorFuncPtr __DTOR_LIST__[];
extern DtorFuncPtr __DTOR_END__[];
/**
*
* @brief Invoke all C++ style global object destructors
*
* This routine is invoked after the execution of the
* application's main().
*/
void __do_global_dtors_aux(void)
{
unsigned int nDtors;
unsigned int i;
nDtors = (unsigned int)__DTOR_LIST__[0];
i = 0;
while (i <= nDtors) {
__DTOR_LIST__[i++]();
}
}
void *__dso_handle = 0;
/**
* @brief Register destructor for a global object
*
* @param destructor the global object destructor function
* @param objptr global object pointer
* @param dso Dynamic Shared Object handle for shared libraries
*
* Function does nothing at the moment, assuming the global objects
* do not need to be deleted
*
* @return N/A
*/
int __cxa_atexit(void (*destructor)(void *), void *objptr, void *dso)
{
return 0;
}
typedef void (*func_ptr)(void);
extern func_ptr __init_array_start[0];
extern func_ptr __init_array_end[0];
/**
* @brief Execute initialization routines referenced in .init_array section
*
* @return N/A
*/
void __do_init_array_aux(void)
{
for (func_ptr *func = __init_array_start;
func < __init_array_end;
func++) {
(*func)();
}
}
/**
* @brief Stub for pure virtual functions
*
* This routine is needed for linking C++ code that uses pure virtual
* functions.
*
* @return N/A
*/
void __cxa_pure_virtual(void)
{
while (1) {
;
}
}
#endif
bsp/synopsys/embarc/arc/startup/arc_startup.S 已删除 100644 → 0
浏览文件 @ 54814c42
/* ------------------------------------------
* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2016.05
* \date 2014-07-15
* \author Wayne Ren(Wei.Ren@synopsys.com)
--------------------------------------------- */
/**
* \file
* \ingroup ARC_HAL_STARTUP
* \brief assembly part of startup process
*/
/**
* \addtogroup ARC_HAL_STARTUP
* @{
*/
/** @cond STARTUP_ASM */
#define __ASSEMBLY__
#include "embARC_BSP_config.h"
#include "inc/arc/arc.h"
.file "arc_startup.S"
.weak _f_sdata /* start of small data, defined in link script */
.weak init_hardware_hook /* app hardware init hook */
.weak init_software_hook /* app software init hook */
.extern board_main
.extern exc_entry_table
/* initial vector table */
.section .init_vector, "a"
.long _arc_reset
.section .init_bootstrap, "ax"
.global _arc_reset
.global _start
.align 4
_start:
_arc_reset:
_arc_reset_stage1:
kflag STATUS32_RESET_VALUE
/* STAGE 1 */
/* necessary hardware should be done first to speed up initialization
1. system clk
2. mem controller must be initialized before any access to external
mem.
3. others
*/
_arc_cache_init_start:
lr r0, [AUX_BCR_D_CACHE]
cmp r0, 2
/* invalidate dcache */
jle _arc_icache_init
mov r0, 1
sr r0, [AUX_DC_IVDC]
sr r0, [AUX_DC_CTRL]
_arc_icache_init:
lr r0, [AUX_BCR_I_CACHE]
cmp r0, 2
jle _arc_cache_init_end
/* invalidate icache */
mov r0, 1
sr r0, [AUX_IC_IVIC]
nop_s
nop_s
nop_s
sr r0, [AUX_IC_CTRL]
_arc_cache_init_end:
mov r0, init_hardware_hook
cmp r0, 0
jlne [r0]
/* STAGE 2: init necessary registers */
_arc_reset_stage2:
mov r0, 0
/* interrupt related init */
sr r0, [AUX_IRQ_ACT]
sr r0, [AUX_IRQ_CTRL]
sr r0, [AUX_IRQ_HINT]
/* use the new vector table to replace the old one */
#if defined(ARC_FEATURE_SEC_PRESENT) && (SECURESHIELD_VERSION < 2)
sr exc_entry_table, [AUX_INT_VECT_BASE_S]
#else
sr exc_entry_table, [AUX_INT_VECT_BASE]
#endif
/* init stack */
#if ARC_FEATURE_RGF_BANKED_REGS >= 16 && ARC_FEATURE_RGF_BANKED_REGS > 1 && ARC_FEATURE_FIRQ == 1
#if _STACKSIZE < 512
#error "not enough stack size for irq and firq"
#endif
/* switch to register bank1 */
lr r0, [AUX_STATUS32]
bic r0, r0, 0x70000
or r0, r0, 0x10000
kflag r0
/* set sp, gp, fp in bank1 */
mov sp, _e_stack
mov gp, _f_sdata
mov fp, 0
/* come back to bank0 */
lr r0, [AUX_STATUS32]
bic r0, r0, 0x70000
kflag r0
mov sp, _e_stack-256
#else
mov sp, _e_stack /* init stack pointer */
#endif
mov gp, _f_sdata /* init small-data base register */
mov fp, 0 /* init fp register */
_arc_reset_stage3:
_s3_copy_text:
mov r0, _f_text
mov r1, _load_addr_text
cmp r0, r1
/* if load addr == run addr, no need to copy */
jeq _s3_copy_rodata
mov r3, _e_text
_s3_copy_text_loop:
ld.ab r2, [r1, 4]
st.ab r2, [r0, 4]
cmp r0, r3
jlt _s3_copy_text_loop
_s3_copy_rodata:
mov r0, _f_rodata
mov r1, _load_addr_rodata
cmp r0, r1
/* if load addr == run addr, no need to copy */
jeq _s3_copy_data
mov r3, _e_rodata
_s3_copy_rodata_loop:
ld.ab r2, [r1, 4]
st.ab r2, [r0, 4]
cmp r0, r3
jlt _s3_copy_rodata_loop
_s3_copy_data:
mov r0, _f_data
mov r1, _load_addr_data
cmp r0, r1
jeq _s3_clear_bss
/* if load addr == run addr, no need to copy */
mov r3, _e_data
_s3_copy_data_loop:
ld.ab r2, [r1, 4]
st.ab r2, [r0, 4]
cmp r0, r3
jlt _s3_copy_data_loop
_s3_clear_bss:
mov r0, _f_bss
mov r1, _e_bss
cmp r0, r1
jge _arc_reset_call_main
mov r2, 0
_s3_clear_bss_loop:
st.ab r2, [r0, 4]
cmp r0, r1
jlt _s3_clear_bss_loop
/* STAGE 3: go to main */
_arc_reset_call_main:
/* \todo add cpp init here */
mov r0, init_software_hook
cmp r0, 0
jlne [r0]
/* board level library init */
/* early init of interrupt and exception */
jl exc_int_init
/* init cache */
jl arc_cache_init
#if defined(__MW__)
jl _init
#elif defined(__GNU__)
jl __do_global_ctors_aux
jl __do_init_array_aux
#endif
jl board_main /* board-level main */
#if defined(__MW__)
jl _fini
#elif defined(__GNU__)
jl __do_global_dtors_aux
#endif
.global _exit_loop
.global _exit_halt
.align 4
_exit_halt:
_exit_loop:
flag 0x1
nop
nop
nop
b _exit_loop
#if defined(__MW__)
.global _init, _fini
.section ".init",text
_init:
.cfa_bf _init
push %blink
.cfa_push {%blink}
.section ".init$999999", text, 1, 2, check_text_align=0
pop %blink
.cfa_pop {%blink}
j [%blink]
.cfa_ef
.section ".fini", text
_fini:
.cfa_bf _fini
push %blink
.cfa_push {%blink}
.section ".fini$999999", text, 1, 2, check_text_align=0
pop %blink
.cfa_pop {%blink}
j [%blink]
.cfa_ef
#endif
/** @endcond */
/** }@*/
bsp/synopsys/embarc/device/designware/gpio/dw_gpio.c 已删除 100644 → 0
浏览文件 @ 54814c42
/* ------------------------------------------
* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2016.05
* \date 2014-07-22
* \author Wayne Ren(Wei.Ren@synopsys.com)
--------------------------------------------- */
/**
* \defgroup DEVICE_DW_GPIO Designware GPIO Driver
* \ingroup DEVICE_DW
* \brief Designware GPIO Driver Implementation
*/
/**
* \file
* \brief designware gpio driver
* \ingroup DEVICE_DW_GPIO
* \brief Designware GPIO driver
*/
#include "inc/embARC_toolchain.h"
#include "inc/embARC_error.h"
#include "inc/arc/arc_exception.h"
#include "device/designware/gpio/dw_gpio.h"
/** check expressions used in DesignWare GPIO driver implementation */
#define DW_GPIO_CHECK_EXP(EXPR, ERROR_CODE) CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit)
#ifndef DISABLE_DEVICE_OBJECT_VALID_CHECK
/** valid check of uart info object */
#define VALID_CHK_GPIO_INFO_OBJECT(gpioinfo_obj_ptr) { \
DW_GPIO_CHECK_EXP((gpioinfo_obj_ptr)!=NULL, E_OBJ); \
DW_GPIO_CHECK_EXP(((gpioinfo_obj_ptr)->gpio_ctrl)!=NULL, E_OBJ); \
}
#endif
/**
* \defgroup DEVICE_DW_GPIO_STATIC DesignWare GPIO Driver Static Functions
* \ingroup DEVICE_DW_GPIO
* \brief Static or inline functions, variables for DesignWare GPIO handle gpio operations,
* only used in this file
* @{
*/
Inline uint32_t dw_gpio_read_ext(DW_GPIO_PORT_PTR port)
{
return port->regs->EXT_PORTS[port->no];
}
Inline uint32_t dw_gpio_read_dir(DW_GPIO_PORT_PTR port)
{
return port->regs->SWPORTS[port->no].DDR;
}
Inline uint32_t dw_gpio_read_dr(DW_GPIO_PORT_PTR port)
{
return port->regs->SWPORTS[port->no].DR;
}
Inline uint32_t dw_gpio_read_mthd(DW_GPIO_PORT_PTR port)
{
return port->regs->INTEN;
}
Inline void dw_gpio_int_enable(DW_GPIO_PORT_PTR port, uint32_t bit_mask)
{
port->regs->INTEN |= bit_mask;
}
Inline void dw_gpio_int_disable(DW_GPIO_PORT_PTR port, uint32_t bit_mask)
{
port->regs->INTEN &= (~bit_mask);
}
Inline void dw_gpio_int_mask(DW_GPIO_PORT_PTR port, uint32_t bit_mask)
{
port->regs->INTMASK |= bit_mask;
}
Inline void dw_gpio_int_unmask(DW_GPIO_PORT_PTR port, uint32_t bit_mask)
{
port->regs->INTMASK &= (~bit_mask);
}
Inline uint32_t dw_gpio_int_read_level(DW_GPIO_PORT_PTR port)
{
return port->regs->INTTYPE_LEVEL;
}
Inline uint32_t dw_gpio_int_read_polarity(DW_GPIO_PORT_PTR port)
{
return port->regs->INT_POLARITY;
}
Inline uint32_t dw_gpio_int_read_debounce(DW_GPIO_PORT_PTR port)
{
return port->regs->DEBOUNCE;
}
Inline uint32_t dw_gpio_int_read_status(DW_GPIO_PORT_PTR port)
{
return port->regs->INTSTATUS;
}
Inline void dw_gpio_int_clear(DW_GPIO_PORT_PTR port, uint32_t bit_mask)
{
port->regs->PORTA_EOI = bit_mask;
}
static void dw_gpio_int_write_level(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t bit_level)
{
uint32_t reg_val;
reg_val = port->regs->INTTYPE_LEVEL;
reg_val &= (~bit_mask);
bit_level &= bit_mask;
reg_val |= bit_level;
port->regs->INTTYPE_LEVEL = reg_val;
}
static void dw_gpio_int_write_polarity(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t bit_polarity)
{
uint32_t reg_val;
reg_val = port->regs->INT_POLARITY;
reg_val &= (~bit_mask);
bit_polarity &= bit_mask;
reg_val |= bit_polarity;
port->regs->INT_POLARITY = reg_val;
}
static void dw_gpio_int_write_debounce(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t bit_debounce)
{
uint32_t reg_val;
reg_val = port->regs->DEBOUNCE;
reg_val &= (~bit_mask);
bit_debounce &= bit_mask;
reg_val |= bit_debounce;
port->regs->DEBOUNCE = reg_val;
}
static void dw_gpio_set_int_cfg(DW_GPIO_PORT_PTR port, DEV_GPIO_INT_CFG *int_cfg)
{
dw_gpio_int_write_level(port, int_cfg->int_bit_mask, int_cfg->int_bit_type);
dw_gpio_int_write_polarity(port, int_cfg->int_bit_mask, int_cfg->int_bit_polarity);
dw_gpio_int_write_debounce(port, int_cfg->int_bit_mask, int_cfg->int_bit_debounce);
}
static void dw_gpio_get_int_cfg(DW_GPIO_PORT_PTR port, DEV_GPIO_INT_CFG *int_cfg)
{
int_cfg->int_bit_type = dw_gpio_int_read_level(port) & int_cfg->int_bit_mask;
int_cfg->int_bit_polarity = dw_gpio_int_read_polarity(port) & int_cfg->int_bit_mask;
int_cfg->int_bit_debounce = dw_gpio_int_read_debounce(port) & int_cfg->int_bit_mask;
}
static void dw_gpio_write_dr(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t val)
{
uint32_t temp_reg;
temp_reg = port->regs->SWPORTS[port->no].DR;
temp_reg &= ~bit_mask;
val &= bit_mask;
temp_reg |= val;
port->regs->SWPORTS[port->no].DR = temp_reg;
}
static void dw_gpio_write_dir(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t val)
{
uint32_t temp_reg;
temp_reg = port->regs->SWPORTS[port->no].DDR;
temp_reg &= ~bit_mask;
val &= bit_mask;
temp_reg |= val;
port->regs->SWPORTS[port->no].DDR = temp_reg;
}
static uint32_t dw_gpio_read_val(DW_GPIO_PORT_PTR port)
{
uint32_t val;
val = dw_gpio_read_ext(port) & (~dw_gpio_read_dir(port));
val |= dw_gpio_read_dr(port) & dw_gpio_read_dir(port);
return val;
}
/** @} end of group DEVICE_DW_GPIO_STATIC */
/* interface for DEV_GPIO */
/** Open designware gpio device with specified io direction configuration */
int32_t dw_gpio_open(DEV_GPIO *gpio_obj, uint32_t dir)
{
int32_t ercd = E_OK;
DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info);
/* START ERROR CHECK */
VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr);
/* END OF ERROR CHECK */
DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl);
DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ);
port_info_ptr->opn_cnt ++;
if (port_info_ptr->opn_cnt > 1) { /* opened before */
if (dir == port_info_ptr->direction) { /* direction is the same */
return E_OK;
} else { /* open with different direction */
return E_OPNED;
}
}
dw_gpio_write_dir(port, port->valid_bit_mask, dir);
if (port->no == DW_GPIO_PORT_A) {
dw_gpio_int_clear(port, DW_GPIO_MASK_ALL);
dw_gpio_int_disable(port, DW_GPIO_MASK_ALL);
dw_gpio_int_unmask(port, DW_GPIO_MASK_ALL);
/* install gpio interrupt handler */
int_handler_install(port->intno, port->int_handler);
int_disable(port->intno);
/** Set int type, int polarity and debounce configuration to default settings of device gpio */
dw_gpio_set_int_cfg(port, (DEV_GPIO_INT_CFG *)(&gpio_int_cfg_default));
port_info_ptr->method = dw_gpio_read_mthd(port);
} else {
port_info_ptr->method = DEV_GPIO_BITS_MTHD_DEFAULT;
}
dw_gpio_write_dr(port, port->valid_bit_mask, 0);
port_info_ptr->direction = dir;
port_info_ptr->extra = NULL;
error_exit:
return ercd;
}
/** Close designware gpio device */
int32_t dw_gpio_close(DEV_GPIO *gpio_obj)
{
int32_t ercd = E_OK;
DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info);
/* START ERROR CHECK */
VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr);
/* END OF ERROR CHECK */
DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl);
DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ);
DW_GPIO_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_OK);
port_info_ptr->opn_cnt --;
if (port_info_ptr->opn_cnt == 0) {
dw_gpio_write_dr(port, port->valid_bit_mask, 0);
dw_gpio_write_dir(port, port->valid_bit_mask, 0);
if (port->no == DW_GPIO_PORT_A) {
dw_gpio_int_clear(port, DW_GPIO_MASK_ALL);
dw_gpio_int_disable(port, DW_GPIO_MASK_ALL);
int_disable(port->intno);
}
port_info_ptr->direction = 0;
port_info_ptr->method = 0;
port_info_ptr->extra = NULL;
} else {
ercd = E_OPNED;
}
error_exit:
return ercd;
}
/** Read designware gpio device value */
int32_t dw_gpio_read(DEV_GPIO *gpio_obj, uint32_t *val, uint32_t mask)
{
int32_t ercd = E_OK;
DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info);
/* START ERROR CHECK */
VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr);
/* END OF ERROR CHECK */
DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl);
DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ);
DW_GPIO_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_CLSED);
DW_GPIO_CHECK_EXP(val!=NULL, E_PAR);
//*val = dw_gpio_read_ext(port) & mask;
*val = dw_gpio_read_val(port) & mask;
error_exit:
return ercd;
}
/** Write designware gpio device value */
int32_t dw_gpio_write(DEV_GPIO *gpio_obj, uint32_t val, uint32_t mask)
{
int32_t ercd = E_OK;
DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info);
/* START ERROR CHECK */
VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr);
/* END OF ERROR CHECK */
DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl);
DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ);
DW_GPIO_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_CLSED);
dw_gpio_write_dr(port, mask, val);
error_exit:
return ercd;
}
/** Control designware gpio device */
int32_t dw_gpio_control(DEV_GPIO *gpio_obj, uint32_t ctrl_cmd, void *param)
{
int32_t ercd = E_OK;
DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info);
/* START ERROR CHECK */
VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr);
/* END OF ERROR CHECK */
DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl);
DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ);
DW_GPIO_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_CLSED);
uint32_t val32; /** to receive unsigned int value */
if (ctrl_cmd == GPIO_CMD_SET_BIT_DIR_INPUT) {
val32 = (uint32_t)param;
dw_gpio_write_dir(port, val32, DW_GPIO_INPUT_ALL);
port_info_ptr->direction = dw_gpio_read_dir(port);
} else if (ctrl_cmd == GPIO_CMD_SET_BIT_DIR_OUTPUT) {
val32 = (uint32_t)param;
dw_gpio_write_dir(port, val32, DW_GPIO_OUTPUT_ALL);
port_info_ptr->direction = dw_gpio_read_dir(port);
} else if (ctrl_cmd == GPIO_CMD_GET_BIT_DIR) {
DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
port_info_ptr->direction = dw_gpio_read_dir(port);
*((int32_t *)param) = port_info_ptr->direction;
} else {
DW_GPIO_CHECK_EXP(port->no == DW_GPIO_PORT_A, E_NOSPT);
/* output pin cannot be used as interrupt */
DEV_GPIO_INT_CFG *gpio_int_cfg;
DEV_GPIO_BIT_ISR *port_bit_isr;
switch (ctrl_cmd) {
case GPIO_CMD_SET_BIT_INT_CFG:
DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
gpio_int_cfg = (DEV_GPIO_INT_CFG *)param;
dw_gpio_set_int_cfg(port, gpio_int_cfg);
break;
case GPIO_CMD_GET_BIT_INT_CFG:
DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
gpio_int_cfg = (DEV_GPIO_INT_CFG *)param;
/** read configuration, each bit stands for different configuration */
dw_gpio_get_int_cfg(port, gpio_int_cfg);
break;
case GPIO_CMD_SET_BIT_ISR:
DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
port_bit_isr = (DEV_GPIO_BIT_ISR *)param;
if (port_bit_isr->int_bit_ofs < port->gpio_bit_isr->int_bit_max_cnt) {
port->gpio_bit_isr->int_bit_handler_ptr[port_bit_isr->int_bit_ofs] = port_bit_isr->int_bit_handler;
} else {
ercd = E_PAR;
}
break;
case GPIO_CMD_GET_BIT_ISR:
DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
port_bit_isr = (DEV_GPIO_BIT_ISR *)param;
if (port_bit_isr->int_bit_ofs < port->gpio_bit_isr->int_bit_max_cnt) {
port_bit_isr->int_bit_handler = port->gpio_bit_isr->int_bit_handler_ptr[port_bit_isr->int_bit_ofs];
} else {
ercd = E_PAR;
}
break;
case GPIO_CMD_ENA_BIT_INT:
val32 = (uint32_t)param;
dw_gpio_int_enable(port, val32);
port_info_ptr->method = dw_gpio_read_mthd(port);
if (port_info_ptr->method) {
int_enable(port->intno);
}
break;
case GPIO_CMD_DIS_BIT_INT:
val32 = (uint32_t)param;
dw_gpio_int_disable(port, val32);
port_info_ptr->method = dw_gpio_read_mthd(port);
if (port_info_ptr->method == 0) {
int_disable(port->intno);
}
break;
case GPIO_CMD_GET_BIT_MTHD:
DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR);
port_info_ptr->method = dw_gpio_read_mthd(port);
*((int32_t *)param) = port_info_ptr->method;
break;
default:
ercd = E_NOSPT;
break;
}
}
error_exit:
return ercd;
}
/** designware gpio interrupt process */
int32_t dw_gpio_isr_handler(DEV_GPIO *gpio_obj, void *ptr)
{
int32_t ercd = E_OK;
DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info);
/* START ERROR CHECK */
VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr);
/* END OF ERROR CHECK */
DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl);
DW_GPIO_CHECK_EXP(port->no == DW_GPIO_PORT_A, E_NOSPT);
uint32_t i, gpio_bit_isr_state;
uint32_t max_int_bit_count = 0;
/** read interrupt status */
gpio_bit_isr_state = dw_gpio_int_read_status(port);
if (port->gpio_bit_isr) {
max_int_bit_count = (port->gpio_bit_isr->int_bit_max_cnt);
} else {
dw_gpio_int_clear(port, gpio_bit_isr_state);
}
for (i=0; i<max_int_bit_count; i++) {
if (gpio_bit_isr_state & (1<<i)) {
/* this bit interrupt enabled */
if (port->gpio_bit_isr->int_bit_handler_ptr[i]) {
port->gpio_bit_isr->int_bit_handler_ptr[i](gpio_obj);
}
dw_gpio_int_clear(port, (1<<i)); /** clear this bit interrupt */
}
}
error_exit:
return ercd;
}
bsp/synopsys/embarc/device/designware/gpio/dw_gpio.h 已删除 100644 → 0
浏览文件 @ 54814c42
/* ------------------------------------------
* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2016.05
* \date 2014-07-22
* \author Wayne Ren(Wei.Ren@synopsys.com)
--------------------------------------------- */
/**
* \file
* \brief designware gpio driver
* \ingroup DEVICE_DW_GPIO
* \brief Designware GPIO driver header file
*/
#ifndef _DW_GPIO_H_
#define _DW_GPIO_H_
#include "device/device_hal/inc/dev_gpio.h"
#include "inc/arc/arc_exception.h"
#define DW_GPIO_PORT_A (0x00)
#define DW_GPIO_PORT_B (0x01)
#define DW_GPIO_PORT_C (0x02)
#define DW_GPIO_PORT_D (0x03)
#define DW_GPIO_INT_ACT_LOW GPIO_INT_ACTIVE_LOW
#define DW_GPIO_INT_ACT_HIGH GPIO_INT_ACTIVE_HIGH
#define DW_GPIO_INT_LEVEL_TRIG GPIO_INT_LEVEL_TRIG
#define DW_GPIO_INT_EDGE_TRIG GPIO_INT_EDGE_TRIG
#define DW_GPIO_INT_NO_DEBOUNCE GPIO_INT_NO_DEBOUNCE
#define DW_GPIO_INT_DEBOUNCE GPIO_INT_DEBOUNCE
#define DW_GPIO_ALL_ZERO (0x0)
#define DW_GPIO_ALL_ONE (0xffffffff)
#define DW_GPIO_MASK_ALL (0xffffffff)
#define DW_GPIO_INPUT_ALL (0x0)
#define DW_GPIO_OUTPUT_ALL (0xffffffff)
/**
* \name DesignWare GPIO Register Structure
* \brief contains definitions of DesignWare GPIO register structure.
* @{
*/
typedef struct port_ctrl {
uint32_t DR;
uint32_t DDR;
uint32_t CTRL;
} PORT_CTRL;
/* DW GPIO PORTS Registers */
typedef volatile struct dw_gpio_reg {
PORT_CTRL SWPORTS[4];
uint32_t INTEN; /*!< (0x30) */
uint32_t INTMASK; /*!< (0x34) */
uint32_t INTTYPE_LEVEL; /*!< (0x38) */
uint32_t INT_POLARITY; /*!< (0x3c) */
uint32_t INTSTATUS; /*!< (0x40) */
uint32_t RAW_INTSTATUS; /*!< (0x44) */
uint32_t DEBOUNCE; /*!< (0x48) */
uint32_t PORTA_EOI; /*!< (0x4c) */
uint32_t EXT_PORTS[4]; /*!< (0x50) -A
(0x54) -B
(0x58) -C
(0x5c) -D */
uint32_t LS_SYNC; /*!< (0x60) */
uint32_t ID_CODE; /*!< (0x64) */
uint32_t RESERVED_3; /*!< (0x68) */
uint32_t VER_ID_CODE; /*!< (0x6c) */
uint32_t CONFIG_REG2; /*!< (0x70) */
uint32_t CONFIG_REG1; /*!< (0x74) */
} DW_GPIO_REG, *DW_GPIO_REG_PTR;
/** @} */
/** interrupt handler for each port bit */
typedef struct dw_gpio_bit_isr {
uint32_t int_bit_max_cnt; /*!< max bit count for each port */
DEV_GPIO_HANDLER *int_bit_handler_ptr; /*!< interrupt handler pointer */
} DW_GPIO_BIT_ISR, * DW_GPIO_BIT_ISR_PTR;
/**
* \brief DesignWare GPIO control structure definition
* \details implement of dev_gpio_info::gpio_ctrl
*/
typedef struct dw_gpio_port {
uint32_t no; /*!< gpio port number */
DW_GPIO_REG_PTR regs; /*!< gpio port register */
uint32_t intno; /*!< gpio interrupt vector number */
uint32_t valid_bit_mask; /*!< valid bit mask of gpio port */
INT_HANDLER int_handler; /*!< gpio interrupt handler */
DW_GPIO_BIT_ISR_PTR gpio_bit_isr; /*!< gpio bit handler struct */
} DW_GPIO_PORT, *DW_GPIO_PORT_PTR;
#ifdef __cplusplus
extern "C" {
#endif
/**
* \name DesignWare GPIO Function Declaration
* \brief contains declarations of designware gpio functions.
* \details This are only used in gpio object implementation source file
* @{
*/
extern int32_t dw_gpio_open(DEV_GPIO *gpio_obj, uint32_t dir);
extern int32_t dw_gpio_close(DEV_GPIO *gpio_obj);
extern int32_t dw_gpio_read(DEV_GPIO *gpio_obj, uint32_t *val, uint32_t mask);
extern int32_t dw_gpio_write(DEV_GPIO *gpio_obj, uint32_t val, uint32_t mask);
extern int32_t dw_gpio_control(DEV_GPIO *gpio_obj, uint32_t ctrl_cmd, void *param);
extern int32_t dw_gpio_isr_handler(DEV_GPIO *gpio_obj, void *ptr);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* _DW_GPIO_H_ */
bsp/synopsys/embarc/device/designware/iic/dw_iic.h 已删除 100644 → 0
浏览文件 @ 54814c42
/* ------------------------------------------
* Copyright (c) 2017, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2017.03
* \date 2014-06-30
* \author Huaqi Fang(Huaqi.Fang@synopsys.com)
--------------------------------------------- */
/**
* \file
* \brief designware iic driver header file
* \ingroup DEVICE_DW_IIC
*/
#ifndef _DW_IIC_H_
#define _DW_IIC_H_
#include "device/device_hal/inc/dev_iic.h"
#include "inc/arc/arc_exception.h"
/**
* If this header file is included,
* will indicate that this designware iic device
* is used
*/
#define DEVICE_USE_DESIGNWARE_IIC
/**
* \defgroup DEVICE_DW_IIC_INFO DesignWare IIC Related Information
* \ingroup DEVICE_DW_IIC
* \brief Defines some macros of DesignWare IIC need.
* \details macros like, iic number
* @{
*/
#define DW_IIC_MASTER_SUPPORTED (0x1) /*!< Support Designware IIC Master Mode */
#define DW_IIC_SLAVE_SUPPORTED (0x2) /*!< Support Designware IIC Slave Mode */
/*!< Support Designware IIC Both Master and Slave Mode */
#define DW_IIC_BOTH_SUPPORTED (DW_IIC_MASTER_SUPPORTED|DW_IIC_SLAVE_SUPPORTED)
/** @} */
/**
* \defgroup DEVICE_DW_IIC_REGSTRUCT DesignWare IIC Register Structure
* \ingroup DEVICE_DW_IIC
* \brief contains definitions of DesignWare IIC register structure.
* \details detailed description of DesignWare IIC register information
* @{
*/
/**
* \brief DesignWare IIC register structure
* \details Detailed struct description of DesignWare IIC
* block register information, implementation of dev_iic_info::iic_regs
*/
typedef volatile struct dw_iic_reg {
uint32_t IC_CON; /*!< (0x00) : IIC control */
uint32_t IC_TAR; /*!< (0x04) : IIC target address */
uint32_t IC_SAR; /*!< (0x08) : IIC slave address */
uint32_t IC_HS_MADDR; /*!< (0x0c) : IIC HS Master Mode Code address */
uint32_t IC_DATA_CMD; /*!< (0x10) : IIC Rx/Tx Data Buffer and Command */
uint32_t IC_SS_SCL_HCNT; /*!< (0x14) : Standard Speed IIC clock SCL High Count */
uint32_t IC_SS_SCL_LCNT; /*!< (0x18) : Standard Speed IIC clock SCL Low Count */
uint32_t IC_FS_SCL_HCNT; /*!< (0x1c) : Fast Speed IIC clock SCL Low Count */
uint32_t IC_FS_SCL_LCNT; /*!< (0x20) : Fast Speed IIC clock SCL Low Count */
uint32_t IC_HS_SCL_HCNT; /*!< (0x24) : High Speed IIC clock SCL Low Count */
uint32_t IC_HS_SCL_LCNT; /*!< (0x28) : High Speed IIC clock SCL Low Count */
uint32_t IC_INTR_STAT; /*!< (0x2c) : IIC Interrupt Status */
uint32_t IC_INTR_MASK; /*!< (0x30) : IIC Interrupt Mask */
uint32_t IC_RAW_INTR_STAT; /*!< (0x34) : IIC Raw Interrupt Status */
uint32_t IC_RX_TL; /*!< (0x38) : IIC Receive FIFO Threshold */
uint32_t IC_TX_TL; /*!< (0x3c) : IIC Transmit FIFO Threshold */
uint32_t IC_CLR_INTR; /*!< (0x40) : Clear combined and Individual Interrupts */
uint32_t IC_CLR_RX_UNDER; /*!< (0x44) : Clear RX_UNDER Interrupt */
uint32_t IC_CLR_RX_OVER; /*!< (0x48) : Clear RX_OVER Interrupt */
uint32_t IC_CLR_TX_OVER; /*!< (0x4c) : Clear TX_OVER Interrupt */
uint32_t IC_CLR_RD_REQ; /*!< (0x50) : Clear RQ_REQ Interrupt */
uint32_t IC_CLR_TX_ABRT; /*!< (0x54) : Clear TX_ABRT Interrupt */
uint32_t IC_CLR_RX_DONE; /*!< (0x58) : Clear RX_DONE Interrupt */
uint32_t IC_CLR_ACTIVITY; /*!< (0x5c) : Clear ACTIVITY Interrupt */
uint32_t IC_CLR_STOP_DET; /*!< (0x60) : Clear STOP_DET Interrupt */
uint32_t IC_CLR_START_DET; /*!< (0x64) : Clear START_DET Interrupt */
uint32_t IC_CLR_GEN_CALL; /*!< (0x68) : Clear GEN_CALL Interrupt */
uint32_t IC_ENABLE; /*!< (0x6c) : IIC Enable */
uint32_t IC_STATUS; /*!< (0x70) : IIC Status */
uint32_t IC_TXFLR; /*!< (0x74) : Transmit FIFO Level Register */
uint32_t IC_RXFLR; /*!< (0x78) : Receive FIFO Level Register */
uint32_t IC_SDA_HOLD; /*!< (0x7c) : SDA Hold Time Length Reg */
uint32_t IC_TX_ABRT_SOURCE; /*!< (0x80) : IIC Transmit Abort Status Reg */
uint32_t IC_SLV_DATA_NACK_ONLY; /*!< (0x84) : Generate SLV_DATA_NACK Register */
uint32_t IC_DMA_CR; /*!< (0x88) : DMA Control Register */
uint32_t IC_DMA_TDLR; /*!< (0x8c) : DMA Transmit Data Level */
uint32_t IC_DMA_RDLR; /*!< (0x90) : DMA Receive Data Level */
uint32_t IC_SDA_SETUP; /*!< (0x94) : SDA Setup Register */
uint32_t IC_ACK_GENERAL_CALL; /*!< (0x98) : ACK General Call Register */
uint32_t IC_ENABLE_STATUS; /*!< (0x9c) : Enable Status Register */
uint32_t IC_FS_SPKLEN; /*!< (0xa0) : ISS and FS spike suppression limit */
uint32_t IC_HS_SPKLEN; /*!< (0xa4) : HS spike suppression limit */
uint32_t RESERVED[19]; /*!< (0xa8) : Reserved */
uint32_t IC_COMP_PARAM_1; /*!< (0xf4) : Component Parameter Register */
uint32_t IC_COMP_VERSION; /*!< (0xf8) : Component Version ID Reg */
uint32_t IC_COMP_TYPE; /*!< (0xfc) : Component Type Reg */
} DW_IIC_REG, *DW_IIC_REG_PTR;
/** @} */
/** Spike Suppression Limit Configurations */
typedef struct dw_iic_spklen {
uint32_t fs_spklen; /*!< value for IC_FS_SPKLEN, Tsp for fast mode is 50ns */
uint32_t hs_spklen; /*!< value for IC_HS_SPKLEN, Tsp for high-speed mode is 10ns */
} DW_IIC_SPKLEN, *DW_IIC_SPKLEN_PTR;
/** IIC Clock SCL High and Low Count Configurations for Different Speed */
typedef struct dw_iic_scl_cnt {
uint32_t ss_scl_hcnt; /*!< value for IC_SS_SCL_HCNT */
uint32_t ss_scl_lcnt; /*!< value for IC_SS_SCL_LCNT */
uint32_t fs_scl_hcnt; /*!< value for IC_FS_SCL_HCNT */
uint32_t fs_scl_lcnt; /*!< value for IC_FS_SCL_LCNT */
uint32_t hs_scl_hcnt; /*!< value for IC_HS_SCL_HCNT */
uint32_t hs_scl_lcnt; /*!< value for IC_HS_SCL_LCNT */
} DW_IIC_SCL_CNT, *DW_IIC_SCL_CNT_PTR;
#define DW_IIC_GINT_DISABLED (0) /*!< designware interrupt disabled for control iic irq/fiq */
#define DW_IIC_GINT_ENABLE (1<<0) /*!< designware interrupt enabled for control iic irq/fiq */
#define DW_IIC_TXINT_ENABLE (1<<1) /*!< designware interrupt enabled for control transmit process */
#define DW_IIC_RXINT_ENABLE (1<<2) /*!< designware interrupt enabled for control transmit process */
typedef struct dw_iic_buffer {
DEV_BUFFER *buf;
uint32_t ofs;
uint32_t len;
} DW_IIC_BUFFER, *DW_IIC_BUFFER_PTR;
/**
* \brief DesignWare IIC control structure definition
* \details implement of dev_iic_info::iic_ctrl
*/
typedef struct dw_iic_ctrl {
DW_IIC_REG *dw_iic_regs; /*!< iic device registers */
/* Variables which should be set during object implementation */
uint32_t support_modes; /*!< supported iic modes */
uint32_t tx_fifo_len; /*!< transmit fifo length */
uint32_t rx_fifo_len; /*!< receive fifo length */
uint32_t iic_master_code; /*!< value for IC_HS_MADDR */
uint32_t retry_cnt; /*!< retry count for TX or RX */
uint32_t intno; /*!< iic interrupt vector number */
INT_HANDLER dw_iic_int_handler; /*!< iic interrupt handler */
DW_IIC_SPKLEN iic_spklen; /*!< iic spike suppression length settings */
DW_IIC_SCL_CNT iic_scl_cnt; /*!< iic scl count settings */
/* Variables which always change during iic operation */
uint32_t int_status; /*!< iic interrupt status */
uint32_t iic_tx_over; /*!< iic tx overflow count */
uint32_t iic_rx_over; /*!< iic rx overflow count */
DW_IIC_BUFFER dw_iic_rxbuf; /*!< iic read buffer for receive data */
} DW_IIC_CTRL, *DW_IIC_CTRL_PTR;
/*!< One possible value for \ref dw_iic_ctrl::retry_cnt */
#define DW_IIC_MAX_RETRY_COUNT (100000)
#if DW_IIC_USE_IC_CLK_MHZ == 100 /*!< 100MHz */
/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
static const DW_IIC_SPKLEN dw_iic_spklen_const = {5, 1};
/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
#if DW_IIC_USE_HS_BUS_LOADING_100PF
static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x0190, 0x01d6, 0x003c, 0x0082, 0x6, 0x10};
#else
static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x0190, 0x01d6, 0x003c, 0x0082, 0xc, 0x20};
#endif
#elif DW_IIC_USE_IC_CLK_MHZ == 50 /* 50MHz */
/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
static const DW_IIC_SPKLEN dw_iic_spklen_const = {5, 1};
/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
#if DW_IIC_USE_HS_BUS_LOADING_100PF
static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x00c8, 0x00eb, 0x001e, 0x0041, 0x6, 0x8};
#else
static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x00c8, 0x00eb, 0x001e, 0x0041, 0x6, 0x10};
#endif
#else /* Default 100MHz */
/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
static const DW_IIC_SPKLEN dw_iic_spklen_const = {5, 1};
/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */
#if DW_IIC_USE_HS_BUS_LOADING_100PF
static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x0190, 0x01d6, 0x003c, 0x0082, 0x6, 0x10};
#else
static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x0190, 0x01d6, 0x003c, 0x0082, 0xc, 0x20};
#endif
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \defgroup DEVICE_DW_IIC_FUNCDLR DesignWare IIC Function Declaration
* \ingroup DEVICE_DW_IIC
* \brief Contains declarations of designware iic functions.
* \details This are only used in iic object implementation source file
* @{
*/
extern int32_t dw_iic_open (DEV_IIC *iic_obj, uint32_t mode, uint32_t param);
extern int32_t dw_iic_close (DEV_IIC *iic_obj);
extern int32_t dw_iic_control (DEV_IIC *iic_obj, uint32_t ctrl_cmd, void *param);
extern int32_t dw_iic_write (DEV_IIC *iic_obj, const void *data, uint32_t len);
extern int32_t dw_iic_read (DEV_IIC *iic_obj, void *data, uint32_t len);
extern void dw_iic_isr(DEV_IIC *iic_obj, void *ptr);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* _DW_IIC_H_ */
bsp/synopsys/embarc/device/designware/iic/dw_iic_hal.h 已删除 100644 → 0
浏览文件 @ 54814c42
/* ------------------------------------------
* Copyright (c) 2017, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2017.03
* \date 2014-06-30
* \author Huaqi Fang(Huaqi.Fang@synopsys.com)
--------------------------------------------- */
/**
* \file
* \ingroup DEVICE_DW_IIC
* \brief DesignWare IIC driver hardware description related header file
* \details detailed hardware related definitions of DesignWare IIC driver
*/
#ifndef _DEVICE_DW_IIC_HAL_H_
#define _DEVICE_DW_IIC_HAL_H_
#include "device/designware/iic/dw_iic_hal_cfg.h"
/** Enable Designware IIC */
#define DW_IIC_ENABLE (1)
/** Disable Designware IIC */
#define DW_IIC_DISABLE (0)
/** Stop Condition issue after this byte */
#define IC_DATA_CMD_STOP (1 << 9)
/** Restart Condition issue after this byte */
#define IC_DATA_CMD_RESTART (1 << 10)
/** No Restart or stop condition after this byte */
#define IC_DATA_CMD_NONE (0)
/** Perform a write request */
#define IC_DATA_CMD_WRITE_REQ (0)
/** Perform a read request */
#define IC_DATA_CMD_READ_REQ (1 << 8)
/** Fields of IC_CON register */
/* DW_APB I2C IP Config Dependencies. */
#if DW_IIC_ALLOW_RESTART
#define IC_CON_RESTART_EN (1 << 5)
#else
#define IC_CON_RESTART_EN (0x00)
#endif
/* Master Addressing Mode Config */
#if DW_IIC_MST_10_BIT_ADDR_SUPPORT
#define MST_10_BIT_ADDR_MODE (1 << 4)
#define IC_10BITADDR_MASTER (1 << 12)
#else
#define MST_10_BIT_ADDR_MODE (0x00)
#define IC_10BITADDR_MASTER (0x00)
#endif
/* Slave Addressing Mode Config */
#if DW_IIC_SLV_10_BIT_ADDR_SUPPORT
#define SLV_10_BIT_ADDR_MODE (1 << 3)
#else
#define SLV_10_BIT_ADDR_MODE (0x00)
#endif
#if DW_IIC_SPECIAL_START_BYTE
#define IC_TAR_SPECIAL (1 << 11)
#define IC_TAR_GC_OR_START (1 << 10)
#else
#define IC_TAR_SPECIAL (0x00)
#define IC_TAR_GC_OR_START (0x00)
#endif
/** 7bit IIC address mask for target address register */
#define IC_TAR_7BIT_ADDR_MASK (0x7F)
/** 7bit IIC address mask for slave address register */
#define IC_SAR_7BIT_ADDR_MASK (0x7F)
/** 10bit IIC address mask for target address register */
#define IC_TAR_10BIT_ADDR_MASK (0x3FF)
/** 10bit IIC address mask for slave address register */
#define IC_SAR_10BIT_ADDR_MASK (0x3FF)
/** Speed modes of IC_CON */
#define IC_CON_SPEED_MASK (0x6)
#define IC_CON_SPEED_STANDARD (0x2)
#define IC_CON_SPEED_FAST (0x4)
#define IC_CON_SPEED_HIGH (0x6)
/** Working mode of IC_CON */
#define IC_CON_MST_SLV_MODE_MASK (0x41)
#define IC_CON_ENA_MASTER_MODE (0x41)
#define IC_CON_ENA_SLAVE_MODE (0)
/* IIC interrupt control */
#define IC_INT_DISABLE_ALL (0x0)
#define IC_INT_ENABLE_ALL (0x7FF)
/* Interrupt Register Fields */
#define IC_INTR_STAT_GEN_CALL (1 << 11)
#define IC_INTR_STAT_START_DET (1 << 10)
#define IC_INTR_STAT_STOP_DET (1 << 9)
#define IC_INTR_STAT_ACTIVITY (1 << 8)
#define IC_INTR_STAT_RX_DONE (1 << 7)
#define IC_INTR_STAT_TX_ABRT (1 << 6)
#define IC_INTR_STAT_RD_REQ (1 << 5)
#define IC_INTR_STAT_TX_EMPTY (1 << 4)
#define IC_INTR_STAT_TX_OVER (1 << 3)
#define IC_INTR_STAT_RX_FULL (1 << 2)
#define IC_INTR_STAT_RX_OVER (1 << 1)
#define IC_INTR_STAT_RX_UNDER (1 << 0)
/* Interrupt enable mask as master */
#define IC_INT_MST_TX_ENABLE (IC_INTR_STAT_TX_EMPTY|IC_INTR_STAT_TX_OVER|IC_INTR_STAT_TX_ABRT)
#define IC_INT_MST_RX_ENABLE (IC_INTR_STAT_TX_EMPTY|IC_INTR_STAT_RX_FULL|IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER|IC_INTR_STAT_TX_ABRT)
/* Interrupt enable mask as master */
#define IC_INT_SLV_COMMON_ENABLE (IC_INTR_STAT_START_DET|IC_INTR_STAT_STOP_DET)
#define IC_INT_SLV_TX_ENABLE (IC_INTR_STAT_RD_REQ|IC_INTR_STAT_TX_ABRT)
#define IC_INT_SLV_RX_ENABLE (IC_INTR_STAT_RX_FULL|IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER)
/* IC_ENABLE_STATUS Bits */
#define IC_ENABLE_STATUS_IC_EN (1 << 0)
#define IC_ENABLE_STATUS_SLV_DIS (1 << 1)
#define IC_ENABLE_STATUS_SLV_RX_LOST (1 << 2)
/* IIC TX & RX threshold settings */
#define IIC_TX_THRESHOLD (0)
#define IIC_RX_THRESHOLD (0)
/* DW_APB IIC (DW_IC_STATUS) Status Register Fields. */
#define IC_STATUS_ACTIVITY (0x01)
#define IC_STATUS_TFNF (0x02) /* (1 << 1) */
#define IC_STATUS_TFE (0x04) /* (1 << 2) */
#define IC_STATUS_RFNE (0x08) /* (1 << 3) */
#define IC_STATUS_RFF (0x10) /* (1 << 4) */
#define IC_STATUS_MASTER_ACT (0x20) /* (1 << 5) */
#define IC_STATUS_SLAVE_ACT (0x40) /* (1 << 6) */
/* IC_TX_ABRT_SOURCE Register Bit Fields */
#define IC_TX_ABRT_7B_ADDR_NOACK (1 << 0)
#define IC_TX_ABRT_10ADDR1_NOACK (1 << 1)
#define IC_TX_ABRT_10ADDR2_NOACK (1 << 2)
#define IC_TX_ABRT_TXDATA_NOACK (1 << 3)
#define IC_TX_ABRT_GCALL_NOACK (1 << 4)
#define IC_TX_ABRT_GCALL_READ (1 << 5)
#define IC_TX_ABRT_HS_ACKDET (1 << 6)
#define IC_TX_ABRT_SBYTE_ACKDET (1 << 7)
#define IC_TX_ABRT_HS_NORSTRT (1 << 8)
#define IC_TX_ABRT_SBYTE_NORSTRT (1 << 9)
#define IC_TX_ABRT_10B_RD_NORSTRT (1 << 10)
#define IC_TX_ABRT_MASTER_DIS (1 << 11)
#define IC_TX_ABRT_ARB_LOST (1 << 12)
#define IC_TX_ABRT_SLVFLUSH_TXFIFO (1 << 13)
#define IC_TX_ABRT_SLV_ARBLOST (1 << 14)
#define IC_TX_ABRT_SLVRD_INTX (1 << 15)
/* Combined bits for iic abort source as master */
#define IIC_MST_ABRT_ADDR_NOACK (IC_TX_ABRT_7B_ADDR_NOACK|IC_TX_ABRT_10ADDR1_NOACK|IC_TX_ABRT_10ADDR1_NOACK)
#define IIC_MST_ABRT_LOST_BUS (IC_TX_ABRT_ARB_LOST)
#define IIC_MST_ABRT_DATA_NOACK (IC_TX_ABRT_TXDATA_NOACK)
/* Combined bits for iic abort source as slave */
#define IIC_SLV_ABRT_LOST_BUS (IC_TX_ABRT_ARB_LOST|IC_TX_ABRT_SLV_ARBLOST)
/** @} */
#endif /* _DEVICE_DW_IIC_HAL_H_ */
bsp/synopsys/embarc/device/designware/iic/dw_iic_hal_cfg.h 已删除 100644 → 0
浏览文件 @ 54814c42
/* ------------------------------------------
* Copyright (c) 2017, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2017.03
* \date 2014-07-01
* \author Huaqi Fang(Huaqi.Fang@synopsys.com)
--------------------------------------------- */
/**
* \file
* \ingroup DEVICE_DW_IIC
* \brief DesignWare IIC driver hardware description
* related header file configuration file
* \details configuration file to enable or disable some function of iic
*/
#ifndef _DEVICE_DW_IIC_HAL_CFG_H_
#define _DEVICE_DW_IIC_HAL_CFG_H_
#ifndef DW_IIC_ALLOW_RESTART
#define DW_IIC_ALLOW_RESTART (1) /*!< allow restart configuration */
#endif
#ifdef DW_IIC_SPECIAL_START_BYTE
#define DW_IIC_SPECIAL_START_BYTE (0) /*!< SPECIAL bit enable in IC_TAR */
#endif
#ifndef DW_IIC_MST_10_BIT_ADDR_SUPPORT
#define DW_IIC_MST_10_BIT_ADDR_SUPPORT (1) /*!< enable 10-bit address mode */
#endif
#ifdef DW_IIC_SLV_10_BIT_ADDR_SUPPORT
#define DW_IIC_SLV_10_BIT_ADDR_SUPPORT (1) /*!< slave 10-bit addressing mode */
#endif
#ifndef DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT
#define DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT (0) /*!< Dynamic target address update support */
#endif
#ifndef DW_IIC_DISABLE_MAX_T_POLL_CNT
#define DW_IIC_DISABLE_MAX_T_POLL_CNT (1250) /*!< Timeout count, approximate to be 25us in 50MHz CPU @ Standard mode */
#endif
#ifndef DW_IIC_CALC_FIFO_LEN_ENABLE
#define DW_IIC_CALC_FIFO_LEN_ENABLE (1) /*!< Default enable calculate fifo length */
#endif
#ifndef DW_IIC_USE_IC_CLK_MHZ
#define DW_IIC_USE_IC_CLK_MHZ (50) /*!< Default use 50MHz IC_CLK */
#endif
#ifndef DW_IIC_USE_HS_BUS_LOADING_100PF
#define DW_IIC_USE_HS_BUS_LOADING_100PF (1) /*!< Use bus loading 100pf */
#endif
#endif /* _DEVICE_DW_IIC_HAL_CFG_H_ */
bsp/synopsys/embarc/device/designware/spi/dw_spi.h 已删除 100644 → 0
浏览文件 @ 54814c42
/* ------------------------------------------
* Copyright (c) 2017, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2017.03
* \date 2014-06-25
* \author Huaqi Fang(Huaqi.Fang@synopsys.com)
--------------------------------------------- */
/**
* \file
* \brief DesignWare SPI driver header file
* \ingroup DEVICE_DW_SPI
*/
#ifndef _DEVICE_DW_SPI_H_
#define _DEVICE_DW_SPI_H_
#include "device/device_hal/inc/dev_spi.h"
/**
* if this header file is included,
* will indicate that this designware spi device
* is used
*/
#define DEVICE_USE_DESIGNWARE_SPI
#define DW_SPI_IN_FREE (0) /*!< Currently not in spi transfer */
#define DW_SPI_IN_XFER (DEV_IN_TX|DEV_IN_RX|DEV_IN_XFER) /*!< Currently in spi transfer */
#define DW_SPI_IN_TX (DEV_IN_TX|DEV_IN_XFER) /*!< Currently in spi tx */
#define DW_SPI_IN_RX (DEV_IN_RX|DEV_IN_XFER) /*!< Currently in spi rx */
#define DW_SPI_GINT_DISABLED (0) /*!< designware interrupt disabled for control iic irq/fiq */
#define DW_SPI_GINT_ENABLE (1<<0) /*!< designware interrupt enabled for control iic irq/fiq */
#define DW_SPI_MASTER_SUPPORTED (0x1) /*!< Support Designware SPI Master Mode */
#define DW_SPI_SLAVE_SUPPORTED (0x2) /*!< Support Designware SPI Slave Mode */
/*!< Support Designware SPI Both Master and Slave Mode */
#define DW_SPI_BOTH_SUPPORTED (DW_SPI_MASTER_SUPPORTED|DW_SPI_SLAVE_SUPPORTED)
/**
* \defgroup DEVICE_DW_SPI_REGSTRUCT DesignWare SPI Register Structure
* \ingroup DEVICE_DW_SPI
* \brief contains definitions of DesignWare SPI register structure.
* \details detailed description of DesignWare SPI register information
* @{
*/
/**
* \brief DesignWare SPI register structure
* \details Detailed struct description of DesignWare SPI
* block register information, implementation of dev_spi_info::spi_regs
*/
typedef volatile struct dw_spi_reg
{
/*!< Control Register */
/*!< SPI Control Register 0 (0x0) */
uint32_t CTRLR0;
/*!< SPI Control Register 1 (0x4) */
uint32_t CTRLR1;
/*!< Enable Register */
/*!< SPI Enable Register (0x8) */
uint32_t SSIENR;
/*!< SPI Microwire Control Register (0xC) */
uint32_t MWCR;
/*!< SPI Slave Enable Register (0x10) */
uint32_t SER;
/*!< SPI Baud Rate Select Register (0x14) */
uint32_t BAUDR;
/*!< TX and RX FIFO Control Register */
/*!< SPI Transmit FIFO Threshold Level Register (0x18) */
uint32_t TXFTLR;
/*!< SPI Receive FIFO Threshold Level Register (0x1C) */
uint32_t RXFTLR;
/*!< SPI Transmit FIFO Level Register (0x20) */
uint32_t TXFLR;
/*!< SPI Receive FIFO Level Register (0x24) */
uint32_t RXFLR;
/*!< SPI Status Register (0x28) */
uint32_t SR;
/*!< Interrupt Enable/Disable/Control Registers */
/*!< SPI Interrupt Mask Register (0x2C) */
uint32_t IMR;
/*!< SPI Interrupt Status Register (0x30) */
uint32_t ISR;
/*!< SPI Raw Interrupt Status Register (0x34) */
uint32_t RISR;
/*!< SPI Transmit FIFO Overflow Interrupt Clear Register (0x38) */
uint32_t TXOICR;
/*!< SPI Receive FIFO Overflow Interrupt Clear Register (0x3C) */
uint32_t RXOICR;
/*!< SPI Receive FIFO Underflow Interrupt Clear Register (0x40) */
uint32_t RXUICR;
/*!< SPI Multi-Master Interrupt Clear Register (0x44) */
uint32_t MSTICR;
/*!< SPI Interrupt Clear Register (0x48) */
uint32_t ICR;
/*!< DMA Control Register (0x4C) */
uint32_t DMACR;
/*!< DMA Transmit Data Level (0x50) */
uint32_t DMATDLR;
/*!< DMA Receive Data Level (0x54) */
uint32_t DMARDLR;
/*!< SPI Identification Register (0x58) */
uint32_t IDR;
/*!< SPI CoreKit ID Register (Value after Reset : 0x3332322A) (0x5C) */
uint32_t SSI_VER_ID;
/*!< Data Register */
/*!< SPI DATA Register for both Read and Write (0x60) */
uint32_t DATAREG;
} DW_SPI_REG, *DW_SPI_REG_PTR;
/** @} */
/** Designware SPI Message Transfer */
typedef struct dw_spi_transfer {
uint32_t xfer_len;
uint32_t tx_idx;
uint32_t rx_idx;
uint32_t nbytes;
DEV_SPI_TRANSFER *tx_xfer;
DEV_SPI_TRANSFER *rx_xfer;
} DW_SPI_TRANSFER, *DW_SPI_TRANSFER_PTR;
/**
* \brief DesignWare SPI control structure definition
* \details implement of dev_spi_info::dev_spi_info
*/
typedef struct dw_spi_ctrl {
DW_SPI_REG *dw_spi_regs; /*!< spi register */
/* Variables which should be set during object implementation */
uint32_t support_modes; /*!< supported spi modes */
uint32_t intno; /*!< interrupt no */
uint32_t dw_apb_bus_freq; /*!< spi ip apb bus frequency */
uint32_t tx_fifo_len; /*!< transmit fifo length */
uint32_t rx_fifo_len; /*!< receive fifo length */
INT_HANDLER dw_spi_int_handler; /*!< spi interrupt handler */
/* Variables which always change during iic operation */
uint32_t int_status; /*!< iic interrupt status */
DW_SPI_TRANSFER dw_xfer; /*!< designware spi transfer */
} DW_SPI_CTRL, *DW_SPI_CTRL_PTR;
#ifdef __cplusplus
extern "C" {
#endif
/**
* \defgroup DEVICE_DW_SPI_FUNCDLR DesignWare SPI Function Declaration
* \ingroup DEVICE_DW_SPI
* \brief contains declarations of designware spi functions.
* \details This are only used in \ref dw_spi_obj.c
* @{
*/
extern int32_t dw_spi_open (DEV_SPI *spi_obj, uint32_t mode, uint32_t param);
extern int32_t dw_spi_close (DEV_SPI *spi_obj);
extern int32_t dw_spi_control (DEV_SPI *spi_obj, uint32_t ctrl_cmd, void *param);
extern int32_t dw_spi_write (DEV_SPI *spi_obj, const void *data, uint32_t len);
extern int32_t dw_spi_read (DEV_SPI *spi_obj, void *data, uint32_t len);
extern void dw_spi_isr(DEV_SPI *spi_obj, void *ptr);
/** @} */
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* _DEVICE_DW_SPI_H_ */
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/* ------------------------------------------
* Copyright (c) 2017, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2017.03
* \date 2015-09-09
* \author Huaqi Fang(Huaqi.Fang@synopsys.com)
--------------------------------------------- */
/**
* \file
* \ingroup DEVICE_DW_SPI
* \brief DesignWare SPI driver hardware description
* related header file configuration file
* \details configuration file to enable or disable some function of spi
*/
#ifndef _DEVICE_DW_SPI_HAL_CFG_H_
#define _DEVICE_DW_SPI_HAL_CFG_H_
#ifndef DW_SPI_CALC_FIFO_LEN_ENABLE
#define DW_SPI_CALC_FIFO_LEN_ENABLE (1) /*!< Defaultly enable calculate fifo length */
#endif
#ifndef DW_SPI_MAX_FIFO_LENGTH
#define DW_SPI_MAX_FIFO_LENGTH (256) /*!< Max FIFO depth for designware SPI device */
#endif
#ifndef DW_SPI_MIN_FIFO_LENGTH
#define DW_SPI_MIN_FIFO_LENGTH (2) /*!< Min FIFO depth for designware SPI device */
#endif
#endif /* _DEVICE_DW_SPI_HAL_CFG_H_ */
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Warn : deprecated option: -p/--pipe. Use '-c "gdb_port pipe; log_output openocd.log"' instead.
adapter speed: 5000 kHz
Error: libusb_open() failed with LIBUSB_ERROR_NOT_SUPPORTED
Info : clock speed 5000 kHz
Info : JTAG tap: arc-em.cpu tap/device found: 0x200044b1 (mfg: 0x258, part: 0x0004, ver: 0x2)
Info : JTAG tap: arc-em.cpu tap/device found: 0x200044b1 (mfg: 0x258, part: 0x0004, ver: 0x2)
target state: halted
Info : accepting 'gdb' connection from pipe
Info : dropped 'gdb' connection
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libcpu/arc/em/SConscript
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......@@ -8,9 +8,7 @@ cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd]
if rtconfig.PLATFORM == 'gcc':
src += Glob('*_gcc.S')
src += Glob('*.S')
group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
......
libcpu/arc/em/cpuport.c
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