[bsp]update x1000 bsp driver

bsp/x1000/Kconfig

+mainmenu "RT-Thread Configuration"
+
+config $BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config $RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "E:/rt-thread"
+    
+# you can change the RTT_ROOT default "../.." to your rtthread_root,
+# example : default "F:/git_repositories/rt-thread"
+
+config $PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/KConfig"
+source "$PKGS_DIR/KConfig"
+source "$BSP_DIR/drivers/Kconfig"
+

bsp/x1000/SConstruct

 import os
 import sys
 import rtconfig
-from rtconfig import RTT_ROOT
 
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.join(Dir('#').get_abspath(), 'rt-thread')
+    
 sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
 from building import *
 
@@ -11,16 +15,19 @@ TARGET = 'rtthread-x1000.' + rtconfig.TARGET_EXT
 env = Environment(tools = ['mingw'],
     AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
     CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
-    CXX = rtconfig.CC, CXXFLAGS = rtconfig.CXXFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
     AR = rtconfig.AR, ARFLAGS = '-rc',
     LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
 env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
 
+# add --start-group and --end-group for GNU GCC
+env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group'
+
 Export('RTT_ROOT')
 Export('rtconfig')
 
 # prepare building environment
-objs = PrepareBuilding(env, RTT_ROOT)
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
 
 # make a building
 DoBuilding(TARGET, objs)

bsp/x1000/applications/SConscript

 from building import *
 
 cwd = GetCurrentDir()
-src = Glob('*.c')
+src = Glob('*.c') + Glob('*.cpp')
 
 CPPPATH = [cwd, str(Dir('#'))]
 
-if not GetDepend("RT_USING_DFS_ROMFS"):
-    SrcRemove(src, "romfs.c")
-
 group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
 
 Return('group')

bsp/x1000/applications/blink.c

+/*
+ * File      : blink.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-11-8      Tangyuxin    first version
+ */
+
+#include <rtthread.h>
+
+#include <board.h>
+#include <drv_gpio.h>
+
+void blink_task(void* param)
+{
+    rt_uint8_t cnt = 0;
+    
+    while(1)
+    {
+        rt_thread_delay(RT_TICK_PER_SECOND / 4);
+
+        if(cnt & 0x01)
+            gpio_set_value(BLINK_LED0_PORT,BLINK_LED0_PIN,0);
+        else
+            gpio_set_value(BLINK_LED0_PORT,BLINK_LED0_PIN,1);
+
+        if(cnt & 0x02)
+            gpio_set_value(BLINK_LED1_PORT,BLINK_LED1_PIN,0);
+        else
+            gpio_set_value(BLINK_LED1_PORT,BLINK_LED1_PIN,1);
+
+        if(cnt & 0x04)
+            gpio_set_value(BLINK_LED2_PORT,BLINK_LED2_PIN,0);
+        else
+            gpio_set_value(BLINK_LED2_PORT,BLINK_LED2_PIN,1);
+
+        if(cnt & 0x08)
+            gpio_set_value(BLINK_LED3_PORT,BLINK_LED3_PIN,0);
+        else
+            gpio_set_value(BLINK_LED3_PORT,BLINK_LED3_PIN,1);
+
+        cnt ++;
+    }
+}
+
+int blink_init(void)
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("blink",
+                           blink_task, RT_NULL,
+                           512,
+                           RT_THREAD_PRIORITY_MAX - 2,
+                           10);
+    if (tid != RT_NULL)
+        rt_thread_startup(tid);
+}
+INIT_APP_EXPORT(blink_init);

bsp/x1000/applications/main.c

 /*
- * File      : _main.c
+ * File      : main.c
  * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * COPYRIGHT (C) 2008 - 2017, RT-Thread Development Team
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -19,14 +19,12 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2015-11-19     Urey         the first version
+ * 2017-11-8      Tangyuxin    first version
  */
-#include <stdio.h>
-#include <stdlib.h>
 
-int main(int argc, char** argv)
-{
-    printf("Hello RT-Thread!\n");
+#include <rtthread.h>
 
+int main(int argc, char** argv)
+{   
     return 0;
 }

bsp/x1000/applications/mnt_init.c

+/*
+ * File      : mnt_init.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-11-8      Tangyuxin    first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#ifdef RT_USING_DFS
+#include <dfs_fs.h>
+
+int mnt_init(void)
+{
+    rt_kprintf("init filesystem...\n");
+#ifdef RT_USING_MTD_NOR
+    //mount rootfs
+    if (dfs_mount("rootfs", "/", "elm", 0, 0) == 0)
+    {
+        rt_kprintf("File System on root initialized!\n");
+    }
+    else
+    {
+        rt_kprintf("File System on root initialization failed!\n");
+    }
+
+    //mount appfs
+    if (dfs_mount("appfs", "/appfs", "elm", 0, 0) == 0)
+    {
+        rt_kprintf("File System on appfs initialized!\n");
+    }
+    else
+    {
+        rt_kprintf("File System on appfs initialization failed!\n");
+    }
+#endif
+
+#if (defined(RT_USING_SDIO) && defined(RT_USING_MSC0))
+    rt_thread_delay(RT_TICK_PER_SECOND/5);
+    if (dfs_mount("sd0", "/sd", "elm", 0, 0) == 0)
+    {
+        rt_kprintf("File System on TF initialized!\n");
+    }
+    else
+    {
+        rt_kprintf("File System on TF fail!\n");
+    }
+#endif
+
+    return 0;
+}
+INIT_ENV_EXPORT(mnt_init);
+
+#endif

bsp/x1000/applications/rtgui_demo.c

+/*
+ * File      : rtgui_demo.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-11-8      Tangyuxin    first version
+ */
+
+#include <rtthread.h>
+
+// #define DEBUG
+
+#ifdef DEBUG
+#define DEBUG_PRINTF(...)   rt_kprintf(__VA_ARGS__)
+#else
+#define DEBUG_PRINTF(...)   
+#endif
+
+#ifdef RT_USING_GUIENGINE
+
+#include <rtgui/rtgui.h>
+#include <rtgui/rtgui_system.h>
+#include <rtgui/rtgui_app.h>
+
+#include <rtgui/widgets/window.h>
+#include <rtgui/dc.h>
+
+struct rtgui_win *main_win;
+rt_bool_t dc_event_handler(struct rtgui_object *object, rtgui_event_t *event);
+
+static void rt_gui_demo_entry(void *parameter)
+{    
+    struct rtgui_app *app;
+    
+    DEBUG_PRINTF("gui demo entry\n");
+	
+	/* create gui app */
+    app = rtgui_app_create("gui_demo");
+    if (app == RT_NULL)
+    {
+        DEBUG_PRINTF("rtgui_app_create faild\n");
+        return;	
+    }
+    
+	/* create main window */
+	main_win = rtgui_mainwin_create(RT_NULL, 
+									"UiWindow", RTGUI_WIN_STYLE_NO_TITLE | RTGUI_WIN_STYLE_NO_BORDER);
+    if (main_win == RT_NULL)
+    {
+        DEBUG_PRINTF("main_win is null\n");
+        rtgui_app_destroy(app);
+        return;
+    }
+    
+	rtgui_object_set_event_handler(RTGUI_OBJECT(main_win), dc_event_handler);
+	
+    DEBUG_PRINTF("rtgui_win_show\n");
+	rtgui_win_show(main_win, RT_FALSE);
+    
+    DEBUG_PRINTF("rtgui_app_run\n");
+	rtgui_app_run(app);
+    
+    DEBUG_PRINTF("rtgui_win_destroy\n");
+	rtgui_win_destroy(main_win);
+    
+    DEBUG_PRINTF("rtgui_app_destroy\n");
+	rtgui_app_destroy(app);	
+}
+
+rt_bool_t dc_event_handler(struct rtgui_object *object, rtgui_event_t *event)
+{
+    struct rtgui_widget *widget = RTGUI_WIDGET(object);
+
+    if (event->type == RTGUI_EVENT_PAINT)
+    {
+        struct rtgui_dc *dc;
+        rtgui_rect_t rect;
+		
+		rt_kprintf("\r\n RTGUI_EVENT_PAINT \r\n");
+		rtgui_win_event_handler(RTGUI_OBJECT(widget), event);
+        
+        rtgui_widget_get_rect(widget, &rect);
+        DEBUG_PRINTF("widget react x1: %d, y1: %d, x2: %d, y2: %d\r\n",
+                                rect.x1, rect.y1, rect.x2, rect.y2);
+
+		dc = rtgui_dc_begin_drawing(widget);
+		if(dc == RT_NULL)
+		{
+			DEBUG_PRINTF("\r\n dc is null \r\n");
+			return RT_FALSE;
+		}
+
+		rtgui_dc_draw_line(dc, rect.x1, rect.y1, rect.x2, rect.y2);
+		rtgui_dc_draw_line(dc, rect.x1, rect.y2, rect.x2, rect.y1);
+        
+        rect.x1 += (rect.x2 - rect.x1) / 2;
+        rect.y1 += (rect.y2 - rect.y1) / 2;
+        rtgui_dc_draw_text_stroke(dc, __DATE__"--"__TIME__, &rect, HIGH_LIGHT, BLUE);
+               
+		rtgui_dc_end_drawing(dc,RT_TRUE);
+    }
+	return RT_FALSE;
+}
+
+int rt_gui_demo_init(void)
+{
+    rt_thread_t tid;
+    rt_device_t device;
+    rt_err_t  err;
+    
+    device = rt_device_find("lcd");
+    if(device == RT_NULL)
+    {
+        rt_kprintf("Not found LCD driver\n");
+        return RT_ERROR;
+    }
+    
+    err = rt_device_open(device, RT_DEVICE_OFLAG_RDWR);
+    if (err != RT_EOK)
+    {
+        rt_kprintf("Open LCD driver fail\n");
+        return RT_ERROR;
+    }
+    
+    /* set graphic device */
+    rtgui_graphic_set_device(device);
+    
+    tid = rt_thread_create("mygui",
+        rt_gui_demo_entry, RT_NULL,
+        2048, 25, 10);
+
+    if (tid != RT_NULL)
+        rt_thread_startup(tid);
+    
+    return 0;
+}
+INIT_APP_EXPORT(rt_gui_demo_init);
+#endif /* RT_USING_GUIENGINE */

bsp/x1000/drivers/Kconfig

+choice
+    prompt "Choice bsp board"
+    default BOARD_HALLEY2_REALBOARD_V2
+    
+    config BOARD_HALLEY2
+        bool "Using haller2 board"
+        
+    config BOARD_PHOENIX
+        bool "Using phoenix board"
+
+    config BOARD_CANNA
+        bool "Using canna board"
+    
+    config BOARD_HALLEY2_FIR
+        bool "Using haller2 fir board"
+    
+    config BOARD_HALLEY2_REALBOARD
+        bool "Using haller2 realboard board"
+        
+    config BOARD_HALLEY2_REALBOARD_V2
+        bool "Using haller2 realboard v2 board"
+    
+    config BOARD_HALLEY2_IDELAN
+        bool "Using haller2 idelan board"
+endchoice
+
+if RT_USING_SERIAL
+    config RT_USING_UART0
+        bool "Using UART0"
+        default n
+
+    config RT_USING_UART1
+        bool "Using UART1"
+        default n    
+        
+    config RT_USING_UART2
+        bool "Using UART2"
+        default y
+endif
+
+if RT_USING_SDIO
+    config RT_USING_MSC0
+        bool "Using MSC0 for sd card"
+        default y
+        
+    config RT_USING_MSC1
+        bool "Using MSC1 for wifi"
+        default y
+
+    config RT_MMCSD_STACK_SIZE
+    int "Set mmc thread stack size"
+    default 2048
+endif
+
+if RT_USING_GUIENGINE
+    config RT_USING_SLCD
+        bool "Using lcd display"
+        default y
+        
+    if RT_USING_SLCD
+        choice
+            prompt "Choice LCD controller"
+            default RT_USING_ILI9488
+            
+            config RT_USING_ILI9488
+                bool "Using  ILI9488 controller"
+                
+            config RT_USING_ILI9341
+                bool "Using  ILI9341 controller"
+
+            config RT_USING_OTM4802
+                bool "Using  OTM4802 controller"
+            
+            config RT_USING_TRULY_TFT240240
+                bool "Using  TFT240240 controller"
+        endchoice
+    endif
+
+    if RT_USING_I2C
+        config RT_USING_TOUCH
+            bool "Using touch"
+            default y
+            
+        if RT_USING_TOUCH
+            choice
+                prompt "Choice touch controller"
+                default RT_USING_GT9XX
+                
+                config RT_USING_GT9XX
+                    bool "Using  GT9XX controller"
+                    
+                config RT_USING_FT6x06
+                    bool "Using  FT6x06 controller"
+            endchoice
+            
+            config RT_TOUCH_THREAD_PRIORITY
+                int "Set touch thread priority"
+                range 2 32
+                default 10
+        endif
+    endif
+endif
+
+if RT_USING_I2C
+    config RT_USING_I2C0
+        bool "Using iic0 bus"
+        default y
+        
+    config RT_USING_I2C1
+        bool "Using iic1 bus"
+        default n
+
+    config RT_USING_I2C2
+        bool "Using iic2 bus"
+        default n
+endif
+
+config RT_USING_AUDIO
+    bool "Using audio"
+    default n
+if RT_USING_AUDIO
+    config RT_USING_ICODEC
+    bool "Using icodec"
+    default n
+endif
+
+config RT_USING_CPU_FFS
+    bool "Using CPU FFS"
+    default y
+
+

bsp/x1000/drivers/SConscript

+# RT-Thread building script for component
+
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c') + Glob('*.S')
+CPPPATH = [cwd, str(Dir('#'))]
+
+if not GetDepend('RT_USING_I2C'):
+    SrcRemove(src, ['drv_i2c.c'])
+if not GetDepend('RT_USING_SPI'):
+    SrcRemove(src, ['drv_spi.c'])
+if not GetDepend('RT_USING_WDT'):
+    SrcRemove(src, ['drv_reset.c'])
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+# build for sub-directory
+list = os.listdir(cwd)
+objs = []
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+group = group + objs
+
+Return('group')

bsp/x1000/drivers/audio/SConscript

+# RT-Thread building script for component
+
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c') + Glob('*.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('drv_audio', src, depend = ['RT_USING_AUDIO'], CPPPATH = CPPPATH)
+
+Return('group')

bsp/x1000/drivers/audio/drv_aic_i2s.c

+/*
+ * File      : drv_i2s.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-11-19     Urey         the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <drivers/audio.h>
+
+#include "dma.h"
+
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+#endif
+
+#include "board.h"
+#include "drv_clock.h"
+#include "drv_dma.h"
+#include "drv_gpio.h"
+#include "drv_aic.h"
+#include "drv_aic_i2s.h"
+
+#define AIC_DEBUG   0
+#if AIC_DEBUG
+#define AIC_DBG(...)     rt_kprintf("[AIC]"),rt_kprintf(__VA_ARGS__)
+#else
+#define AIC_DBG(...)
+#endif
+
+static struct jz_aic _g_jz_aic;
+
+int aic_set_rate(struct jz_aic *aic, uint32_t freq)
+{
+    int ret;
+//    clk_disable(aic->clk);
+
+    if (aic->clk_rate != freq)
+    {
+        ret = clk_set_rate(aic->clk, freq);
+        if (!ret)
+            aic->clk_rate = clk_get_rate(aic->clk);
+
+    }
+
+//    clk_enable(aic->clk);
+
+    AIC_DBG("aic clock = %d\n",clk_get_rate(aic->clk));
+    return aic->clk_rate;
+}
+
+static void aic_irq_handler(int vector, void *param)
+{
+    struct jz_aic *aic = (struct jz_aic *)param;
+
+    aic->mask = __aic_get_irq_enmask(aic);
+
+    if (aic->mask && (aic->mask & __aic_get_irq_flag(aic)))
+    {
+        /*Disable all aic interrupt*/
+        __aic_set_irq_enmask(aic, 0);
+
+        if ((aic->mask & 0x8) && __aic_test_ror(aic))
+        {
+            aic->ror++;
+            AIC_DBG("recieve fifo [overrun] interrupt time [%d]\n",
+                            aic->ror);
+        }
+
+        if ((aic->mask & 0x4) && __aic_test_tur(aic))
+        {
+            aic->tur++;
+            AIC_DBG("transmit fifo [underrun] interrupt time [%d]\n",
+                            aic->tur);
+        }
+
+        if ((aic->mask & 0x2) && __aic_test_rfs(aic))
+        {
+            AIC_DBG("[recieve] fifo at or above threshold interrupt time\n");
+        }
+
+        if ((aic->mask & 0x1) && __aic_test_tfs(aic))
+        {
+            AIC_DBG("[transmit] fifo at or blow threshold interrupt time\n");
+        }
+
+        /*sleep, avoid frequently interrupt*/
+        __aic_clear_all_irq_flag(aic);
+        __aic_set_irq_enmask(aic, aic->mask);
+    }
+}
+
+struct jz_aic* _aic_init(void)
+{
+    struct jz_aic       *aic = &_g_jz_aic;
+    struct rt_device    *device;
+
+
+    aic->base = AIC_BASE;
+
+    aic->clk_gate   = clk_get("aic");
+    aic->clk        = clk_get("cgu_i2s");
+    if((aic->clk_gate == RT_NULL) || (aic->clk == RT_NULL))
+    {
+        AIC_DBG("aic or i2s clk error\n");
+
+        goto aic_init_error;
+    }
+    /* set system clock */
+    clk_set_rate(aic->clk, 24000000);
+    aic->clk_rate = 24000000;
+
+    clk_enable(aic->clk_gate);
+    clk_enable(aic->clk);
+    aic->irqno      = IRQ_AIC0;
+    aic->irqflags   =  0;
+
+    rt_hw_interrupt_install(IRQ_AIC0,aic_irq_handler,aic,"irq_aic");
+    rt_hw_interrupt_umask(IRQ_AIC0);
+
+    return aic;
+
+aic_init_error:
+    clk_put(aic->clk);
+    clk_put(aic->clk_gate);
+    return RT_NULL;
+}
+
+#define I2S_DEBUG   0
+#if I2S_DEBUG
+#define I2S_DBG(...)     rt_kprintf("[I2S]"),rt_kprintf(__VA_ARGS__)
+#else
+#define I2S_DBG(...)
+#endif
+
+#define I2S_TFIFO_DEPTH     64
+#define I2S_RFIFO_DEPTH     32
+
+#define I2S_OSS_FMT         16
+#define I2S_ISS_FMT         16
+
+#define I2S_PALY_CHANEL     2
+
+struct jz_i2s   _g_jz_i2s =
+{
+    .aic        = 0,
+    .i2s_init   = 0,
+    .i2s_mode   = 0,
+    .tx_dr_base = ((AIC_BASE + AICDR) & 0x1FFFFFFF),
+	.channels	= 2,
+	.fmt_width	= 16,
+    .tx_dmac    = RT_NULL,
+    .rx_dmac    = RT_NULL,
+};
+
+#define I2S_DMA_TX_CHAN     2
+#define I2S_DMA_RX_CHAN     3
+
+static void aic_i2s_trans_complete(struct rt_dma_channel *dmac, struct dma_message *msg);
+
+static void dump_registers(struct jz_aic *aic)
+{
+    rt_kprintf("AIC_FR     0x%08x : 0x%08x\n",     (aic->base+AICFR),  jz_aic_read_reg(aic, AICFR));
+    rt_kprintf("AIC_CR     0x%08x : 0x%08x\n",     (aic->base+AICCR),  jz_aic_read_reg(aic, AICCR));
+    rt_kprintf("AIC_I2SCR  0x%08x : 0x%08x\n",     (aic->base+I2SCR),  jz_aic_read_reg(aic, I2SCR));
+    rt_kprintf("AIC_SR     0x%08x : 0x%08x\n",     (aic->base+AICSR),  jz_aic_read_reg(aic, AICSR));
+    rt_kprintf("AIC_I2SSR  0x%08x : 0x%08x\n",     (aic->base+I2SSR),  jz_aic_read_reg(aic, I2SSR));
+    rt_kprintf("AIC_I2SDIV 0x%08x : 0x%08x\n",     (aic->base+I2SDIV), jz_aic_read_reg(aic, I2SDIV));
+    rt_kprintf("AIC_DR     0x%08x : 0x%08x\n",     (aic->base+AICDR),  jz_aic_read_reg(aic, AICDR));
+
+    rt_kprintf("AIC_I2SCDR\t 0x%08x\n",*(volatile unsigned int*)0xb0000060);
+    rt_kprintf("AIC_I2SCDR1\t 0x%08x\n",*(volatile unsigned int*)0xb0000070);
+    rt_kprintf("AICSR\t 0x%08x\n",*(volatile unsigned int*)0xb0020014);
+    return;
+}
+
+int dump_aic_i2s(void)
+{
+	dump_registers(_g_jz_i2s.aic);
+
+	return 0;
+}
+MSH_CMD_EXPORT(dump_aic_i2s,dump i2s registers...);
+
+#if 0
+int i2scdr_extclk(void)
+{
+	rt_uint32_t regValue;
+
+	regValue = readl(0xb0000060);
+	regValue &= ~(0x01 << 30);
+	writel(regValue,0xb0000060);
+
+    rt_kprintf("AIC_I2SCDR\t 0x%08x\n",*(volatile unsigned int*)0xb0000060);
+}
+MSH_CMD_EXPORT(i2scdr_extclk,set i2s cdr ext clk...);
+
+int i2scdr_pllclk(void)
+{
+	rt_uint32_t regValue;
+
+	regValue = readl(0xb0000060);
+	regValue |= (0x01 << 30);
+	writel(regValue,0xb0000060);
+
+    rt_kprintf("AIC_I2SCDR\t 0x%08x\n",*(volatile unsigned int*)0xb0000060);
+}
+MSH_CMD_EXPORT(i2scdr_pllclk,set i2s cdr pll clk...);
+#endif
+
+static void aic_i2s_start_substream(struct jz_i2s *i2s,int stream)
+{
+	struct jz_aic *aic = i2s->aic;
+
+	if(stream == AUDIO_STREAM_REPLAY)
+	{
+		int i = 4;
+		I2S_DBG("codec fifo level0 %x\n", jz_aic_read_reg(aic, AICSR));
+		for (i= 0; i < I2S_TFIFO_DEPTH ; i++)
+		{
+			__aic_write_txfifo(aic, 0x0);
+			__aic_write_txfifo(aic, 0x0);
+		}
+
+		__aic_clear_tur(aic);
+		I2S_DBG("codec fifo level1 %x\n", jz_aic_read_reg(aic, AICSR));
+		__i2s_enable_replay(aic);
+
+		while (!__aic_test_tur(aic)) ;
+		__i2s_enable_transmit_dma(aic);
+		__aic_clear_tur(aic);
+#if I2S_DEBUG
+		__aic_en_tur_int(aic);
+#endif
+	}
+	else
+	{
+		__aic_flush_rxfifo(aic);
+		rt_thread_delay(1);
+		__i2s_enable_record(aic);
+		__i2s_enable_receive_dma(aic);
+
+#if I2S_DEBUG
+		__aic_en_ror_int(aic);
+#endif
+	}
+
+	I2S_DBG("strtup sub stream ok!\n");
+}
+
+static void aic_i2s_stop_substream(struct jz_i2s *i2s,int stream)
+{
+	struct jz_aic *aic = i2s->aic;
+
+	if(stream == AUDIO_STREAM_REPLAY)
+	{
+#if I2S_DEBUG
+		__aic_dis_tur_int(aic);
+#endif
+		if (__i2s_transmit_dma_is_enable(aic))
+		{
+			//wait all dma queue is complete
+			while(i2s->tx_dmac->get_index != i2s->tx_dmac->put_index)
+				rt_thread_delay(1);
+
+			__i2s_disable_transmit_dma(aic);
+			__aic_clear_tur(aic);
+			/*hrtime mode: stop will be happen in any where, make sure there is
+			 *	no data transfer on ahb bus before stop dma
+			 */
+			while(!__aic_test_tur(aic));
+		}
+		__i2s_disable_replay(aic);
+		__aic_clear_tur(aic);
+	}
+	else
+	{
+//		if (jz_i2s_debug) __aic_dis_ror_int(aic);
+
+		if (__i2s_receive_dma_is_enable(aic))
+		{
+			__i2s_disable_receive_dma(aic);
+			__aic_clear_ror(aic);
+			while(!__aic_test_ror(aic));
+		}
+		__i2s_disable_record(aic);
+		__aic_clear_ror(aic);
+	}
+}
+
+int aic_i2s_set_clkdiv(struct jz_i2s *i2s,int div_id, int div)
+{
+    struct jz_aic *aic = i2s->aic;
+
+    I2S_DBG("enter %s div_id %d div %d\n", __func__, div_id , div);
+
+    /*BIT CLK fix 64FS*/
+    /*SYS_CLK is 256, 384, 512, 768*/
+    if (div != 256 && div != 384 && div != 512 && div != 768)
+        return -RT_EIO;
+
+	__i2s_set_dv(aic, (div/64) - 1);
+	__i2s_set_idv(aic, (div/64) - 1);
+
+    return RT_EOK;
+}
+
+
+/*
+ * stream = CODEC_STREAM_PLAYBACK or CODEC_STREAM_CAPTURE
+ */
+int aic_i2s_startup(struct jz_i2s *i2s,int stream)
+{
+	struct jz_aic   *aic = i2s->aic;
+
+	if(!i2s->i2s_mode)
+	{
+		I2S_DBG("start set AIC register....\n");
+	    __aic_disable(aic);
+
+		__aic_select_i2s(aic);
+		__i2s_select_i2s_fmt(aic);
+
+#ifndef CODEC_AS_MASTER
+		__i2s_bclk_output(aic);
+		__i2s_sync_output(aic);
+#else
+		__i2s_bclk_input(aic);
+		__i2s_sync_input(aic);
+#endif
+
+		aic_i2s_set_sysclk(i2s,CODEC_DEF_RATE);
+
+		__i2s_play_lastsample(aic);
+		__i2s_set_transmit_trigger(aic, I2S_TFIFO_DEPTH/4);
+		__i2s_set_receive_trigger(aic, (I2S_RFIFO_DEPTH/4 - 1));
+		__aic_enable(aic);
+
+	}
+
+	/* Set playback or record mode */
+	if(stream == AUDIO_STREAM_REPLAY)
+	{
+		__i2s_send_rfirst(aic);
+		__i2s_disable_transmit_dma(aic);
+		__i2s_disable_replay(aic);
+		__aic_clear_tur(aic);
+		i2s->i2s_mode |= I2S_WRITE;
+	}
+	else
+	{
+		__i2s_disable_receive_dma(aic);
+		__i2s_disable_record(aic);
+		__aic_clear_ror(aic);
+		i2s->i2s_mode |= I2S_READ;
+	}
+
+	return 0;
+}
+
+int aic_i2s_trigger(struct jz_i2s* i2s,int cmd,int stream)
+{
+	switch (cmd)
+	{
+		case I2S_TRIGGER_START:
+		case I2S_TRIGGER_RESUME:
+		case I2S_TRIGGER_PAUSE_RELEASE:
+			aic_i2s_start_substream(i2s,stream);
+			break;
+		case I2S_TRIGGER_STOP:
+		case I2S_TRIGGER_SUSPEND:
+		case I2S_TRIGGER_PAUSE_PUSH:
+		default:
+			aic_i2s_stop_substream(i2s,stream);
+			break;
+	}
+
+	return 0;
+}
+
+int aic_i2s_hw_params(struct jz_i2s* i2s,int stream)
+{
+	struct jz_aic   *aic = i2s->aic;
+    struct dma_config       config;
+
+    int trigger;
+	int bus_width;
+
+	I2S_DBG("upgrade hw params...\n");
+
+	if(stream == AUDIO_STREAM_REPLAY)
+	{
+		/* channel */
+		__i2s_channel(aic, i2s->channels);
+
+		/* format */
+		if(i2s->fmt_width == 8)
+			bus_width = RT_DMA_BUSWIDTH_1_BYTE;
+		else if(i2s->fmt_width == 16)
+			bus_width = RT_DMA_BUSWIDTH_2_BYTES;
+		else
+			bus_width = RT_DMA_BUSWIDTH_4_BYTES;
+
+        i2s->tx_dmac = rt_dma_get_channel(I2S_DMA_TX_CHAN);
+        RT_ASSERT(i2s->tx_dmac != RT_NULL);
+        if(i2s->tx_dmac != RT_NULL)
+        {
+            config.direction        = RT_DMA_MEM_TO_DEV;
+            config.src_addr_width   = bus_width;
+            config.src_maxburst     = (64 * 1024);
+            config.dst_addr_width   = bus_width;
+            config.dst_maxburst     = (I2S_TFIFO_DEPTH * bus_width)/2;
+            rt_dma_configture(i2s->tx_dmac,&config);
+
+            i2s->tx_dmac->start = RT_NULL;
+            i2s->tx_dmac->complete = aic_i2s_trans_complete;
+        }
+
+		__i2s_set_oss(aic, i2s->fmt_width);
+		__i2s_set_transmit_trigger(aic, (I2S_TFIFO_DEPTH / 4));
+
+		I2S_DBG("TX_DMAC config ok!\n");
+	}
+	else
+	{
+		/* format */
+		if(i2s->fmt_width == 8)
+			bus_width = RT_DMA_BUSWIDTH_1_BYTE;
+		else if(i2s->fmt_width == 16)
+			bus_width = RT_DMA_BUSWIDTH_2_BYTES;
+		else
+			bus_width = RT_DMA_BUSWIDTH_4_BYTES;
+
+        i2s->rx_dmac = rt_dma_get_channel(I2S_DMA_RX_CHAN);
+        if(i2s->rx_dmac != RT_NULL)
+        {
+            config.direction        = RT_DMA_DEV_TO_MEM;
+            config.src_addr_width   = bus_width;
+            config.src_maxburst     =  (I2S_RFIFO_DEPTH * bus_width)/2;
+            config.dst_addr_width   = bus_width;
+            config.dst_maxburst     = (64 * 1024);
+            rt_dma_configture(i2s->rx_dmac,&config);
+
+            i2s->rx_dmac->start = RT_NULL;
+            i2s->rx_dmac->complete = aic_i2s_trans_complete;
+
+            I2S_DBG("RX DMA config ok \n");
+        }
+
+		__i2s_set_iss(aic, i2s->fmt_width);
+		__i2s_set_receive_trigger(aic, (I2S_RFIFO_DEPTH/4 - 1));
+
+	}
+
+	return 0;
+}
+
+void aic_i2s_shutdown(struct jz_i2s *i2s,int stream)
+{
+	struct jz_aic   *aic = i2s->aic;
+
+	aic_i2s_stop_substream(i2s,stream);
+
+	if(stream == AUDIO_STREAM_REPLAY)
+		i2s->i2s_mode &= ~I2S_WRITE;
+	else
+		i2s->i2s_mode &= ~I2S_READ;
+
+	if(!i2s->i2s_mode)
+		__aic_disable(aic);
+}
+
+int aic_i2s_set_sysclk(struct jz_i2s *i2s,uint32_t freq)
+{
+	struct jz_aic *aic = i2s->aic;
+
+
+#ifdef RT_USING_ICODEC
+	__aic_select_internal_codec(aic);
+#else
+	__aic_select_external_codec(aic);
+#endif
+
+	__i2s_stop_bitclk(aic);
+
+	aic_set_rate(aic, freq);
+
+	__i2s_start_bitclk(aic);
+
+#ifdef CFG_AIC_SOC_CLKOUT
+	/* Master clk output */
+	__i2s_select_sysclk_output(aic);
+
+	__i2s_enable_sysclk_output(aic);
+#else
+	/* Master clk input */
+	__i2s_select_sysclk_input(aic);
+	__i2s_disable_sysclk_output(aic);
+#endif
+
+    return 0;
+}
+
+
+static void aic_i2s_trans_complete(struct rt_dma_channel *dmac, struct dma_message *msg)
+{
+	I2S_DBG("TAG,%d,%s\n",__LINE__,__func__);
+	if(msg->complete_cb)
+	{
+		if(msg->t_mode == JZDMA_REQ_I2S0_TX)
+			msg->complete_cb(msg->complete_arg,msg->src_addr);
+		else
+			msg->complete_cb(msg->complete_arg,msg->dst_addr);
+	}
+}
+
+rt_size_t aic_i2s_send(struct jz_i2s *i2s, const void* buffer, rt_size_t size,void (*tx_callback)(void *,void *), void *tx_arg)
+{
+    struct dma_message         message;
+
+	I2S_DBG("TAG,%d,%s\n",__LINE__,__func__);
+
+    message.src_addr    = (uint8_t *) (buffer);
+    message.src_option  = RT_DMA_ADDR_INC;
+
+    message.dst_addr    = (uint8_t *) (AIC_BASE + AICDR);
+    message.dst_option  = RT_DMA_ADDR_FIX;
+
+    message.t_size      = size;
+    message.t_mode      = JZDMA_REQ_I2S0_TX;
+
+    message.complete_cb	= (void *)tx_callback;
+    message.complete_arg= tx_arg;
+
+    I2S_DBG("i2s trans  length = %d\n",size);
+
+	if (rt_dma_trans_message(i2s->tx_dmac, &message) == RT_EOK)
+		return size;
+
+    return 0;
+}
+
+rt_size_t aic_i2s_recv(struct jz_i2s *i2s, void* buffer, rt_size_t size,void (*rx_callback)(void *,void *), void *rx_arg)
+{
+    struct dma_message         message;
+
+    message.src_addr    = (uint8_t *) (AIC_BASE + AICDR);
+    message.src_option  = RT_DMA_ADDR_FIX;
+
+    message.dst_addr    = (uint8_t *) (buffer);
+    message.dst_option  = RT_DMA_ADDR_INC;
+
+    message.t_size      = size;
+    message.t_mode      = JZDMA_REQ_I2S0_RX;
+
+    message.complete_cb	= (void *)rx_callback;
+    message.complete_arg= rx_arg;
+
+	if(rt_dma_trans_message(i2s->rx_dmac,&message) == RT_EOK)
+		return size;
+
+    return 0;
+}
+
+
+
+struct jz_i2s *rt_hw_aic_i2s_init(void)
+{
+    struct jz_aic *aic;
+    struct jz_i2s *i2s = &_g_jz_i2s;
+
+#ifndef RT_USING_ICODEC
+#ifdef CFG_AIC_SOC_CLKOUT
+	gpio_set_func(GPIO_PORT_B, GPIO_Pin_0, GPIO_FUNC_1); // I2S_MCLK
+#endif
+	gpio_set_func(GPIO_PORT_B, GPIO_Pin_1, GPIO_FUNC_1); // I2S_BCLK
+	gpio_set_func(GPIO_PORT_B, GPIO_Pin_2, GPIO_FUNC_1); // I2S_LRCLK
+	gpio_set_func(GPIO_PORT_B, GPIO_Pin_3, GPIO_FUNC_1); // I2S_DI
+	gpio_set_func(GPIO_PORT_B, GPIO_Pin_4, GPIO_FUNC_1); // I2S_DO
+#endif
+
+	I2S_DBG("TAG,%d,%s\n",__LINE__,__func__);
+    aic = _aic_init();
+    if(aic == RT_NULL)
+        return RT_NULL;
+    i2s->aic = aic;
+
+    i2s->i2s_mode = 0;
+
+	I2S_DBG("TAG,%d,%s\n",__LINE__,__func__);
+
+	/* now ,we just support I2S playback */
+	aic_i2s_startup(i2s,AUDIO_STREAM_REPLAY);
+
+	aic_i2s_hw_params(i2s,AUDIO_STREAM_REPLAY);
+
+    return i2s;
+}
+

bsp/x1000/drivers/audio/drv_aic_i2s.h

+/*
+ * drv_aic_i2s.h
+ *
+ *  Created on: 2016年4月1日
+ *      Author: Urey
+ */
+
+#ifndef DRIVER_DRV_AIC_I2S_H_
+#define DRIVER_DRV_AIC_I2S_H_
+
+#include "board.h"
+
+
+#ifdef RT_USING_ICODEC
+#	define CODEC_AS_MASTER
+
+#define CODEC_DEF_RATE    (24000000)
+#else
+//#	undef CODEC_AS_MASTER
+//#	define CODEC_AS_MASTER
+
+#define CODEC_DEF_RATE    (44100)
+#endif
+
+#ifdef RT_USING_ECODEC_WM8978
+#	define CFG_AIC_I2S_EXT_CODEC
+#endif
+
+#define CFG_AIC_SOC_CLKOUT
+//#define CFG_AIC_SOC_CLKIN
+
+#define CFG_I2S_DMA_PAGE_SIZE	(32 * 1024)
+#define CFG_I2S_DMA_PAGE_NUM	8
+
+enum
+{
+    I2S_TRIGGER_STOP  = 0,
+    I2S_TRIGGER_START ,
+	I2S_TRIGGER_PAUSE_PUSH ,
+	I2S_TRIGGER_PAUSE_RELEASE ,
+    I2S_TRIGGER_SUSPEND ,
+    I2S_TRIGGER_RESUME,
+};
+
+
+
+/*********************************************************************************************************
+**   数据结构
+*********************************************************************************************************/
+struct jz_i2s
+{
+    struct jz_aic   *aic;
+    int i2s_init;
+#define I2S_WRITE 0x1
+#define I2S_READ  0x2
+#define I2S_INCODEC (0x1 <<4)
+#define I2S_EXCODEC (0x2 <<4)
+#define I2S_SLAVE (0x1 << 8)
+#define I2S_MASTER (0x2 << 8)
+    int i2s_mode;
+    uint32_t    tx_dr_base;
+
+	int channels;
+	int fmt_width;
+	int rates;
+
+    /* used for DMA transform */
+    struct rt_dma_channel *tx_dmac;
+    struct rt_dma_channel *rx_dmac;
+};
+
+/*********************************************************************************************************
+**   函数申明
+*********************************************************************************************************/
+int aic_set_rate(struct jz_aic *aic, uint32_t freq);
+
+struct jz_i2s *rt_hw_aic_i2s_init(void);
+
+//void aic_i2s_start_substream(struct jz_i2s *i2s,int stream);
+//void aic_i2s_stop_substream(struct jz_i2s *i2s,int stream);
+int aic_i2s_set_sysclk(struct jz_i2s *i2s,uint32_t freq);
+int aic_i2s_set_clkdiv(struct jz_i2s *i2s,int div_id, int div);
+int aic_i2s_startup(struct jz_i2s *i2s,int stream);
+int aic_i2s_trigger(struct jz_i2s* i2s,int cmd,int stream);
+
+int aic_i2s_hw_params(struct jz_i2s* i2s,int stream);
+void aic_i2s_shutdown(struct jz_i2s *i2s,int stream);
+
+rt_size_t aic_i2s_send(struct jz_i2s *i2s, const void* buffer, rt_size_t size,void (*tx_callback)(void *,void *), void *tx_arg);
+rt_size_t aic_i2s_recv(struct jz_i2s *i2s,        void* buffer, rt_size_t size,void (*rx_callback)(void *,void *), void *rx_arg);
+
+
+void aic_i2s_set_rate(struct jz_i2s *i2s,int rate);
+#endif /* DRIVER_DRV_AIC_I2S_H_ */

bsp/x1000/drivers/audio/drv_codec_icodec.h

+/*
+ * drv_codec_icodec.h
+ *
+ *  Created on: 2017110
+ *      Author: Urey
+ */
+
+#ifndef _DRV_CODEC_ICODEC_H_
+#define _DRV_CODEC_ICODEC_H_
+
+#include <stdint.h>
+
+#include "x1000.h"
+#include "drv_clock.h"
+
+
+struct jz_icodec
+{
+    struct jz_i2s               *i2s;
+    struct rt_audio_configure	 replay_config;
+#ifdef AUDIO_DEVICE_USE_PRIVATE_BUFFER
+    struct rt_mempool  			mp;
+#endif /* AUDIO_DEVICE_USE_PRIVATE_BUFFER */
+	uint32_t mapped_base;
+
+	/* replay */
+    int     user_replay_volume;
+    int 	dac_user_mute;              	/*dac user mute state*/
+    int 	aohp_in_pwsq;               	/*aohp in power up/down seq*/
+    int 	hpl_wished_gain;                /*keep original hpl/r gain register value*/
+    int 	hpr_wished_gain;
+    int 	linl_wished_gain;               /*keep original hpl/r gain register value*/
+    int 	linr_wished_gain;
+
+};
+
+#define ICODEC_PCM_FORMAT       AUDIO_FMT_PCM_S16_LE
+#define ICODEC_SAMPLING_RATE    44100
+
+
+/*  icodec internal register space */
+enum {
+    SCODA_REG_SR = 0x0,
+    SCODA_REG_SR2,
+    SCODA_REG_SIGR,
+    SCODA_REG_SIGR2,
+    SCODA_REG_SIGR3,
+    SCODA_REG_SIGR5,
+    SCODA_REG_SIGR7,
+    SCODA_REG_MR,
+    SCODA_REG_AICR_DAC,
+    SCODA_REG_AICR_ADC,
+    SCODA_REG_CR_DMIC,
+    SCODA_REG_CR_MIC1,
+    SCODA_REG_CR_MIC2,
+    SCODA_REG_CR_DAC,
+    SCODA_REG_CR_DAC2,
+    SCODA_REG_CR_ADC,
+    SCODA_REG_CR_MIX,
+    SCODA_REG_DR_MIX,
+    SCODA_REG_CR_VIC,
+    SCODA_REG_CR_CK,
+    SCODA_REG_FCR_DAC,
+    SCODA_REG_SFCCR_DAC,
+    SCODA_REG_SFFCR_DAC,
+    SCODA_REG_FCR_ADC,
+    SCODA_REG_CR_TIMER_MSB,
+    SCODA_REG_CR_TIMER_LSB,
+    SCODA_REG_ICR,
+    SCODA_REG_IMR,
+    SCODA_REG_IFR,
+    SCODA_REG_IMR2,
+    SCODA_REG_IFR2,
+    SCODA_REG_GCR_DACL,
+    SCODA_REG_GCR_DACR,
+    SCODA_REG_GCR_DACL2,
+    SCODA_REG_GCR_DACR2,
+    SCODA_REG_GCR_MIC1,
+    SCODA_REG_GCR_MIC2,
+    SCODA_REG_GCR_ADCL,
+    SCODA_REG_GCR_ADCR,
+    SCODA_REG_GCR_MIXDACL,
+    SCODA_REG_GCR_MIXDACR,
+    SCODA_REG_GCR_MIXADCL,
+    SCODA_REG_GCR_MIXADCR,
+    SCODA_REG_CR_DAC_AGC,
+    SCODA_REG_DR_DAC_AGC,
+    SCODA_REG_CR_DAC2_AGC,
+    SCODA_REG_DR_DAC2_AGC,
+    SCODA_REG_CR_ADC_AGC,
+    SCODA_REG_DR_ADC_AGC,
+    SCODA_REG_SR_ADC_AGCDGL,
+    SCODA_REG_SR_ADC_AGCDGR,
+    SCODA_REG_SR_ADC_AGCAGL,
+    SCODA_REG_SR_ADC_AGCAGR,
+    SCODA_REG_CR_TR,
+    SCODA_REG_DR_TR,
+    SCODA_REG_SR_TR1,
+    SCODA_REG_SR_TR2,
+    SCODA_REG_SR_TR_SRCDAC,
+
+/*  icodec internal register extend space */
+    SCODA_MIX_0,
+    SCODA_MIX_1,
+    SCODA_MIX_2,
+    SCODA_MIX_3,
+    SCODA_MIX_4,
+
+    SCODA_DAC_AGC0,
+    SCODA_DAC_AGC1,
+    SCODA_DAC_AGC2,
+    SCODA_DAC_AGC3,
+
+    SCODA_DAC2_AGC0,
+    SCODA_DAC2_AGC1,
+    SCODA_DAC2_AGC2,
+    SCODA_DAC2_AGC3,
+
+    SCODA_ADC_AGC0,
+    SCODA_ADC_AGC1,
+    SCODA_ADC_AGC2,
+    SCODA_ADC_AGC3,
+    SCODA_ADC_AGC4,
+    SCODA_MAX_REG_NUM,
+};
+
+
+
+/*aicr dac*/
+#define SCODA_AICR_DAC_ADWL_SHIFT (6)
+#define SCODA_AICR_DAC_ADWL_MASK (0x3 << SCODA_AICR_DAC_ADWL_SHIFT)
+#define SCODA_AICR_DAC_SLAVE_SHIFT (5)
+#define SCODA_AICR_DAC_SLAVE_MASK (0x1 << SCODA_AICR_DAC_SLAVE_SHIFT)
+#define SCODA_AICR_DAC_SLAVE (1 << 5)
+#define SCODA_AICR_DAC_SB_SHIFT (4)
+#define SCODA_AICR_DAC_SB_MASK (0x1 << SCODA_AICR_DAC_SB_SHIFT)
+#define SCODA_AICR_DAC_AUDIOIF_SHIFT (0)
+#define SCODA_AICR_DAC_AUDIO_MASK (0x3 << SCODA_AICR_DAC_AUDIOIF_SHIFT)
+#define SCODA_AICR_DAC_AUDIOIF_I2S (0x3)
+
+/* aicr adc */
+#define SCODA_AICR_ADC_ADWL_SHIFT (6)
+#define SCODA_AICR_ADC_ADWL_MASK (0x3 << SCODA_AICR_ADC_ADWL_SHIFT)
+#define SCODA_AICR_ADC_SB_SHIFT (4)
+#define SCODA_AICR_ADC_SB_MASK (0x1 << SCODA_AICR_ADC_SB_SHIFT)
+#define SCODA_AICR_ADC_AUDIOIF_SHIFT (0)
+#define SCODA_AICR_ADC_AUDIO_MASK (0x3 << SCODA_AICR_ADC_AUDIOIF_SHIFT)
+#define SCODA_AICR_ADC_AUDIOIF_I2S (0x3)
+
+/* cr vic */
+#define SCODA_CR_VIC_SB_SHIFT (0)
+#define SCODA_CR_VIC_SB_MASK (1 << SCODA_CR_VIC_SB_SHIFT)
+#define SCODA_CR_VIC_SB_SLEEP_SHIFT (1)
+#define SCODA_CR_VIC_SB_SLEEP_MASK (1 << SCODA_CR_VIC_SB_SLEEP_SHIFT)
+
+/* fcr adc/dac */
+#define SCODA_FCR_FREQ_SHIFT (0)
+#define SCODA_FCR_FREQ_MASK (0xf << SCODA_FCR_FREQ_SHIFT)
+
+/* cr dac */
+#define SCODA_CR_DAC_SMUTE_SHIFT (7)
+#define SCODA_CR_DAC_SMUTE_MASK (0x1 << SCODA_CR_DAC_SMUTE_SHIFT)
+#define SCODA_CR_DAC_SB_SHIFT (4)
+#define SCODA_CR_DAC_SB_MASK (0x1 << SCODA_CR_DAC_SB_SHIFT)
+#define SCODA_CR_DAC_ZERO_SHIFT (0)
+#define SCODA_CR_DAC_ZERO_MASK (0x1 << SCODA_CR_DAC_ZERO_SHIFT)
+
+/* cr dac */
+#define SCODA_CR_ADC_SMUTE_SHIFT (7)
+#define SCODA_CR_ADC_SMUTE_MASK (0x1 << SCODA_CR_ADC_SMUTE_SHIFT)
+#define SCODA_CR_ADC_MIC_SEL_SHIFT (6)
+#define SCODA_CR_ADC_MIC_SEL_MASK (0x1 << SCODA_CR_ADC_MIC_SEL_SHIFT)
+#define SCODA_CR_ADC_SB_SHIFT (4)
+#define SCODA_CR_ADC_SB_MASK (0x1 << SCODA_CR_ADC_SB_SHIFT)
+#define SCODA_CR_ADC_ZERO_SHIFT (0)
+#define SCODA_CR_ADC_ZERO_MASK (0x1 << SCODA_CR_ADC_ZERO_SHIFT)
+
+/* ifr */
+#define SCODA_IFR_DAC_MUTE_SHIFT (0)
+#define SCODA_IFR_DAC_MUTE_MASK (0x1 << SCODA_IFR_DAC_MUTE_SHIFT)
+#define SCODA_IFR_ADC_MUTE_SHIFT (2)
+#define SCODA_IFR_ADC_MUTE_MASK (0x1 << SCODA_IFR_ADC_MUTE_SHIFT)
+#define SCODA_IFR_ADAS_LOCK_SHIFT (7)
+#define SCODA_IFR_ADAS_LOCK_MASK (0x1 << SCODA_IFR_ADAS_LOCK_SHIFT)
+
+/* cr ck */
+#define SCODA_CR_CK_MCLK_DIV_SHIFT (6)
+#define SCODA_CR_CK_MCLK_DIV_MASK (0x1 << SCODA_CR_CK_MCLK_DIV_SHIFT)
+#define SCODA_CR_CK_SDCLK_SHIFT (4)
+#define SCODA_CR_CK_SDCLK_MASK (0x1 << SCODA_CR_CK_SDCLK_SHIFT)
+#define SCODA_CR_CRYSTAL_SHIFT (0)
+#define SCODA_CR_CRYSTAL_MASK (0xf << SCODA_CR_CRYSTAL_SHIFT)
+
+/* icr */
+#define SCODA_ICR_INT_FORM_SHIFT (6)
+#define SCODA_ICR_INT_FORM_MASK (0x3 << SCODA_ICR_INT_FORM_SHIFT)
+#define SCODA_ICR_INT_FORM_HIGH (0)
+#define SCODA_ICR_INT_FORM_LOW  (1)
+
+/* imr */
+#define SCODA_IMR_COMMON_MASK (0xff)
+#define SCODA_IMR2_COMMON_MASK (0xff)
+
+/*For Codec*/
+#define RGADW       (0x4)
+#define RGDATA      (0x8)
+
+
+static inline void icodec_mapped_reg_set(uint32_t xreg, int xmask, int xval)
+{
+    int val = readl(xreg);
+    val &= ~(xmask);
+    val |= xval;
+    writel(val, xreg);
+}
+
+
+static inline int icodec_mapped_test_bits(uint32_t xreg, int xmask, int xval)
+{
+    int val = readl(xreg);
+    val &= xmask;
+    return (val == xval);
+}
+
+
+/*
+ * RGADW
+ */
+#define SCODA_RGDIN_BIT         (0)
+#define SCODA_RGDIN_MASK        (0xff << SCODA_RGDIN_BIT)
+#define SCODA_RGADDR_BIT        (8)
+#define SCODA_RGADDR_MASK       (0x7f << SCODA_RGADDR_BIT)
+#define SCODA_RGWR_BIT          (16)
+#define SCODA_RGWR_MASK         (0x1  << SCODA_RGWR_BIT)
+
+#define icodec_test_rw_inval(icodec)      \
+    icodec_mapped_test_bits((icodec->mapped_base + RGADW), SCODA_RGWR_MASK, (1 << SCODA_RGWR_BIT))
+/*
+ * RGDATA
+ */
+#define SCODA_RGDOUT_BIT        (0)
+#define SCODA_RGDOUT_MASK       (0xff << SCODA_RGDOUT_BIT)
+#define SCODA_IRQ_BIT           (8)
+#define SCODA_IRQ_MASK          (0x1  << SCODA_IRQ_BIT)
+
+#define icodec_test_irq(icodec)   \
+    icodec_mapped_test_bits((icodec->mapped_base + RGDATA), SCODA_IRQ_MASK, (1 << SCODA_IRQ_BIT))
+
+static inline uint8_t icodec_hw_read_normal(struct jz_icodec *icodec, int reg)
+{
+    uint32_t mapped_base = icodec->mapped_base;
+    int reval;
+    int timeout = 0xfffff;
+    uint32_t flags;
+
+    while (icodec_test_rw_inval(icodec))
+    {
+        timeout--;
+        if (!timeout)
+        {
+//            rt_kprintf("icodec test_rw_inval timeout\n");
+            break;
+        }
+    }
+
+    icodec_mapped_reg_set((mapped_base + RGADW), SCODA_RGWR_MASK,(0 << SCODA_RGWR_BIT));
+    icodec_mapped_reg_set((mapped_base + RGADW), SCODA_RGADDR_MASK,(reg << SCODA_RGADDR_BIT));
+
+    reval = readl((mapped_base + RGDATA));
+    reval = readl((mapped_base + RGDATA));
+    reval = readl((mapped_base + RGDATA));
+    reval = readl((mapped_base + RGDATA));
+    reval = readl((mapped_base + RGDATA));
+    reval = ((reval & SCODA_RGDOUT_MASK) >> SCODA_RGDOUT_BIT);
+//  rt_kprintf("reg %x = %x\n", reg, reval);
+
+    return (uint8_t) reval;
+}
+
+
+static inline int icodec_hw_write_normal(struct jz_icodec *icodec, int reg, int data)
+{
+    uint32_t mapped_base = icodec->mapped_base;
+    int ret = 0;
+    int timeout = 0xfffff;
+    uint32_t flags;
+
+
+    while (icodec_test_rw_inval(icodec))
+    {
+        timeout--;
+        if (!timeout)
+        {
+//            rt_kprintf("icodec test_rw_inval timeout\n");
+            break;
+        }
+    }
+    icodec_mapped_reg_set((mapped_base + RGADW), SCODA_RGDIN_MASK | SCODA_RGADDR_MASK,
+                             (data << SCODA_RGDIN_BIT) | (reg << SCODA_RGADDR_BIT));
+    icodec_mapped_reg_set((mapped_base + RGADW), SCODA_RGWR_MASK ,
+                             1 << SCODA_RGWR_BIT);
+
+    if (reg != SCODA_REG_IFR && reg != SCODA_REG_IFR2)
+    {
+        ret = icodec_hw_read_normal(icodec, reg);
+        if (data != ret)
+        {
+//            rt_kprintf("icdc write reg %x err exp %x now is %x\n", reg, data, ret);
+            ret = -1;
+        }
+    }
+    return ret;
+}
+
+static int icodec_hw_write_extend(struct jz_icodec *icodec, uint8_t sreg, uint8_t sdata)
+{
+    int creg, cdata, dreg;
+    switch (sreg) {
+        case SCODA_MIX_0 ... SCODA_MIX_4:
+            creg = SCODA_REG_CR_MIX;
+            dreg = SCODA_REG_DR_MIX;
+            sreg -= (SCODA_REG_SR_TR_SRCDAC + 1);
+            break;
+        case SCODA_DAC_AGC0 ... SCODA_DAC_AGC3:
+            creg = SCODA_REG_CR_DAC_AGC;
+            dreg = SCODA_REG_DR_DAC_AGC;
+            sreg -= (SCODA_MIX_4 +1);
+            break;
+        case SCODA_DAC2_AGC0 ... SCODA_DAC2_AGC3:
+            creg = SCODA_REG_CR_DAC2;
+            dreg = SCODA_REG_DR_DAC2_AGC;
+            sreg -= (SCODA_DAC_AGC3 + 1);
+            break;
+        case SCODA_ADC_AGC0 ... SCODA_ADC_AGC4:
+            creg = SCODA_REG_CR_ADC_AGC;
+            dreg = SCODA_REG_DR_ADC_AGC;
+            sreg -= (SCODA_ADC_AGC4 + 1);
+            break;
+        default:
+            return 0;
+    }
+//    rt_kprintf("write extend : sreg: %d [0 - 4], creg: %x sdata: %d\n", sreg, creg, sdata);
+
+    cdata = (icodec_hw_read_normal(icodec,creg)&(~0x3f))|((sreg&0x3f)|0x40);
+
+    icodec_hw_write_normal(icodec, creg, cdata);
+    icodec_hw_write_normal(icodec, dreg, sdata);
+    if(sdata!=icodec_hw_read_normal(icodec,dreg))
+        return -1;
+    return 0;
+}
+
+
+static uint8_t icodec_hw_read_extend(struct jz_icodec *icodec, uint8_t sreg)
+{
+    int creg, cdata, dreg, ddata;
+    switch (sreg)
+    {
+        case SCODA_MIX_0 ... SCODA_MIX_4:
+            creg = SCODA_REG_CR_MIX;
+            dreg = SCODA_REG_DR_MIX;
+            sreg -= (SCODA_REG_SR_TR_SRCDAC + 1);
+            break;
+        case SCODA_DAC_AGC0 ... SCODA_DAC_AGC3:
+            creg = SCODA_REG_CR_DAC_AGC;
+            dreg = SCODA_REG_DR_DAC_AGC;
+            sreg -= (SCODA_MIX_4 +1);
+            break;
+        case SCODA_DAC2_AGC0 ... SCODA_DAC2_AGC3:
+            creg = SCODA_REG_CR_DAC2;
+            dreg = SCODA_REG_DR_DAC2_AGC;
+            sreg -= (SCODA_DAC_AGC3 + 1);
+            break;
+        case SCODA_ADC_AGC0 ... SCODA_ADC_AGC4:
+            creg = SCODA_REG_CR_ADC_AGC;
+            dreg = SCODA_REG_DR_ADC_AGC;
+            sreg -= (SCODA_ADC_AGC4 + 1);
+            break;
+        default:
+            return 0;
+    }
+    cdata = (icodec_hw_read_normal(icodec, creg) & (~0x7f)) | (sreg & 0x3f);
+    icodec_hw_write_normal(icodec, creg, cdata);
+    ddata = icodec_hw_read_normal(icodec, dreg);
+
+    return (uint8_t) ddata;
+}
+
+
+static inline uint8_t icodec_hw_read(struct jz_icodec *icodec, int reg)
+{
+    if (reg > SCODA_REG_SR_TR_SRCDAC)
+        return icodec_hw_read_extend(icodec, reg);
+    else
+        return icodec_hw_read_normal(icodec, reg);
+}
+static inline int icodec_hw_write(struct jz_icodec *icodec, int reg, int data)
+{
+	if (reg > SCODA_REG_SR_TR_SRCDAC)
+		return icodec_hw_write_extend(icodec, reg, data);
+	else
+		return icodec_hw_write_normal(icodec, reg, data);
+}
+
+
+#endif /* _DRV_CODEC_ICODEC_H_ */

bsp/x1000/drivers/audio/drv_dmic.c

+/*
+ * File      : drv_dmic.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-11-19     Urey         the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <drivers/audio.h>
+
+#ifdef RT_USING_FINSH
+#   include <finsh.h>
+#endif
+
+#include "board.h"
+#include "drv_gpio.h"
+#include "drv_dma.h"
+#include "drv_aic.h"
+#include "drv_clock.h"
+#include "drv_dmic.h"
+#include "dma.h"
+#include "audio_pipe.h"
+
+#define DMIC_DEBUG   0
+#if DMIC_DEBUG
+#	define DMIC_DBG(...)     rt_kprintf("[DMIC]"),rt_kprintf(__VA_ARGS__)
+#else
+#	define DMIC_DBG(...)
+#endif
+
+#define DMIC_DMA_RX_CHAN        4
+#define DMIC_FIFO_DEPTH         64
+#define JZ_DMIC_FORMATS         16
+#define JZ_DMIC_RATE            (8000)
+ALIGN(32) rt_uint32_t    _g_dmic_dma_buffer[DMIC_DMA_PAGE_NUM*DMIC_DMA_PAGE_SIZE/sizeof(rt_uint32_t)];
+static struct jz_dmic _g_jz_dmic=
+{
+    .io_base    =   DMIC_BASE,
+    .dma_buf    =   (rt_uint8_t *)_g_dmic_dma_buffer,
+    .dma_offset =   0,
+};
+
+static void dump_dmic_registers(void)
+{
+    struct jz_dmic *jz_dmic = &_g_jz_dmic;
+    rt_kprintf("DMICCR0      %p : 0x%08x\n", (jz_dmic->io_base+DMICCR0),dmic_read_reg(jz_dmic, DMICCR0));
+    rt_kprintf("DMICGCR      %p : 0x%08x\n", (jz_dmic->io_base+DMICGCR),dmic_read_reg(jz_dmic, DMICGCR));
+    rt_kprintf("DMICIMR      %p : 0x%08x\n", (jz_dmic->io_base+DMICIMR),dmic_read_reg(jz_dmic, DMICIMR));
+    rt_kprintf("DMICINTCR    %p : 0x%08x\n", (jz_dmic->io_base+DMICINTCR),dmic_read_reg(jz_dmic, DMICINTCR));
+    rt_kprintf("DMICTRICR    %p : 0x%08x\n", (jz_dmic->io_base+DMICTRICR),dmic_read_reg(jz_dmic, DMICTRICR));
+    rt_kprintf("DMICTHRH     %p : 0x%08x\n", (jz_dmic->io_base+DMICTHRH),dmic_read_reg(jz_dmic, DMICTHRH));
+    rt_kprintf("DMICTHRL     %p : 0x%08x\n", (jz_dmic->io_base+DMICTHRL),dmic_read_reg(jz_dmic, DMICTHRL));
+    rt_kprintf("DMICTRIMMAX  %p : 0x%08x\n", (jz_dmic->io_base+DMICTRIMMAX),dmic_read_reg(jz_dmic, DMICTRIMMAX));
+    rt_kprintf("DMICTRINMAX  %p : 0x%08x\n", (jz_dmic->io_base+DMICTRINMAX),dmic_read_reg(jz_dmic, DMICTRINMAX));
+    rt_kprintf("DMICDR       %p : 0x%08x\n", (jz_dmic->io_base+DMICDR),dmic_read_reg(jz_dmic, DMICDR));
+    rt_kprintf("DMICFTHR     %p : 0x%08x\n", (jz_dmic->io_base+DMICFTHR),dmic_read_reg(jz_dmic, DMICFTHR));
+    rt_kprintf("DMICFSR      %p : 0x%08x\n", (jz_dmic->io_base+DMICFSR),dmic_read_reg(jz_dmic, DMICFSR));
+    rt_kprintf("DMICCGDIS    %p : 0x%08x\n", (jz_dmic->io_base+DMICCGDIS),dmic_read_reg(jz_dmic, DMICCGDIS));
+    return;
+}
+MSH_CMD_EXPORT(dump_dmic_registers,"dump dmic regs...\n");
+
+int jz_dmic_set_rate(struct jz_dmic*   dmic, int rate)
+{
+    // rt_kprintf("rate = %d\n",rate);
+    switch (rate)
+    {
+    case 8000:
+        __dmic_set_sr_8k(dmic);
+        break;
+    case 16000:
+        __dmic_set_sr_16k(dmic);
+        break;
+    case 48000:
+        __dmic_set_sr_48k(dmic);
+        break;
+    default:
+        DMIC_DBG("dmic unsupport rate %d\n", rate);
+    }
+    return 0;
+}
+
+int jz_dmic_set_channels(struct jz_dmic*   dmic, int channels)
+{
+    if (channels > 4)
+        channels = 4;
+    if (channels <= 1)
+        channels = 1;
+
+    __dmic_set_chnum(dmic,channels - 1);
+}
+
+
+int jz_dmic_set_record_volume(struct jz_dmic*   dmic, int vol)
+{
+    if(vol >= 32)
+        vol = 31;
+    __dmic_set_gcr(dmic,vol);
+
+    dmic->record_gain = vol;
+}
+
+static void jz_dmic_dma_complete(struct rt_dma_channel *dmac, struct dma_message *msg)
+{
+    rt_base_t   level;
+    if(msg->complete_cb)
+    	msg->complete_cb(msg->complete_arg,msg->dst_addr);
+
+    /* restart DMA Job */
+    rt_dma_trans_message(dmac,msg);
+}
+
+
+void jz_dmic_start_recv(struct jz_dmic* dmic,void (*rx_callback)(void *,void *), void *rx_arg)
+{
+    rt_base_t   level;
+    rt_uint32_t i;
+    struct dma_message         message;
+    __dmic_enable_rdms(dmic);
+    __dmic_enable(dmic);
+    level = rt_hw_interrupt_disable();
+    dmic->dma_offset    = 0;
+    dmic->dma_buf       = (rt_uint8_t *)_g_dmic_dma_buffer;
+
+    for (i = 0; i < DMIC_DMA_PAGE_NUM; ++i)
+    {
+        message.src_addr    = (uint8_t *) (DMIC_BASE + DMICDR);
+        message.src_option  = RT_DMA_ADDR_FIX;
+        message.dst_addr    = (uint8_t *) (dmic->dma_buf + DMIC_DMA_PAGE_SIZE * i);
+        message.dst_option  = RT_DMA_ADDR_INC;
+        message.t_size      = DMIC_DMA_PAGE_SIZE;
+        message.t_mode      = JZDMA_REQ_DMIC_RX;
+        /* init callback */
+        message.complete_cb  = rx_callback;
+        message.complete_arg = rx_arg;
+        rt_dma_trans_message(dmic->rx_dmac,&message);
+    }
+    rt_hw_interrupt_enable(level);
+    return ;
+}
+
+void jz_dmic_stop_recv(struct jz_dmic* dmic)
+{
+    if (__dmic_is_enable_rdms(dmic))
+    {
+        __dmic_disable_rdms(dmic);
+    }
+    __dmic_disable(dmic);
+}
+
+
+void  dmic_rx_complete(void *data,void *pbuf)
+{
+    struct jz_dmic *dmic =  (struct jz_dmic *)data;
+
+    rt_device_write(RT_DEVICE(&dmic->pipe),0,pbuf,DMIC_DMA_PAGE_SIZE);
+}
+
+#define CFG_DMIC_PIPE_SIZE      (2 * 1024)
+struct jz_dmic* rt_hw_dmic_init(void)
+{
+    struct jz_dmic  *dmic = &_g_jz_dmic;
+
+    //init pipe for record
+    {
+        rt_uint8_t *buf = rt_malloc(CFG_DMIC_PIPE_SIZE);
+
+        if(buf == RT_NULL)
+        {
+            rt_kprintf("request pipe memory error\n");
+
+            return RT_NULL;
+        }
+
+        rt_audio_pipe_init(&dmic->pipe,"recdmic",RT_PIPE_FLAG_FORCE_WR | RT_PIPE_FLAG_BLOCK_RD,buf,(CFG_DMIC_PIPE_SIZE));
+
+        rt_device_open(RT_DEVICE(&dmic->pipe),RT_DEVICE_OFLAG_RDONLY);
+    }
+
+    /* GPIO config
+     * PB05 -> FUNC1  DMIC1_IN
+     * PB21 -> FUNC0  DMIC_CLK
+     * PB22 -> FUNC0  DMIC0_IN
+     * */
+    gpio_set_func(GPIO_PORT_B,GPIO_Pin_5,GPIO_FUNC_1);
+    gpio_set_func(GPIO_PORT_B,GPIO_Pin_21,GPIO_FUNC_0);
+    gpio_set_func(GPIO_PORT_B,GPIO_Pin_22,GPIO_FUNC_0);
+
+    /* enable clock */
+    dmic->clk_gate = clk_get("dmic");
+    if (dmic->clk_gate == RT_NULL)
+    {
+        DMIC_DBG("Failed to get dmic gate clock \n");
+        return RT_NULL;
+    }
+    clk_enable(dmic->clk_gate);
+
+    /*gain: 0, ..., e*/
+    __dmic_reset(dmic);
+    while (__dmic_get_reset(dmic)) ;
+
+    jz_dmic_set_rate(dmic, 8000);
+    __dmic_set_chnum(dmic,0);           //mono
+    __dmic_enable_hpf1(dmic);
+    __dmic_set_gcr(dmic, 27);
+    __dmic_mask_all_int(dmic);
+    __dmic_enable_pack(dmic);
+    __dmic_enable_sw_lr(dmic);
+    __dmic_enable_lp(dmic);
+    __dmic_disable_lp(dmic);
+    __dmic_set_request(dmic, 48);
+    __dmic_enable_hpf2(dmic);
+    __dmic_set_thr_high(dmic, 32);
+    __dmic_set_thr_low(dmic, 16);
+    __dmic_enable_tri(dmic);
+
+
+    //config DMA
+    {
+        int trigger;
+
+        /* DMA config */
+        struct dma_config config;
+        dmic->rx_dmac = rt_dma_get_channel(DMIC_DMA_RX_CHAN);
+        if (dmic->rx_dmac != RT_NULL)
+        {
+            DMIC_DBG("config dmic dma rx channel...\n");
+            config.direction        = RT_DMA_DEV_TO_MEM;
+            config.src_addr_width   = RT_DMA_BUSWIDTH_2_BYTES;
+            config.src_maxburst     = (DMIC_FIFO_DEPTH * RT_DMA_BUSWIDTH_2_BYTES) / 2;
+            config.dst_addr_width   = RT_DMA_BUSWIDTH_2_BYTES;
+            config.dst_maxburst     = (64 * 1024);
+            rt_dma_configture(dmic->rx_dmac, &config);
+
+            dmic->rx_dmac->start = RT_NULL;
+            dmic->rx_dmac->complete = jz_dmic_dma_complete;
+        }
+        trigger = config.src_maxburst / config.src_addr_width;
+        __dmic_set_request(dmic, trigger);
+    }
+
+    jz_dmic_start_recv(dmic,dmic_rx_complete,dmic);
+
+    return dmic;
+
+_error_exit:
+    __dmic_disable(dmic);
+
+    rt_audio_pipe_detach(&dmic->pipe);
+
+    clk_disable(dmic->clk_gate);
+
+    return RT_NULL;
+}
+//INIT_ENV_EXPORT(rt_hw_dmic_init);
+
+
+struct speech_wav_header
+{
+    char riff_id[4];            //"RIFF"
+    uint32_t size0;             //file len - 8
+    char wave_fmt[8];           //"WAVEfmt "
+    uint32_t size1;             //0x10
+    uint16_t fmttag;            //0x01
+    uint16_t channel;           //1
+    uint32_t samplespersec;     //8000
+    uint32_t bytepersec;        //8000 * 2
+    uint16_t blockalign;        //1 * 16 / 8
+    uint16_t bitpersamples;     //16
+    char data_id[4];            //"data"
+    uint32_t size2;             //file len - 44
+};
+
+static void speech_wav_init_header(struct speech_wav_header *header,rt_uint16_t Channels,int SamplesPerSec,int BitsPerSample)
+{
+    strcpy(header->riff_id, "RIFF");
+    header->size0           = 0;                // Final file size not known yet, write 0
+    strcpy(header->wave_fmt, "WAVEfmt ");
+    header->size1           = 16;               // Sub-chunk size, 16 for PCM
+    header->fmttag          = 1;                // AudioFormat, 1 for PCM
+    header->channel         = Channels;         // Number of channels, 1 for mono, 2 for stereo
+    header->samplespersec   = SamplesPerSec;    // Sample rate
+    header->bytepersec      = SamplesPerSec * BitsPerSample * Channels / 8; //Byte rate
+    header->blockalign      = Channels * BitsPerSample / 8;                 // Block align, NumberOfChannels*BitsPerSample/8
+    header->bitpersamples   = BitsPerSample;
+    strcpy(header->data_id, "data");
+    header->size2           = 0;
+}
+
+static void speech_wav_upgrade_size(struct speech_wav_header *header,rt_uint32_t paylodSize)
+{
+    header->size0           = paylodSize + 36;
+    header->size2           = paylodSize;
+}
+
+
+#include <finsh.h>
+#include <dfs_posix.h>
+
+rt_uint8_t  rec_buff[2048];
+int dmic_record(int samplingrates)
+{
+    struct jz_dmic  *dmic = &_g_jz_dmic;
+    rt_device_t dmic_pipe;
+    struct speech_wav_header wav_header;
+    rt_uint32_t wav_len = 0;
+    char *file_name;
+    int fd;
+    int i = 0;
+    int rdlen, wrlen;
+
+    rt_kprintf("samplingrates = %d\n",samplingrates);
+    if((samplingrates != 8000) && (samplingrates != 16000))
+    {
+        rt_kprintf("un-support this samplingrates\n");
+        return -RT_EIO;
+    }
+
+    dmic_pipe = rt_device_find("recdmic");
+    if(dmic_pipe == RT_NULL)
+    {
+        rt_kprintf("can't find the record device\n");
+        return -RT_ERROR ;
+    }
+
+    rt_kprintf("pls hold WAKE key to start record...\n");
+    while(gpio_get_value(GPIO_PORT_B, GPIO_Pin_31) == 1)
+        rt_thread_delay(100);
+    rt_kprintf("OK,start record....\n");
+    if(samplingrates == 8000)
+        file_name = "/appfs/dmic8k.wav";
+    else
+        file_name = "/appfs/dmic16k.wav";
+
+    fd = open(file_name, O_WRONLY | O_CREAT | O_TRUNC, 0);
+    if (fd < 0)
+    {
+        rt_kprintf("open file for write failed\n");
+        return -RT_EIO;
+    }
+
+    speech_wav_init_header(&wav_header,1,samplingrates,16);
+    write(fd, &wav_header, wav_len);
+
+    jz_dmic_set_rate(dmic,samplingrates);
+    wav_len = 0;
+    while(i++ < 1000)
+    {
+        rdlen = rt_device_read(dmic_pipe,0,rec_buff,sizeof(rec_buff));
+
+        wrlen = write(fd, rec_buff, rdlen);
+        if (wrlen != rdlen)
+        {
+            rt_kprintf("write data failed\n");
+            close(fd);
+
+            return -RT_EIO;
+        }
+
+        wav_len += wrlen;
+
+        if(gpio_get_value(GPIO_PORT_B, GPIO_Pin_31) == 1)
+            break;
+    }
+    rt_kprintf("record complete...\n");
+
+    //upgrage wav header
+    lseek(fd,0,SEEK_SET);
+    speech_wav_upgrade_size(&wav_header,wav_len);
+    write(fd, &wav_header, sizeof(struct speech_wav_header));
+
+    close(fd);
+
+    rt_kprintf("WAV file saved ok!\n");
+}
+FINSH_FUNCTION_EXPORT(dmic_record,dmic record test);
+
+#if 0
+int dmic_test(void)
+{
+    rt_device_t device;
+    int i = 0;
+
+    device = rt_device_find("recdmic");
+    if(device == RT_NULL)
+    {
+        rt_kprintf("can't find the record device\n");
+        return -RT_ERROR ;
+    }
+
+    audio_device_set_rate(8000);
+
+    while(i++ < 1000)
+    {
+        int     len;
+        uint8_t *sendBuf;
+
+        sendBuf = audio_device_get_buffer(&len);
+        len = rt_device_read(device,0,sendBuf,len);
+
+        audio_device_write(sendBuf,len);
+    }
+
+    rt_kprintf("dmic test complete...\n");
+
+    return 0;
+}
+MSH_CMD_EXPORT(dmic_test,dmic test ....);
+#endif

bsp/x1000/drivers/audio/drv_dmic.h

+/*
+ * drv_dmic.h
+ *
+ *  Created on: 2017111
+ *      Author: Urey
+ */
+
+#ifndef _DRV_DMIC_H_
+#define _DRV_DMIC_H_
+
+/*
+ * File      : drv_dmic.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2015-11-19     Urey         the first version
+ */
+
+#include <dma.h>
+#include "audio_pipe.h"
+#define DMIC_DMA_PAGE_SIZE  512
+#define DMIC_DMA_PAGE_NUM   RT_DMA_MAX_NODES
+struct jz_dmic
+{
+    struct rt_audio_pipe       pipe;
+    struct rt_audio_configure   record_config;
+    uint32_t    io_base;
+
+    struct clk *clk_gate;
+    struct rt_dma_channel *rx_dmac;
+
+    rt_uint8_t  *dma_buf;
+    rt_uint32_t dma_offset;
+
+    /* record */
+    int     record_gain;
+};
+static inline void dmic_write_reg(struct jz_dmic *dmic, uint32_t reg, uint32_t val)
+{
+    writel(val, dmic->io_base + reg);
+}
+static inline uint32_t dmic_read_reg(struct jz_dmic *jz_dmic, unsigned int reg)
+{
+    return readl(jz_dmic->io_base + reg);
+}
+#define dmic_set_reg(dmic, addr, val, mask, offset)\
+    do {    \
+        int tmp_val = val;                             \
+        int read_val = dmic_read_reg(dmic, addr);      \
+        read_val &= (~mask);                            \
+        tmp_val = ((tmp_val << offset) & mask);         \
+        tmp_val |= read_val;                            \
+        dmic_write_reg(dmic, addr, tmp_val);            \
+    }while(0)
+#define dmic_get_reg(dmic, addr, mask, offset)  \
+    ((dmic_read_reg(dmic, addr) & mask) >> offset)
+/*********************************************************************************************************
+**
+*********************************************************************************************************/
+#define DMICCR0     0x00
+#define DMICGCR     0x04
+#define DMICIMR     0x08
+#define DMICINTCR   0x0c
+#define DMICTRICR   0x10
+#define DMICTHRH    0x14
+#define DMICTHRL    0x18
+#define DMICTRIMMAX 0x1c
+#define DMICTRINMAX 0x20
+#define DMICDR      0x30
+#define DMICFTHR    0x34
+#define DMICFSR     0x38
+#define DMICCGDIS   0x50
+/*    DMICCR0  */
+#define DMIC_RESET      31
+#define DMIC_RESET_MASK     (0x1 << DMIC_RESET)
+#define DMIC_RESET_TRI  30
+#define DMIC_RESET_TRI_MASK (0x1 << DMIC_RESET_TRI)
+#define DMIC_CHNUM      16
+#define DMIC_CHNUM_MASK         (0x7 << DMIC_CHNUM)
+#define DMIC_UNPACK_MSB 13
+#define DMIC_UNPACK_MSB_MASK    (0x1 << DMIC_UNPACK_MSB)
+#define DMIC_UNPACK_DIS 12
+#define DMIC_UNPACK_DIS_MASK    (0x1 << DMIC_UNPACK_DIS)
+#define DMIC_SW_LR      11
+#define DMIC_SW_LR_MASK     (0x1 << DMIC_SW_LR)
+#define DMIC_SPLIT_DI   10
+#define DMIC_SPLIT_DI_MASK  (0x1 << DMIC_SPLIT_DI)
+#define DMIC_PACK_EN    8
+#define DMIC_PACK_EN_MASK   (0x1 << DMIC_PACK_EN)
+#define DMIC_SR         6
+#define DMIC_SR_MASK        (0x3 << DMIC_SR)
+#define DMIC_LP_MODE    3
+#define DMIC_LP_MODE_MASK   (0x1 << DMIC_LP_MODE)
+#define DMIC_HPF1_MODE  2
+#define DMIC_HPF1_MODE_MASK (0x1 << DMIC_HPF1_MODE)
+#define DMIC_TRI_EN     1
+#define DMIC_TRI_EN_MASK    (0x1 << DMIC_TRI_EN)
+#define DMIC_EN         0
+#define DMIC_EN_MASK        (0x1 << DMIC_EN)
+#define __dmic_reset(dmic)\
+        dmic_set_reg(dmic,DMICCR0,1,DMIC_RESET_MASK,DMIC_RESET)
+#define __dmic_get_reset(dmic)\
+        dmic_get_reg(dmic,DMICCR0,DMIC_RESET_MASK,DMIC_RESET)
+#define __dmic_reset_tri(dmic)\
+        dmic_set_reg(dmic,DMICCR0,1,DMIC_RESET_TRI_MASK,DMIC_RESET_TRI)
+#define __dmic_set_chnum(dmic,n)\
+        dmic_set_reg(dmic,DMICCR0,n,DMIC_CHNUM_MASK,DMIC_CHNUM)
+#define __dmic_get_chnum(dmic,n)\
+        dmic_set_reg(dmic,DMICCR0,DMIC_CHNUM_MASK,DMIC_CHNUM)
+#define __dmic_unpack_msb(dmic)\
+        dmic_set_reg(dmic,DMICCR0,1,DMIC_UNPACK_MSB_MASK,DMIC_UNPACK_MSB)
+#define __dmic_unpack_dis(dmic)\
+        dmic_set_reg(dmic,DMICCR0,1,DMIC_UNPACK_DIS_MASK,DMIC_UNPACK_DIS)
+#define __dmic_enable_sw_lr(dmic)\
+        dmic_set_reg(dmic,DMICCR0,1,DMIC_SW_LR_MASK,DMIC_SW_LR)
+#define __dmic_disable_sw_lr(dmic)\
+        dmic_set_reg(dmic,DMICCR0,0,DMIC_SW_LR_MASK,DMIC_SW_LR)
+#define __dmic_split(dmic)\
+        dmic_set_reg(dmic,DMICCR0,1,DMIC_SPLIT_DI_MASK,DMIC_SPLIT_DI)
+#define __dmic_enable_pack(dmic)\
+        dmic_set_reg(dmic,DMICCR0,1,DMIC_PACK_EN_MASK,DMIC_PACK_EN)
+#define __dmic_set_sr(dmic,n)\
+        dmic_set_reg(dmic,DMICCR0,n,DMIC_SR_MASK,DMIC_SR)
+#define __dmic_set_sr_8k(dmic)\
+        __dmic_set_sr(dmic,0)
+#define __dmic_set_sr_16k(dmic)\
+        __dmic_set_sr(dmic,1)
+#define __dmic_set_sr_48k(dmic)\
+        __dmic_set_sr(dmic,2)
+#define __dmic_enable_lp(dmic)\
+        dmic_set_reg(dmic,DMICCR0,1,DMIC_LP_MODE_MASK,DMIC_LP_MODE)
+#define __dmic_disable_lp(dmic)\
+        dmic_set_reg(dmic,DMICCR0,0,DMIC_LP_MODE_MASK,DMIC_LP_MODE)
+#define __dmic_enable_hpf1(dmic)\
+        dmic_set_reg(dmic,DMICCR0,1,DMIC_HPF1_MODE_MASK,DMIC_HPF1_MODE)
+#define __dmic_disable_hpf1(dmic)\
+        dmic_set_reg(dmic,DMICCR0,0,DMIC_HPF1_MODE_MASK,DMIC_HPF1_MODE)
+#define __dmic_is_enable_tri(dmic)\
+        dmic_get_reg(dmic,DMICCR0,DMIC_TRI_EN_MASK,DMIC_TRI_EN)
+#define __dmic_enable_tri(dmic)\
+        dmic_set_reg(dmic,DMICCR0,1,DMIC_TRI_EN_MASK,DMIC_TRI_EN)
+#define __dmic_disable_tri(dmic)\
+        dmic_set_reg(dmic,DMICCR0,0,DMIC_TRI_EN_MASK,DMIC_TRI_EN)
+#define __dmic_is_enable(dmic)\
+        dmic_get_reg(dmic,DMICCR0,DMIC_EN_MASK,DMIC_EN)
+#define __dmic_enable(dmic)\
+        dmic_set_reg(dmic,DMICCR0,1,DMIC_EN_MASK,DMIC_EN)
+#define __dmic_disable(dmic)\
+        dmic_set_reg(dmic,DMICCR0,0,DMIC_EN_MASK,DMIC_EN)
+/*DMICGCR*/
+#define DMIC_GCR    0
+#define DMIC_GCR_MASK   (0Xf << DMIC_GCR)
+#define __dmic_set_gcr(dmic,n)\
+        dmic_set_reg(dmic, DMICGCR, n, DMIC_GCR_MASK,DMIC_GCR)
+/* DMICIMR */
+#define DMIC_FIFO_TRIG_MASK 5
+#define DMIC_FIFO_TRIG_MSK      (1 << DMIC_FIFO_TRIG_MASK)
+#define DMIC_WAKE_MASK  4
+#define DMIC_WAKE_MSK       (1 << DMIC_WAKE_MASK)
+#define DMIC_EMPTY_MASK 3
+#define DMIC_EMPTY_MSK      (1 << DMIC_EMPTY_MASK)
+#define DMIC_FULL_MASK  2
+#define DMIC_FULL_MSK       (1 << DMIC_FULL_MASK)
+#define DMIC_PRERD_MASK 1
+#define DMIC_PRERD_MSK      (1 << DMIC_PRERD_MASK)
+#define DMIC_TRI_MASK   0
+#define DMIC_TRI_MSK        (1 << DMIC_TRI_MASK)
+#define __dmic_mask_all_int(dmic)\
+    dmic_set_reg(dmic,DMICIMR, 0x3f, 0x3f, 0)
+/*DMICINTCR*/
+#define DMIC_FIFO_TRIG_FLAG 4
+#define DMIC_FIFO_TRIG_FLAG_MASK        (1 << DMIC_WAKE_FLAG)
+#define DMIC_WAKE_FLAG  4
+#define DMIC_WAKE_FLAG_MASK     (1 << DMIC_WAKE_FLAG)
+#define DMIC_EMPTY_FLAG 3
+#define DMIC_EMPTY_FLAG_MASK    (1 << DMIC_EMPTY_FLAG)
+#define DMIC_FULL_FLAG  2
+#define DMIC_FULL_FLAG_MASK     (1 << DMIC_FULL_FLAG)
+#define DMIC_PRERD_FLAG 1
+#define DMIC_PRERD_FLAG_MASK    (1 << DMIC_PRERD_FLAG)
+#define DMIC_TRI_FLAG   0
+#define DMIC_TRI_FLAG_MASK      (1 << DMIC_TRI_FLAG)
+/*DMICTRICR*/
+#define DMIC_TRI_MODE   16
+#define DMIC_TRI_MODE_MASK  (0xf << DMIC_TRI_MODE)
+#define DMIC_TRI_DEBUG  4
+#define DMIC_TRI_DEBUG_MASK (0x1 << DMIC_TRI_DEBUG)
+#define DMIC_HPF2_EN    3
+#define DMIC_HPF2_EN_MASK (0x1 << DMIC_HPF2_EN)
+#define DMIC_PREFETCH   1
+#define DMIC_PREFETCH_MASK  (0x3 << DMIC_PREFETCH)
+#define DMIC_TRI_CLR    0
+#define DMIC_TRI_CLR_MASK   (0x1 << DMIC_TRI_CLR)
+#define __dmic_enable_hpf2(dmic) \
+    dmic_set_reg(dmic, DMICTRICR, 1, DMIC_HPF2_EN_MASK, DMIC_HPF2_EN)
+#define __dmic_disable_hpf2(dmic)    \
+    dmic_set_reg(dmic, DMICTRICR, 0, DMIC_HPF2_EN_MASK, DMIC_HPF2_EN)
+/*DMICTHRH*/
+#define DMIC_THR_H 0
+#define DMIC_THR_H_MASK (0xfffff << DMIC_THR_H)
+#define __dmic_set_thr_high(dmic,n)  \
+    dmic_set_reg(dmic, DMICTHRH, n, DMIC_THR_H_MASK, DMIC_THR_H)
+/*DMICTHRL*/
+#define DMIC_THR_L 0
+#define DMIC_THR_L_MASK (0xfffff << DMIC_THR_L)
+#define __dmic_set_thr_low(dmic,n)   \
+    dmic_set_reg(dmic, DMICTHRL, n, DMIC_THR_L_MASK, DMIC_THR_L)
+/* DMICTRIMMAX */
+#define DMIC_M_MAX  0
+#define DMIC_M_MAX_MASK (0xffffff << DMIC_M_MAX)
+/* DMICTRINMAX */
+#define DMIC_N_MAX  0
+#define DMIC_N_MAX_MASK (0xffff << DMIC_N_MAX)
+/* DMICFTHR */
+#define DMIC_RDMS   31
+#define DMIC_RDMS_MASK  (0x1 << DMIC_RDMS)
+#define DMIC_FIFO_THR   0
+#define DMIC_FIFO_THR_MASK  (0x3f << DMIC_FIFO_THR)
+#define __dmic_is_enable_rdms(dmic)\
+    dmic_get_reg(dmic, DMICFTHR,DMIC_RDMS_MASK,DMIC_RDMS)
+#define __dmic_enable_rdms(dmic)\
+    dmic_set_reg(dmic, DMICFTHR,1,DMIC_RDMS_MASK,DMIC_RDMS)
+#define __dmic_disable_rdms(dmic)\
+    dmic_set_reg(dmic, DMICFTHR,1,DMIC_RDMS_MASK,DMIC_RDMS)
+#define __dmic_set_request(dmic,n)   \
+    dmic_set_reg(dmic, DMICFTHR, n, DMIC_FIFO_THR_MASK, DMIC_FIFO_THR)
+/*DMICFSR*/
+#define DMIC_FULLS      19
+#define DMIC_FULLS_MASK (0x1 << DMIC_FULLS)
+#define DMIC_TRIGS      18
+#define DMIC_TRIGS_MASK (0x1 << DMIC_TRIGS)
+#define DMIC_PRERDS     17
+#define DMIC_PRERDS_MASK    (0x1 << DMIC_PRERDS)
+#define DMIC_EMPTYS     16
+#define DMIC_EMPTYS_MASK    (0x1 << DMIC_EMPTYS)
+#define DMIC_FIFO_LVL   0
+#define DMIC_FIFO_LVL_MASK  (0x3f << DMIC_FIFO_LVL)
+/*********************************************************************************************************
+**
+*********************************************************************************************************/
+struct jz_dmic* rt_hw_dmic_init(void);
+int jz_dmic_set_rate(struct jz_dmic*   dmic, int rate);
+int jz_dmic_set_gain(struct jz_dmic*   dmic, int vol);
+int jz_dmic_set_channels(struct jz_dmic*   dmic, int channels);
+
+#endif /* _DRV_DMIC_H_ */

bsp/x1000/driver/board.c → bsp/x1000/drivers/board.c

@@ -24,6 +24,7 @@
 
 #include <rthw.h>
 #include <rtthread.h>
+#include <string.h>
 
 #include "board.h"
 #include "drv_clock.h"
@@ -32,12 +33,38 @@
 
 extern void rt_hw_cache_init(void);
 
+extern unsigned char _iramcopy;
+extern unsigned char _iramstart;
+extern unsigned char _iramend;
+
+#ifdef RT_USING_CPLUSPLUS
+int cplusplus_system_init(void)
+{
+    typedef void (*pfunc) ();
+    extern pfunc __ctors_start__[];
+    extern pfunc __ctors_end__[];
+    pfunc *p;
+    for (p = __ctors_end__ - 2; p > __ctors_start__; )
+    {
+        (*p)();
+        p--;
+    }
+    return 0;
+}
+#endif
+
 void rt_hw_board_init(void)
 {
+    memcpy((void*)&_iramstart, (void*)&_iramcopy, (rt_uint32_t)&_iramend - (rt_uint32_t)&_iramstart);
+    memset((void*)&__bss_start, 0x0, (rt_uint32_t)&__bss_end - (rt_uint32_t)&__bss_start);
+
     rt_hw_cache_init();
+    rt_hw_exception_init();
+
     /* init hardware interrupt */
     rt_hw_interrupt_init();
     rt_hw_uart_init();
+
 #ifdef RT_USING_CONSOLE
     /* set console device */
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);

bsp/x1000/driver/board.h → bsp/x1000/drivers/board.h

 /*
  * File      : board.h
  * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -25,39 +25,78 @@
 #ifndef _BOARD_H_
 #define _BOARD_H_
 
+#include <rtthread.h>
 #include <stdint.h>
-
 #include "x1000.h"
 
 #define RT_USING_JZ_X1000
+#define X1000
+
+#ifdef BOARD_HALLEY2_FIR
+#include "board/halley2_fir/board_halley2_fir.h"
+#endif
 
-// #define BOARD_PHOENIX
-// #define BOARD_CANNA
+#ifdef BOARD_HALLEY2_REALBOARD
+#include "board/halley2_realboard/board_halley2_readboard.h"
+#endif
+
+#ifdef BOARD_HALLEY2_REALBOARD_V2
+#include "board/halley2_realboard_v2/board_halley2_readboard_v2.h"
+#endif
+
+#ifdef BOARD_HALLEY2_IDELAN
+#include "board/halley2_idelan/board_halley2_idelan.h"
+#endif
+
+#ifdef BOARD_HALLEY2
+#include "board/halley2/board_halley2.h"
+#endif
 
 #ifdef BOARD_PHOENIX
-#define RT_USING_EMAC
+#include "board/phoenix/board_phoenix.h"
 #endif
 
-/*********************************************************************************************************
-**   Clock for Board
-*********************************************************************************************************/
+#ifdef BOARD_CANNA
+#include "board/canna/board_canna.h"
+#endif
+
+/*
+ * Clock setting
+ */
 #define BOARD_EXTAL_CLK     24000000
 #define BOARD_RTC_CLK       32768
 #define BOARD_CPU_CLK       (1008 * 1000 * 1000UL)
 
+#define BOARD_APLL_FREQ     1008000000  /*If APLL not use mast be set 0*/
+#define BOARD_MPLL_FREQ     600000000   /*If MPLL not use mast be set 0*/
 
-/*********************************************************************************************************
-**   HEAP Setting
-*********************************************************************************************************/
+/*
+ * Heap setting
+ */
 extern unsigned char __bss_start;
 extern unsigned char __bss_end;
 
 #define RT_HW_HEAP_BEGIN    (void*)&__bss_end
 #define RT_HW_HEAP_END      (void*)(0x80000000 + 32 * 1024 * 1024)
 
-/*********************************************************************************************************
-**   UART Setting
-*********************************************************************************************************/
-#define RT_USING_UART2
+/* HW EVENT */
+#define EVENT_NONE                  0x0000
 
-#endif
+#define EVENT_TYPE_MSK              0xFF00
+#define EVENT_VALUE_MSK             0x00FF
+
+#define EVENT_LINEIN                0x0100
+#define EVENT_LINEIN_INSERT         0x0101
+#define EVENT_LINEIN_REMOVE         0x0102
+#define EVENT_LINEIN_SHUTDOWN       0x0103
+
+#define EVENT_BAT                   0x0200
+#define EVENT_BAT_ALONE             0x0201
+#define EVENT_BAT_CHARGE_IN         0x0202
+#define EVENT_BAT_CHARGE_FULL       0x0203
+#define EVENT_BAT_ERROR             0x0204
+
+#define EVENT_KEY_DOWN              0x0300
+#define EVENT_KEY_UP                0x0400
+
+#endif /* _BOARD_H_ */

bsp/x1000/drivers/board/canna/board_canna.h

+#ifndef BOARD_CANNA_H__
+#define BOARD_CANNA_H__
+
+
+#endif
+

bsp/x1000/drivers/board/halley2/board_halley2.h

+#ifndef BOARD_HALLEY2_H__
+#define BOARD_HALLEY2_H__
+
+#define LCD_RST_PORT            GPIO_PORT_D
+#define LCD_RST_PIN             GPIO_Pin_0
+
+#define LCD_BLPWM_PORT          GPIO_PORT_C
+#define LCD_BLPWM_PIN           GPIO_Pin_25
+
+#define LCD_BLEN_PORT           GPIO_PORT_A
+#define LCD_BLEN_PIN            GPIO_Pin_25
+
+#endif
+

bsp/x1000/drivers/board/halley2_fir/board_halley2_fir.h

+#ifndef BOARD_HALLEY2_IDELAN_H__
+#define BOARD_HALLEY2_IDELAN_H__
+
+#define AUDIO_SHUTDOWN_PORT     GPIO_PORT_B
+#define AUDIO_SHUTDOWN_PIN      GPIO_Pin_7
+#define AUDIO_SHUTDOWN_MUTE     1
+
+/*
+ * IO LCD
+ */
+#define LCD_PWEN_PORT           GPIO_PORT_B
+#define LCD_PWEN_PIN            GPIO_Pin_19 //原理图不对，实际连接到LCD_TE
+
+#define LCD_RST_PORT            GPIO_PORT_B
+#define LCD_RST_PIN             GPIO_Pin_14
+
+#define LCD_BL_PORT             GPIO_PORT_B
+#define LCD_BL_PIN              GPIO_Pin_9
+
+/*
+ * IO Touch
+ */
+#define TP_INT_PORT             GPIO_PORT_B
+#define TP_INT_PIN              GPIO_Pin_11
+
+#define TP_RST_PORT             GPIO_PORT_B
+#define TP_RST_PIN              GPIO_Pin_12
+
+#define TP_PWEN_PORT            GPIO_PORT_B
+#define TP_PWEN_PIN             GPIO_Pin_15
+
+
+/*
+ * IO KeyBoard:
+ */
+#define KEY_WIFI_PORT           GPIO_PORT_A
+#define KEY_WIFI_PIN            GPIO_Pin_20
+
+#define KEY_BT_PORT             GPIO_PORT_A
+#define KEY_BT_PIN              GPIO_Pin_21
+
+#define KEY_VOLD_PORT           GPIO_PORT_A
+#define KEY_VOLD_PIN            GPIO_Pin_22
+
+#define KEY_VOLU_PORT           GPIO_PORT_B
+#define KEY_VOLU_PIN            GPIO_Pin_28
+
+#define KEY_WKUP_PORT           GPIO_PORT_B
+#define KEY_WKUP_PIN            GPIO_Pin_31
+
+/*
+ * IO Camera
+ */
+#define CIM_PWDN_PORT           GPIO_PORT_A
+#define CIM_PWDN_PIN            GPIO_Pin_25
+#define CIM_RST_PORT            GPIO_PORT_A
+#define CIM_RST_PIN             GPIO_Pin_24
+#define CIM_PWEN_PORT           GPIO_PORT_A
+#define CIM_PWEN_PIN            GPIO_Pin_23
+/*
+ * IO LED Config
+ */
+#define LED_BT_PORT             GPIO_PORT_B
+#define LED_BT_PIN              GPIO_Pin_6
+
+#define LED_WIFI_PORT           GPIO_PORT_B
+#define LED_WIFI_PIN            GPIO_Pin_24
+
+#define LED_ZB_PORT             GPIO_PORT_C
+#define LED_ZB_PIN              GPIO_Pin_27
+
+/*
+ * Others
+ */
+
+#define IO_IRQ_FG_PORT          GPIO_PORT_B
+#define IO_IRQ_FG_PIN           GPIO_Pin_13
+
+
+#endif

bsp/x1000/drivers/board/halley2_idelan/README_20160819.txt

+2016/08/29发布
+已知的硬件错误：
+-I2S 信号分配错误 I2SDI I2SDO反了  核心板的DO是输出  Codec的DO也是输出，核心板的DO需要接到Codec的SDI0上
+-X1 12.288晶振不焊接，R13 需要焊接，核心板提供时钟（layout的时候，晶振保留）
+-
+-layout问题，整个板子GND走线 很多实连接，手工焊接质量不保证

bsp/x1000/drivers/board/halley2_idelan/board_halley2_idelan.h

+#ifndef BOARD_HALLEY2_IDELAN_H__
+#define BOARD_HALLEY2_IDELAN_H__
+
+
+#endif

bsp/x1000/drivers/board/halley2_realboard/board_halley2_readboard.h

+#ifndef BOARD_HALLEY2_IDELAN_H__
+#define BOARD_HALLEY2_IDELAN_H__
+
+#define AUDIO_SHUTDOWN_PORT     GPIO_PORT_B
+#define AUDIO_SHUTDOWN_PIN      GPIO_Pin_6
+#define AUDIO_SHUTDOWN_MUTE     1
+
+#define LCD_RST_PORT            GPIO_PORT_C
+#define LCD_RST_PIN             GPIO_Pin_25
+
+#define LCD_BL_PORT             GPIO_PORT_B
+#define LCD_BL_PIN              GPIO_Pin_19
+
+#endif

bsp/x1000/drivers/board/halley2_realboard_v2/board_halley2_readboard_v2.h

+/*
+ * File      : board_halley2_readboard_v2.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-01-01     Urey      first version
+ */
+#ifndef DRIVER_BOARD_HALLEY2_REALBOARD_V2_BOARD_HALLEY2_READBOARD_V2_H_
+#define DRIVER_BOARD_HALLEY2_REALBOARD_V2_BOARD_HALLEY2_READBOARD_V2_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define AUDIO_SHUTDOWN_PORT     GPIO_PORT_C
+#define AUDIO_SHUTDOWN_PIN      GPIO_Pin_26
+#define AUDIO_SHUTDOWN_MUTE     0
+
+#define LCD_RST_PORT            GPIO_PORT_C
+#define LCD_RST_PIN             GPIO_Pin_23
+
+#define LCD_BL_PORT             GPIO_PORT_D
+#define LCD_BL_PIN              GPIO_Pin_1
+
+#define LCD_TP_INT_PORT         GPIO_PORT_C
+#define LCD_TP_INT_PIN          GPIO_Pin_25
+
+/* BLINK LED */
+#define BLINK_LED0_PORT         GPIO_PORT_B
+#define BLINK_LED0_PIN          GPIO_Pin_9
+
+#define BLINK_LED1_PORT         GPIO_PORT_B
+#define BLINK_LED1_PIN          GPIO_Pin_8
+
+#define BLINK_LED2_PORT         GPIO_PORT_B
+#define BLINK_LED2_PIN          GPIO_Pin_13
+
+#define BLINK_LED3_PORT         GPIO_PORT_B
+#define BLINK_LED3_PIN          GPIO_Pin_11
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DRIVER_BOARD_HALLEY2_REALBOARD_V2_BOARD_HALLEY2_READBOARD_V2_H_ */

bsp/x1000/drivers/board/phoenix/board_phoenix.h

+#ifndef BOARD_HALLEY2_H__
+#define BOARD_HALLEY2_H__
+
+#endif

bsp/x1000/drivers/board/phoenix/jz-x1000.gdbinit

+#connect to the JDI gdb server
+target remote 169.28.23.51:2823
+
+#set remote write size
+set remotewritesize fixed
+set remotewritesize 8192
+
+#load the debug image
+load
+
+#debug begin

bsp/x1000/drivers/board_led.h

+#ifndef BOARD_LED_H__
+#define BOARD_LED_H__
+
+struct led_io_def
+{
+    enum gpio_port  port;
+    enum gpio_pin   pin;
+};
+
+void rt_hw_led_off(int led);
+void rt_hw_led_on (int led);
+
+#endif

bsp/x1000/drivers/drv_i2c.h

+#ifndef DRV_I2C_H__
+#define DRV_I2C_H__
+
+#endif