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体验新版 GitCode,发现更多精彩内容 >>
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563e4989
编写于
1月 18, 2022
作者:
mysterywolf
提交者:
Bernard Xiong
1月 20, 2022
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
[asm] 解决tab和空格混用的问题
上级
c89735a3
变更
80
展开全部
隐藏空白更改
内联
并排
Showing
80 changed file
with
3558 addition
and
3558 deletion
+3558
-3558
libcpu/aarch64/common/cache.S
libcpu/aarch64/common/cache.S
+2
-2
libcpu/aarch64/common/context_gcc.S
libcpu/aarch64/common/context_gcc.S
+146
-146
libcpu/aarch64/common/cpu_gcc.S
libcpu/aarch64/common/cpu_gcc.S
+53
-53
libcpu/aarch64/common/startup_gcc.S
libcpu/aarch64/common/startup_gcc.S
+2
-2
libcpu/aarch64/common/vector_gcc.S
libcpu/aarch64/common/vector_gcc.S
+5
-5
libcpu/arc/em/contex_gcc_mw.S
libcpu/arc/em/contex_gcc_mw.S
+220
-220
libcpu/arm/AT91SAM7S/context_gcc.S
libcpu/arm/AT91SAM7S/context_gcc.S
+38
-38
libcpu/arm/AT91SAM7S/context_rvds.S
libcpu/arm/AT91SAM7S/context_rvds.S
+33
-33
libcpu/arm/AT91SAM7S/start_gcc.S
libcpu/arm/AT91SAM7S/start_gcc.S
+181
-181
libcpu/arm/AT91SAM7X/context_gcc.S
libcpu/arm/AT91SAM7X/context_gcc.S
+38
-38
libcpu/arm/AT91SAM7X/context_rvds.S
libcpu/arm/AT91SAM7X/context_rvds.S
+61
-61
libcpu/arm/AT91SAM7X/start_gcc.S
libcpu/arm/AT91SAM7X/start_gcc.S
+183
-183
libcpu/arm/am335x/cp15_gcc.S
libcpu/arm/am335x/cp15_gcc.S
+37
-37
libcpu/arm/am335x/cp15_iar.s
libcpu/arm/am335x/cp15_iar.s
+41
-41
libcpu/arm/am335x/start_gcc.S
libcpu/arm/am335x/start_gcc.S
+3
-3
libcpu/arm/am335x/start_iar.s
libcpu/arm/am335x/start_iar.s
+11
-11
libcpu/arm/am335x/vector_gcc.S
libcpu/arm/am335x/vector_gcc.S
+2
-2
libcpu/arm/arm926/context_iar.S
libcpu/arm/arm926/context_iar.S
+1
-1
libcpu/arm/arm926/start_gcc.S
libcpu/arm/arm926/start_gcc.S
+23
-23
libcpu/arm/armv6/arm_entry_gcc.S
libcpu/arm/armv6/arm_entry_gcc.S
+79
-79
libcpu/arm/common/divsi3.S
libcpu/arm/common/divsi3.S
+320
-320
libcpu/arm/cortex-a/start_gcc.S
libcpu/arm/cortex-a/start_gcc.S
+1
-1
libcpu/arm/cortex-m0/context_gcc.S
libcpu/arm/cortex-m0/context_gcc.S
+10
-10
libcpu/arm/cortex-m0/context_rvds.S
libcpu/arm/cortex-m0/context_rvds.S
+3
-3
libcpu/arm/cortex-m23/context_gcc.S
libcpu/arm/cortex-m23/context_gcc.S
+10
-10
libcpu/arm/cortex-m23/context_rvds.S
libcpu/arm/cortex-m23/context_rvds.S
+3
-3
libcpu/arm/cortex-m3/context_gcc.S
libcpu/arm/cortex-m3/context_gcc.S
+3
-3
libcpu/arm/cortex-m3/context_rvds.S
libcpu/arm/cortex-m3/context_rvds.S
+1
-1
libcpu/arm/cortex-m33/context_iar.S
libcpu/arm/cortex-m33/context_iar.S
+1
-1
libcpu/arm/cortex-m33/syscall_gcc.S
libcpu/arm/cortex-m33/syscall_gcc.S
+2
-2
libcpu/arm/cortex-m33/syscall_iar.S
libcpu/arm/cortex-m33/syscall_iar.S
+2
-2
libcpu/arm/cortex-m33/syscall_rvds.S
libcpu/arm/cortex-m33/syscall_rvds.S
+4
-4
libcpu/arm/cortex-m4/context_gcc.S
libcpu/arm/cortex-m4/context_gcc.S
+3
-3
libcpu/arm/cortex-m7/context_gcc.S
libcpu/arm/cortex-m7/context_gcc.S
+2
-2
libcpu/arm/cortex-r4/context_ccs.asm
libcpu/arm/cortex-r4/context_ccs.asm
+14
-14
libcpu/arm/cortex-r4/context_gcc.S
libcpu/arm/cortex-r4/context_gcc.S
+11
-11
libcpu/arm/cortex-r4/start_ccs.asm
libcpu/arm/cortex-r4/start_ccs.asm
+13
-13
libcpu/arm/cortex-r4/start_gcc.S
libcpu/arm/cortex-r4/start_gcc.S
+9
-9
libcpu/arm/dm36x/context_rvds.S
libcpu/arm/dm36x/context_rvds.S
+61
-61
libcpu/arm/lpc214x/context_gcc.S
libcpu/arm/lpc214x/context_gcc.S
+64
-64
libcpu/arm/lpc214x/context_rvds.S
libcpu/arm/lpc214x/context_rvds.S
+94
-94
libcpu/arm/lpc214x/startup_gcc.S
libcpu/arm/lpc214x/startup_gcc.S
+171
-171
libcpu/arm/lpc24xx/context_gcc.S
libcpu/arm/lpc24xx/context_gcc.S
+38
-38
libcpu/arm/lpc24xx/context_rvds.S
libcpu/arm/lpc24xx/context_rvds.S
+63
-63
libcpu/arm/lpc24xx/start_gcc.S
libcpu/arm/lpc24xx/start_gcc.S
+17
-17
libcpu/arm/lpc24xx/start_rvds.S
libcpu/arm/lpc24xx/start_rvds.S
+60
-60
libcpu/arm/realview-a8-vmm/start_gcc.S
libcpu/arm/realview-a8-vmm/start_gcc.S
+10
-10
libcpu/arm/realview-a8-vmm/vector_gcc.S
libcpu/arm/realview-a8-vmm/vector_gcc.S
+2
-2
libcpu/arm/s3c24x0/context_gcc.S
libcpu/arm/s3c24x0/context_gcc.S
+38
-38
libcpu/arm/s3c24x0/context_rvds.S
libcpu/arm/s3c24x0/context_rvds.S
+61
-61
libcpu/arm/s3c24x0/start_gcc.S
libcpu/arm/s3c24x0/start_gcc.S
+273
-273
libcpu/arm/s3c24x0/start_rvds.S
libcpu/arm/s3c24x0/start_rvds.S
+13
-13
libcpu/arm/s3c44b0/context_gcc.S
libcpu/arm/s3c44b0/context_gcc.S
+38
-38
libcpu/arm/s3c44b0/context_rvds.S
libcpu/arm/s3c44b0/context_rvds.S
+61
-61
libcpu/arm/s3c44b0/start_gcc.S
libcpu/arm/s3c44b0/start_gcc.S
+165
-165
libcpu/arm/sep4020/context_rvds.S
libcpu/arm/sep4020/context_rvds.S
+61
-61
libcpu/arm/zynqmp-r5/context_gcc.S
libcpu/arm/zynqmp-r5/context_gcc.S
+4
-4
libcpu/arm/zynqmp-r5/start_gcc.S
libcpu/arm/zynqmp-r5/start_gcc.S
+37
-37
libcpu/arm/zynqmp-r5/vector_gcc.S
libcpu/arm/zynqmp-r5/vector_gcc.S
+2
-2
libcpu/avr32/uc3/context_gcc.S
libcpu/avr32/uc3/context_gcc.S
+36
-36
libcpu/ia32/context_gcc.S
libcpu/ia32/context_gcc.S
+43
-43
libcpu/ia32/hdisr_gcc.S
libcpu/ia32/hdisr_gcc.S
+61
-61
libcpu/ia32/start_gcc.S
libcpu/ia32/start_gcc.S
+44
-44
libcpu/ia32/trapisr_gcc.S
libcpu/ia32/trapisr_gcc.S
+45
-45
libcpu/m16c/m16c62p/context_gcc.S
libcpu/m16c/m16c62p/context_gcc.S
+9
-9
libcpu/m16c/m16c62p/context_iar.S
libcpu/m16c/m16c62p/context_iar.S
+5
-5
libcpu/m16c/m16c62p/context_iar.asm
libcpu/m16c/m16c62p/context_iar.asm
+5
-5
libcpu/mips/common/context_gcc.S
libcpu/mips/common/context_gcc.S
+2
-2
libcpu/mips/common/entry_gcc.S
libcpu/mips/common/entry_gcc.S
+16
-16
libcpu/mips/common/exception_gcc.S
libcpu/mips/common/exception_gcc.S
+17
-17
libcpu/mips/gs232/cache_gcc.S
libcpu/mips/gs232/cache_gcc.S
+86
-86
libcpu/mips/gs232/cpuinit_gcc.S
libcpu/mips/gs232/cpuinit_gcc.S
+3
-3
libcpu/mips/pic32/context_gcc.S
libcpu/mips/pic32/context_gcc.S
+11
-11
libcpu/risc-v/e310/interrupt_gcc.S
libcpu/risc-v/e310/interrupt_gcc.S
+2
-2
libcpu/risc-v/k210/startup_gcc.S
libcpu/risc-v/k210/startup_gcc.S
+2
-2
libcpu/risc-v/rv32m1/interrupt_gcc.S
libcpu/risc-v/rv32m1/interrupt_gcc.S
+2
-2
libcpu/risc-v/virt64/startup_gcc.S
libcpu/risc-v/virt64/startup_gcc.S
+3
-3
libcpu/ti-dsp/c28x/context.s
libcpu/ti-dsp/c28x/context.s
+59
-59
libcpu/unicore32/sep6200/context_gcc.S
libcpu/unicore32/sep6200/context_gcc.S
+41
-41
libcpu/unicore32/sep6200/start_gcc.S
libcpu/unicore32/sep6200/start_gcc.S
+162
-162
未找到文件。
libcpu/aarch64/common/cache.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
202
1
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
202
2
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -199,4 +199,4 @@ __asm_invalidate_icache_all:
.
globl
__asm_flush_l3_cache
__asm_flush_l3_cache
:
mov
x0
,
#
0
/*
return
status
as
success
*/
ret
\ No newline at end of file
ret
libcpu/aarch64/common/context_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
202
1
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
202
2
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -23,9 +23,9 @@
*/
.
globl
rt_hw_gtimer_enable
rt_hw_gtimer_enable
:
MOV
X0
,#
1
MSR
CNTP_CTL_EL0
,
X0
RET
MOV
X0
,#
1
MSR
CNTP_CTL_EL0
,
X0
RET
/*
*
disable
gtimer
...
...
@@ -40,183 +40,183 @@ rt_hw_gtimer_disable:
*/
.
globl
rt_hw_set_gtimer_val
rt_hw_set_gtimer_val
:
MSR
CNTP_TVAL_EL0
,
X0
RET
MSR
CNTP_TVAL_EL0
,
X0
RET
/*
*
get
gtimer
CNTP_TVAL_EL0
value
*/
.
globl
rt_hw_get_gtimer_val
rt_hw_get_gtimer_val
:
MRS
X0
,
CNTP_TVAL_EL0
RET
MRS
X0
,
CNTP_TVAL_EL0
RET
.
globl
rt_hw_get_cntpct_val
rt_hw_get_cntpct_val
:
MRS
X0
,
CNTPCT_EL0
RET
MRS
X0
,
CNTPCT_EL0
RET
/*
*
get
gtimer
frq
value
*/
.
globl
rt_hw_get_gtimer_frq
rt_hw_get_gtimer_frq
:
MRS
X0
,
CNTFRQ_EL0
RET
MRS
X0
,
CNTFRQ_EL0
RET
.
macro
SAVE_CONTEXT
/
*
Save
the
entire
context
.
*/
SAVE_FPU
SP
STP
X0
,
X1
,
[
SP
,
#-
0x10
]!
STP
X2
,
X3
,
[
SP
,
#-
0x10
]!
STP
X4
,
X5
,
[
SP
,
#-
0x10
]!
STP
X6
,
X7
,
[
SP
,
#-
0x10
]!
STP
X8
,
X9
,
[
SP
,
#-
0x10
]!
STP
X10
,
X11
,
[
SP
,
#-
0x10
]!
STP
X12
,
X13
,
[
SP
,
#-
0x10
]!
STP
X14
,
X15
,
[
SP
,
#-
0x10
]!
STP
X16
,
X17
,
[
SP
,
#-
0x10
]!
STP
X18
,
X19
,
[
SP
,
#-
0x10
]!
STP
X20
,
X21
,
[
SP
,
#-
0x10
]!
STP
X22
,
X23
,
[
SP
,
#-
0x10
]!
STP
X24
,
X25
,
[
SP
,
#-
0x10
]!
STP
X26
,
X27
,
[
SP
,
#-
0x10
]!
STP
X28
,
X29
,
[
SP
,
#-
0x10
]!
STP
X0
,
X1
,
[
SP
,
#-
0x10
]!
STP
X2
,
X3
,
[
SP
,
#-
0x10
]!
STP
X4
,
X5
,
[
SP
,
#-
0x10
]!
STP
X6
,
X7
,
[
SP
,
#-
0x10
]!
STP
X8
,
X9
,
[
SP
,
#-
0x10
]!
STP
X10
,
X11
,
[
SP
,
#-
0x10
]!
STP
X12
,
X13
,
[
SP
,
#-
0x10
]!
STP
X14
,
X15
,
[
SP
,
#-
0x10
]!
STP
X16
,
X17
,
[
SP
,
#-
0x10
]!
STP
X18
,
X19
,
[
SP
,
#-
0x10
]!
STP
X20
,
X21
,
[
SP
,
#-
0x10
]!
STP
X22
,
X23
,
[
SP
,
#-
0x10
]!
STP
X24
,
X25
,
[
SP
,
#-
0x10
]!
STP
X26
,
X27
,
[
SP
,
#-
0x10
]!
STP
X28
,
X29
,
[
SP
,
#-
0x10
]!
MRS
X28
,
FPCR
MRS
X29
,
FPSR
STP
X28
,
X29
,
[
SP
,
#-
0x10
]!
STP
X30
,
XZR
,
[
SP
,
#-
0x10
]!
MRS
X0
,
CurrentEL
CMP
X0
,
0xc
B.EQ
3
f
CMP
X0
,
0x8
B.EQ
2
f
CMP
X0
,
0x4
B.EQ
1
f
B
.
STP
X30
,
XZR
,
[
SP
,
#-
0x10
]!
MRS
X0
,
CurrentEL
CMP
X0
,
0xc
B.EQ
3
f
CMP
X0
,
0x8
B.EQ
2
f
CMP
X0
,
0x4
B.EQ
1
f
B
.
3
:
MRS
X3
,
SPSR_EL3
MRS
X3
,
SPSR_EL3
/
*
Save
the
ELR
.
*/
MRS
X2
,
ELR_EL3
B
0
f
MRS
X2
,
ELR_EL3
B
0
f
2
:
MRS
X3
,
SPSR_EL2
MRS
X3
,
SPSR_EL2
/
*
Save
the
ELR
.
*/
MRS
X2
,
ELR_EL2
B
0
f
MRS
X2
,
ELR_EL2
B
0
f
1
:
MRS
X3
,
SPSR_EL1
MRS
X2
,
ELR_EL1
B
0
f
MRS
X3
,
SPSR_EL1
MRS
X2
,
ELR_EL1
B
0
f
0
:
STP
X2
,
X3
,
[
SP
,
#-
0x10
]!
STP
X2
,
X3
,
[
SP
,
#-
0x10
]!
MOV
X0
,
SP
/*
Move
SP
into
X0
for
saving
.
*/
MOV
X0
,
SP
/*
Move
SP
into
X0
for
saving
.
*/
.
endm
.
macro
SAVE_CONTEXT_T
/
*
Save
the
entire
context
.
*/
SAVE_FPU
SP
STP
X0
,
X1
,
[
SP
,
#-
0x10
]!
STP
X2
,
X3
,
[
SP
,
#-
0x10
]!
STP
X4
,
X5
,
[
SP
,
#-
0x10
]!
STP
X6
,
X7
,
[
SP
,
#-
0x10
]!
STP
X8
,
X9
,
[
SP
,
#-
0x10
]!
STP
X10
,
X11
,
[
SP
,
#-
0x10
]!
STP
X12
,
X13
,
[
SP
,
#-
0x10
]!
STP
X14
,
X15
,
[
SP
,
#-
0x10
]!
STP
X16
,
X17
,
[
SP
,
#-
0x10
]!
STP
X18
,
X19
,
[
SP
,
#-
0x10
]!
STP
X20
,
X21
,
[
SP
,
#-
0x10
]!
STP
X22
,
X23
,
[
SP
,
#-
0x10
]!
STP
X24
,
X25
,
[
SP
,
#-
0x10
]!
STP
X26
,
X27
,
[
SP
,
#-
0x10
]!
STP
X28
,
X29
,
[
SP
,
#-
0x10
]!
STP
X0
,
X1
,
[
SP
,
#-
0x10
]!
STP
X2
,
X3
,
[
SP
,
#-
0x10
]!
STP
X4
,
X5
,
[
SP
,
#-
0x10
]!
STP
X6
,
X7
,
[
SP
,
#-
0x10
]!
STP
X8
,
X9
,
[
SP
,
#-
0x10
]!
STP
X10
,
X11
,
[
SP
,
#-
0x10
]!
STP
X12
,
X13
,
[
SP
,
#-
0x10
]!
STP
X14
,
X15
,
[
SP
,
#-
0x10
]!
STP
X16
,
X17
,
[
SP
,
#-
0x10
]!
STP
X18
,
X19
,
[
SP
,
#-
0x10
]!
STP
X20
,
X21
,
[
SP
,
#-
0x10
]!
STP
X22
,
X23
,
[
SP
,
#-
0x10
]!
STP
X24
,
X25
,
[
SP
,
#-
0x10
]!
STP
X26
,
X27
,
[
SP
,
#-
0x10
]!
STP
X28
,
X29
,
[
SP
,
#-
0x10
]!
MRS
X28
,
FPCR
MRS
X29
,
FPSR
STP
X28
,
X29
,
[
SP
,
#-
0x10
]!
STP
X30
,
XZR
,
[
SP
,
#-
0x10
]!
MRS
X0
,
CurrentEL
CMP
X0
,
0xc
B.EQ
3
f
CMP
X0
,
0x8
B.EQ
2
f
CMP
X0
,
0x4
B.EQ
1
f
B
.
STP
X30
,
XZR
,
[
SP
,
#-
0x10
]!
MRS
X0
,
CurrentEL
CMP
X0
,
0xc
B.EQ
3
f
CMP
X0
,
0x8
B.EQ
2
f
CMP
X0
,
0x4
B.EQ
1
f
B
.
3
:
MOV
X3
,
0x0d
MOV
X2
,
X30
B
0
f
MOV
X3
,
0x0d
MOV
X2
,
X30
B
0
f
2
:
MOV
X3
,
0x09
MOV
X2
,
X30
B
0
f
MOV
X3
,
0x09
MOV
X2
,
X30
B
0
f
1
:
MOV
X3
,
0x05
MOV
X2
,
X30
B
0
f
MOV
X3
,
0x05
MOV
X2
,
X30
B
0
f
0
:
STP
X2
,
X3
,
[
SP
,
#-
0x10
]!
STP
X2
,
X3
,
[
SP
,
#-
0x10
]!
MOV
X0
,
SP
/*
Move
SP
into
X0
for
saving
.
*/
MOV
X0
,
SP
/*
Move
SP
into
X0
for
saving
.
*/
.
endm
.
macro
RESTORE_CONTEXT
/
*
Set
the
SP
to
point
to
the
stack
of
the
task
being
restored
.
*/
MOV
SP
,
X0
LDP
X2
,
X3
,
[
SP
],
#
0x10
/*
SPSR
and
ELR
.
*/
MRS
X0
,
CurrentEL
CMP
X0
,
0xc
B.EQ
3
f
CMP
X0
,
0x8
B.EQ
2
f
CMP
X0
,
0x4
B.EQ
1
f
B
.
MOV
SP
,
X0
LDP
X2
,
X3
,
[
SP
],
#
0x10
/*
SPSR
and
ELR
.
*/
MRS
X0
,
CurrentEL
CMP
X0
,
0xc
B.EQ
3
f
CMP
X0
,
0x8
B.EQ
2
f
CMP
X0
,
0x4
B.EQ
1
f
B
.
3
:
MSR
SPSR_EL3
,
X3
MSR
ELR_EL3
,
X2
B
0
f
MSR
SPSR_EL3
,
X3
MSR
ELR_EL3
,
X2
B
0
f
2
:
MSR
SPSR_EL2
,
X3
MSR
ELR_EL2
,
X2
B
0
f
MSR
SPSR_EL2
,
X3
MSR
ELR_EL2
,
X2
B
0
f
1
:
MSR
SPSR_EL1
,
X3
MSR
ELR_EL1
,
X2
B
0
f
MSR
SPSR_EL1
,
X3
MSR
ELR_EL1
,
X2
B
0
f
0
:
LDP
X30
,
XZR
,
[
SP
],
#
0x10
LDP
X30
,
XZR
,
[
SP
],
#
0x10
LDP
X28
,
X29
,
[
SP
],
#
0x10
MSR
FPCR
,
X28
MSR
FPSR
,
X29
LDP
X28
,
X29
,
[
SP
],
#
0x10
LDP
X26
,
X27
,
[
SP
],
#
0x10
LDP
X24
,
X25
,
[
SP
],
#
0x10
LDP
X22
,
X23
,
[
SP
],
#
0x10
LDP
X20
,
X21
,
[
SP
],
#
0x10
LDP
X18
,
X19
,
[
SP
],
#
0x10
LDP
X16
,
X17
,
[
SP
],
#
0x10
LDP
X14
,
X15
,
[
SP
],
#
0x10
LDP
X12
,
X13
,
[
SP
],
#
0x10
LDP
X10
,
X11
,
[
SP
],
#
0x10
LDP
X8
,
X9
,
[
SP
],
#
0x10
LDP
X6
,
X7
,
[
SP
],
#
0x10
LDP
X4
,
X5
,
[
SP
],
#
0x10
LDP
X2
,
X3
,
[
SP
],
#
0x10
LDP
X0
,
X1
,
[
SP
],
#
0x10
LDP
X28
,
X29
,
[
SP
],
#
0x10
LDP
X26
,
X27
,
[
SP
],
#
0x10
LDP
X24
,
X25
,
[
SP
],
#
0x10
LDP
X22
,
X23
,
[
SP
],
#
0x10
LDP
X20
,
X21
,
[
SP
],
#
0x10
LDP
X18
,
X19
,
[
SP
],
#
0x10
LDP
X16
,
X17
,
[
SP
],
#
0x10
LDP
X14
,
X15
,
[
SP
],
#
0x10
LDP
X12
,
X13
,
[
SP
],
#
0x10
LDP
X10
,
X11
,
[
SP
],
#
0x10
LDP
X8
,
X9
,
[
SP
],
#
0x10
LDP
X6
,
X7
,
[
SP
],
#
0x10
LDP
X4
,
X5
,
[
SP
],
#
0x10
LDP
X2
,
X3
,
[
SP
],
#
0x10
LDP
X0
,
X1
,
[
SP
],
#
0x10
RESTORE_FPU
SP
ERET
...
...
@@ -264,7 +264,7 @@ rt_hw_context_switch_to:
BL
rt_cpus_lock_status_restore
LDR
X0
,
[
SP
],
#
0x8
#endif /*RT_USING_SMP*/
LDR
X0
,
[
X0
]
LDR
X0
,
[
X0
]
RESTORE_CONTEXT
.
text
...
...
@@ -289,14 +289,14 @@ rt_hw_context_switch:
LDP
X0
,
X1
,
[
SP
],
#
0x10
#endif /*RT_USING_SMP*/
MOV
X8
,
X0
MOV
X9
,
X1
MOV
X8
,
X0
MOV
X9
,
X1
SAVE_CONTEXT_T
STR
X0
,
[
X8
]
//
store
sp
in
preempted
tasks
TCB
LDR
X0
,
[
X9
]
//
get
new
task
stack
pointer
STR
X0
,
[
X8
]
//
store
sp
in
preempted
tasks
TCB
LDR
X0
,
[
X9
]
//
get
new
task
stack
pointer
RESTORE_CONTEXT
/*
...
...
@@ -320,17 +320,17 @@ rt_hw_context_switch_interrupt:
MOV
X0
,
SP
RESTORE_CONTEXT
#else
LDR
X2
,
=
rt_thread_switch_interrupt_flag
LDR
X3
,
[
X2
]
CMP
X3
,
#
1
B.EQ
_reswitch
LDR
X4
,
=
rt_interrupt_from_thread
//
set
rt_interrupt_from_thread
MOV
X3
,
#
1
//
set
rt_thread_switch_interrupt_flag
to
1
STR
X0
,
[
X4
]
STR
X3
,
[
X2
]
LDR
X2
,
=
rt_thread_switch_interrupt_flag
LDR
X3
,
[
X2
]
CMP
X3
,
#
1
B.EQ
_reswitch
LDR
X4
,
=
rt_interrupt_from_thread
//
set
rt_interrupt_from_thread
MOV
X3
,
#
1
//
set
rt_thread_switch_interrupt_flag
to
1
STR
X0
,
[
X4
]
STR
X3
,
[
X2
]
_reswitch
:
LDR
X2
,
=
rt_interrupt_to_thread
//
set
rt_interrupt_to_thread
STR
X1
,
[
X2
]
LDR
X2
,
=
rt_interrupt_to_thread
//
set
rt_interrupt_to_thread
STR
X1
,
[
X2
]
RET
#endif
.
text
...
...
@@ -341,9 +341,9 @@ _reswitch:
.
globl
vector_fiq
vector_fiq
:
SAVE_CONTEXT
STP
X0
,
X1
,
[
SP
,
#-
0x10
]!
STP
X0
,
X1
,
[
SP
,
#-
0x10
]!
BL
rt_hw_trap_fiq
LDP
X0
,
X1
,
[
SP
],
#
0x10
LDP
X0
,
X1
,
[
SP
],
#
0x10
RESTORE_CONTEXT
.
globl
rt_interrupt_enter
...
...
@@ -359,13 +359,13 @@ vector_fiq:
.
globl
vector_irq
vector_irq
:
SAVE_CONTEXT
STP
X0
,
X1
,
[
SP
,
#-
0x10
]!
STP
X0
,
X1
,
[
SP
,
#-
0x10
]!
BL
rt_interrupt_enter
BL
rt_hw_trap_irq
BL
rt_interrupt_leave
LDP
X0
,
X1
,
[
SP
],
#
0x10
LDP
X0
,
X1
,
[
SP
],
#
0x10
#ifdef RT_USING_SMP
/
*
Never
reture
If
can
switch
*/
BL
rt_scheduler_do_irq_switch
...
...
@@ -374,7 +374,7 @@ vector_irq:
//
if
rt_thread_switch_interrupt_flag
set
,
jump
to
//
rt_hw_context_switch_interrupt_do
and
don
't return
LDR
X1
,
=
rt_thread_switch_interrupt_flag
LDR
X1
,
=
rt_thread_switch_interrupt_flag
LDR
X2
,
[
X1
]
CMP
X2
,
#
1
B.NE
vector_irq_exit
...
...
@@ -389,8 +389,8 @@ vector_irq:
LDR
x3
,
=
rt_interrupt_to_thread
LDR
X4
,
[
X3
]
LDR
x0
,
[
X4
]
//
get
new
task
's stack pointer
vector_irq_exit
:
vector_irq_exit
:
RESTORE_CONTEXT
//
-------------------------------------------------
...
...
libcpu/aarch64/common/cpu_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
202
0
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
202
2
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
*
Date
Author
Notes
*
2018
-
10
-
06
ZhaoXiaowei
the
first
version
*/
.
text
.
globl
rt_hw_get_current_el
rt_hw_get_current_el
:
MRS
X0
,
CurrentEL
CMP
X0
,
0xc
B.EQ
3
f
CMP
X0
,
0x8
B.EQ
2
f
CMP
X0
,
0x4
B.EQ
1
f
LDR
X0
,
=
0
B
0
f
MRS
X0
,
CurrentEL
CMP
X0
,
0xc
B.EQ
3
f
CMP
X0
,
0x8
B.EQ
2
f
CMP
X0
,
0x4
B.EQ
1
f
LDR
X0
,
=
0
B
0
f
3
:
LDR
X0
,
=
3
B
0
f
LDR
X0
,
=
3
B
0
f
2
:
LDR
X0
,
=
2
B
0
f
LDR
X0
,
=
2
B
0
f
1
:
LDR
X0
,
=
1
B
0
f
LDR
X0
,
=
1
B
0
f
0
:
RET
RET
.
globl
rt_hw_set_current_vbar
rt_hw_set_current_vbar
:
MRS
X1
,
CurrentEL
CMP
X1
,
0xc
B.EQ
3
f
CMP
X1
,
0x8
B.EQ
2
f
CMP
X1
,
0x4
B.EQ
1
f
B
0
f
MRS
X1
,
CurrentEL
CMP
X1
,
0xc
B.EQ
3
f
CMP
X1
,
0x8
B.EQ
2
f
CMP
X1
,
0x4
B.EQ
1
f
B
0
f
3
:
MSR
VBAR_EL3
,
X0
B
0
f
MSR
VBAR_EL3
,
X0
B
0
f
2
:
MSR
VBAR_EL2
,
X0
B
0
f
MSR
VBAR_EL2
,
X0
B
0
f
1
:
MSR
VBAR_EL1
,
X0
B
0
f
MSR
VBAR_EL1
,
X0
B
0
f
0
:
RET
RET
.
globl
rt_hw_set_elx_env
rt_hw_set_elx_env
:
MRS
X1
,
CurrentEL
CMP
X1
,
0xc
B.EQ
3
f
CMP
X1
,
0x8
B.EQ
2
f
CMP
X1
,
0x4
B.EQ
1
f
B
0
f
MRS
X1
,
CurrentEL
CMP
X1
,
0xc
B.EQ
3
f
CMP
X1
,
0x8
B.EQ
2
f
CMP
X1
,
0x4
B.EQ
1
f
B
0
f
3
:
MRS
X0
,
SCR_EL3
ORR
X0
,
X0
,
#
0xF
/*
SCR_EL3
.
NS|IRQ|FIQ
|
EA
*/
MSR
SCR_EL3
,
X0
B
0
f
MRS
X0
,
SCR_EL3
ORR
X0
,
X0
,
#
0xF
/*
SCR_EL3
.
NS|IRQ|FIQ
|
EA
*/
MSR
SCR_EL3
,
X0
B
0
f
2
:
MRS
X0
,
HCR_EL2
ORR
X0
,
X0
,
#
0x38
MSR
HCR_EL2
,
X0
B
0
f
MRS
X0
,
HCR_EL2
ORR
X0
,
X0
,
#
0x38
MSR
HCR_EL2
,
X0
B
0
f
1
:
B
0
f
B
0
f
0
:
RET
RET
libcpu/aarch64/common/startup_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -7,7 +7,7 @@
*
Date
Author
Notes
*/
.
global
Reset_Handler
.
global
Reset_Handler
.
section
".start"
,
"ax"
Reset_Handler
:
nop
libcpu/aarch64/common/vector_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
202
0
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
202
2
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
*
Date
Author
Notes
*
2018
-
10
-
06
ZhaoXiaowei
the
first
version
*/
.
text
.
globl
system_vectors
...
...
@@ -20,7 +20,7 @@ system_vectors:
.
org
VBAR
//
Exception
from
CurrentEL
(
EL1
)
with
SP_EL0
(
SPSEL
=
0
)
.
org
(
VBAR
+
0x00
+
0
)
B
vector_error
//
Synchronous
B
vector_error
//
Synchronous
.
org
(
VBAR
+
0x80
+
0
)
B
vector_irq
//
IRQ
/
vIRQ
.
org
(
VBAR
+
0x100
+
0
)
...
...
@@ -30,9 +30,9 @@ system_vectors:
//
Exception
from
CurrentEL
(
EL1
)
with
SP_ELn
.
org
(
VBAR
+
0x200
+
0
)
B
vector_error
//
Synchronous
B
vector_error
//
Synchronous
.
org
(
VBAR
+
0x280
+
0
)
B
vector_irq
//
IRQ
/
vIRQ
B
vector_irq
//
IRQ
/
vIRQ
.
org
(
VBAR
+
0x300
+
0
)
B
vector_fiq
//
FIQ
/
vFIQ
.
org
(
VBAR
+
0x380
+
0
)
...
...
libcpu/arc/em/contex_gcc_mw.S
浏览文件 @
563e4989
...
...
@@ -15,68 +15,68 @@
.
global
exc_nest_count
;
.
global
set_hw_stack_check
;
.
text
.
align
4
.
text
.
align
4
dispatcher
:
st
sp
,
[
r0
]
ld
sp
,
[
r1
]
st
sp
,
[
r0
]
ld
sp
,
[
r1
]
#if ARC_FEATURE_STACK_CHECK
#if ARC_FEATURE_SEC_PRESENT
lr
r0
,
[
AUX_SEC_STAT
]
bclr
r0
,
r0
,
AUX_SEC_STAT_BIT_SSC
sflag
r0
lr
r0
,
[
AUX_SEC_STAT
]
bclr
r0
,
r0
,
AUX_SEC_STAT_BIT_SSC
sflag
r0
#else
lr
r0
,
[
AUX_STATUS32
]
bclr
r0
,
r0
,
AUX_STATUS_BIT_SC
kflag
r0
lr
r0
,
[
AUX_STATUS32
]
bclr
r0
,
r0
,
AUX_STATUS_BIT_SC
kflag
r0
#endif
jl
set_hw_stack_check
jl
set_hw_stack_check
#if ARC_FEATURE_SEC_PRESENT
lr
r0
,
[
AUX_SEC_STAT
]
bset
r0
,
r0
,
AUX_SEC_STAT_BIT_SSC
sflag
r0
lr
r0
,
[
AUX_SEC_STAT
]
bset
r0
,
r0
,
AUX_SEC_STAT_BIT_SSC
sflag
r0
#else
lr
r0
,
[
AUX_STATUS32
]
bset
r0
,
r0
,
AUX_STATUS_BIT_SC
kflag
r0
lr
r0
,
[
AUX_STATUS32
]
bset
r0
,
r0
,
AUX_STATUS_BIT_SC
kflag
r0
#endif
#endif
pop
r0
j
[
r0
]
pop
r0
j
[
r0
]
/*
return
routine
when
task
dispatch
happened
in
task
context
*/
dispatch_r
:
RESTORE_NONSCRATCH_REGS
j
[
blink
]
RESTORE_NONSCRATCH_REGS
j
[
blink
]
/*
*
rt_base_t
rt_hw_interrupt_disable
()
;
*/
.
global
rt_hw_interrupt_disable
.
align
4
.
global
rt_hw_interrupt_disable
.
align
4
rt_hw_interrupt_disable
:
clri
r0
j
[
blink
]
clri
r0
j
[
blink
]
/*
*
void
rt_hw_interrupt_enable
(
rt_base_t
level
)
;
*/
.
global
rt_hw_interrupt_enable
.
align
4
.
global
rt_hw_interrupt_enable
.
align
4
rt_hw_interrupt_enable
:
seti
r0
j
[
blink
]
seti
r0
j
[
blink
]
.
global
rt_hw_context_switch_interrupt
.
align
4
.
global
rt_hw_context_switch_interrupt
.
align
4
rt_hw_context_switch_interrupt
:
st
r0
,
[
rt_interrupt_from_thread
]
st
r1
,
[
rt_interrupt_to_thread
]
mov
r0
,
1
st
r0
,
[
context_switch_reqflg
]
j
[
blink
]
st
r0
,
[
rt_interrupt_from_thread
]
st
r1
,
[
rt_interrupt_to_thread
]
mov
r0
,
1
st
r0
,
[
context_switch_reqflg
]
j
[
blink
]
/*
...
...
@@ -84,281 +84,281 @@ rt_hw_context_switch_interrupt:
*
r0
-->
from
*
r1
-->
to
*/
.
global
rt_hw_context_switch
.
align
4
.
global
rt_hw_context_switch
.
align
4
rt_hw_context_switch
:
SAVE_NONSCRATCH_REGS
mov
r2
,
dispatch_r
push
r2
b
dispatcher
SAVE_NONSCRATCH_REGS
mov
r2
,
dispatch_r
push
r2
b
dispatcher
/*
*
void
rt_hw_context_switch_to
(
rt_uint32
to
)
;
*
r0
-->
to
*/
.
global
rt_hw_context_switch_to
.
align
4
.
global
rt_hw_context_switch_to
.
align
4
rt_hw_context_switch_to
:
ld
sp
,
[
r0
]
ld
sp
,
[
r0
]
#if ARC_FEATURE_STACK_CHECK
mov
r1
,
r0
mov
r1
,
r0
#if ARC_FEATURE_SEC_PRESENT
lr
r0
,
[
AUX_SEC_STAT
]
bclr
r0
,
r0
,
AUX_SEC_STAT_BIT_SSC
sflag
r0
lr
r0
,
[
AUX_SEC_STAT
]
bclr
r0
,
r0
,
AUX_SEC_STAT_BIT_SSC
sflag
r0
#else
lr
r0
,
[
AUX_STATUS32
]
bclr
r0
,
r0
,
AUX_STATUS_BIT_SC
kflag
r0
lr
r0
,
[
AUX_STATUS32
]
bclr
r0
,
r0
,
AUX_STATUS_BIT_SC
kflag
r0
#endif
jl
set_hw_stack_check
jl
set_hw_stack_check
#if ARC_FEATURE_SEC_PRESENT
lr
r0
,
[
AUX_SEC_STAT
]
bset
r0
,
r0
,
AUX_SEC_STAT_BIT_SSC
sflag
r0
lr
r0
,
[
AUX_SEC_STAT
]
bset
r0
,
r0
,
AUX_SEC_STAT_BIT_SSC
sflag
r0
#else
lr
r0
,
[
AUX_STATUS32
]
bset
r0
,
r0
,
AUX_STATUS_BIT_SC
kflag
r0
lr
r0
,
[
AUX_STATUS32
]
bset
r0
,
r0
,
AUX_STATUS_BIT_SC
kflag
r0
#endif
#endif
pop
r0
j
[
r0
]
pop
r0
j
[
r0
]
.
global
start_r
.
align
4
.
global
start_r
.
align
4
start_r
:
pop
blink
;
pop
r1
pop
r2
pop
r0
pop
blink
;
pop
r1
pop
r2
pop
r0
j_s
.
d
[
r1
]
kflag
r2
j_s
.
d
[
r1
]
kflag
r2
/*
*
int
__rt_ffs
(
int
value
)
;
*
r0
-->
value
*/
.
global
__rt_ffs
.
align
4
.
global
__rt_ffs
.
align
4
__rt_ffs
:
breq
r0
,
0
,
__rt_ffs_return
ffs
r1
,
r0
add
r0
,
r1
,
1
breq
r0
,
0
,
__rt_ffs_return
ffs
r1
,
r0
add
r0
,
r1
,
1
__rt_ffs_return
:
j
[
blink
]
j
[
blink
]
/******
exceptions
and
interrupts
handing
******/
/******
entry
for
exception
handling
******/
.
global
exc_entry_cpu
.
align
4
.
global
exc_entry_cpu
.
align
4
exc_entry_cpu
:
EXCEPTION_PROLOGUE
EXCEPTION_PROLOGUE
mov
blink
,
sp
mov
r3
,
sp
/*
as
exception
handler
's para(p_excinfo) */
mov
blink
,
sp
mov
r3
,
sp
/*
as
exception
handler
's para(p_excinfo) */
ld
r0
,
[
exc_nest_count
]
add
r1
,
r0
,
1
st
r1
,
[
exc_nest_count
]
brne
r0
,
0
,
exc_handler_1
ld
r0
,
[
exc_nest_count
]
add
r1
,
r0
,
1
st
r1
,
[
exc_nest_count
]
brne
r0
,
0
,
exc_handler_1
/*
change
to
exception
stack
if
interrupt
happened
in
task
context
*/
mov
sp
,
_e_stack
mov
sp
,
_e_stack
exc_handler_1
:
PUSH
blink
PUSH
blink
lr
r0
,
[
AUX_ECR
]
lsr
r0
,
r0
,
16
mov
r1
,
exc_int_handler_table
ld.as
r2
,
[
r1
,
r0
]
lr
r0
,
[
AUX_ECR
]
lsr
r0
,
r0
,
16
mov
r1
,
exc_int_handler_table
ld.as
r2
,
[
r1
,
r0
]
mov
r0
,
r3
jl
[
r2
]
mov
r0
,
r3
jl
[
r2
]
/*
interrupts
are
not
allowed
*/
ret_exc
:
POP
sp
mov
r1
,
exc_nest_count
ld
r0
,
[
r1
]
sub
r0
,
r0
,
1
st
r0
,
[
r1
]
brne
r0
,
0
,
ret_exc_1
/*
nest
exception
case
*/
lr
r1
,
[
AUX_IRQ_ACT
]
/*
nest
interrupt
case
*/
brne
r1
,
0
,
ret_exc_1
ld
r0
,
[
context_switch_reqflg
]
brne
r0
,
0
,
ret_exc_2
ret_exc_1
:
/
*
return
from
non
-
task
context
,
interrupts
or
exceptions
are
nested
*/
EXCEPTION_EPILOGUE
rtie
POP
sp
mov
r1
,
exc_nest_count
ld
r0
,
[
r1
]
sub
r0
,
r0
,
1
st
r0
,
[
r1
]
brne
r0
,
0
,
ret_exc_1
/*
nest
exception
case
*/
lr
r1
,
[
AUX_IRQ_ACT
]
/*
nest
interrupt
case
*/
brne
r1
,
0
,
ret_exc_1
ld
r0
,
[
context_switch_reqflg
]
brne
r0
,
0
,
ret_exc_2
ret_exc_1
:
/
*
return
from
non
-
task
context
,
interrupts
or
exceptions
are
nested
*/
EXCEPTION_EPILOGUE
rtie
/*
there
is
a
dispatch
request
*/
ret_exc_2
:
/
*
clear
dispatch
request
*/
mov
r0
,
0
st
r0
,
[
context_switch_reqflg
]
/
*
clear
dispatch
request
*/
mov
r0
,
0
st
r0
,
[
context_switch_reqflg
]
SAVE_CALLEE_REGS
/*
save
callee
save
registers
*/
SAVE_CALLEE_REGS
/*
save
callee
save
registers
*/
/
*
clear
exception
bit
to
do
exception
exit
by
SW
*/
lr
r0
,
[
AUX_STATUS32
]
bclr
r0
,
r0
,
AUX_STATUS_BIT_AE
kflag
r0
/
*
clear
exception
bit
to
do
exception
exit
by
SW
*/
lr
r0
,
[
AUX_STATUS32
]
bclr
r0
,
r0
,
AUX_STATUS_BIT_AE
kflag
r0
mov
r1
,
ret_exc_r
/*
save
return
address
*/
PUSH
r1
mov
r1
,
ret_exc_r
/*
save
return
address
*/
PUSH
r1
ld
r0
,
[
rt_interrupt_from_thread
]
ld
r1
,
[
rt_interrupt_to_thread
]
b
dispatcher
ld
r0
,
[
rt_interrupt_from_thread
]
ld
r1
,
[
rt_interrupt_to_thread
]
b
dispatcher
ret_exc_r
:
/
*
recover
exception
status
*/
lr
r0
,
[
AUX_STATUS32
]
bset
r0
,
r0
,
AUX_STATUS_BIT_AE
kflag
r0
/
*
recover
exception
status
*/
lr
r0
,
[
AUX_STATUS32
]
bset
r0
,
r0
,
AUX_STATUS_BIT_AE
kflag
r0
RESTORE_CALLEE_REGS
EXCEPTION_EPILOGUE
rtie
RESTORE_CALLEE_REGS
EXCEPTION_EPILOGUE
rtie
/******
entry
for
normal
interrupt
exception
handling
******/
.
global
exc_entry_int
/*
entry
for
interrupt
handling
*/
.
align
4
.
global
exc_entry_int
/*
entry
for
interrupt
handling
*/
.
align
4
exc_entry_int
:
#if ARC_FEATURE_FIRQ == 1
/*
check
whether
it
is
P0
interrupt
*/
#if ARC_FEATURE_RGF_NUM_BANKS > 1
lr
r0
,
[
AUX_IRQ_ACT
]
btst
r0
,
0
jnz
exc_entry_firq
lr
r0
,
[
AUX_IRQ_ACT
]
btst
r0
,
0
jnz
exc_entry_firq
#else
PUSH
r10
lr
r10
,
[
AUX_IRQ_ACT
]
btst
r10
,
0
POP
r10
jnz
exc_entry_firq
PUSH
r10
lr
r10
,
[
AUX_IRQ_ACT
]
btst
r10
,
0
POP
r10
jnz
exc_entry_firq
#endif
#endif
INTERRUPT_PROLOGUE
INTERRUPT_PROLOGUE
mov
blink
,
sp
mov
blink
,
sp
clri
/*
disable
interrupt
*/
ld
r3
,
[
exc_nest_count
]
add
r2
,
r3
,
1
st
r2
,
[
exc_nest_count
]
seti
/*
enable
higher
priority
interrupt
*/
clri
/*
disable
interrupt
*/
ld
r3
,
[
exc_nest_count
]
add
r2
,
r3
,
1
st
r2
,
[
exc_nest_count
]
seti
/*
enable
higher
priority
interrupt
*/
brne
r3
,
0
,
irq_handler_1
brne
r3
,
0
,
irq_handler_1
/*
change
to
exception
stack
if
interrupt
happened
in
task
context
*/
mov
sp
,
_e_stack
mov
sp
,
_e_stack
#if ARC_FEATURE_STACK_CHECK
#if ARC_FEATURE_SEC_PRESENT
lr
r0
,
[
AUX_SEC_STAT
]
bclr
r0
,
r0
,
AUX_SEC_STAT_BIT_SSC
sflag
r0
lr
r0
,
[
AUX_SEC_STAT
]
bclr
r0
,
r0
,
AUX_SEC_STAT_BIT_SSC
sflag
r0
#else
lr
r0
,
[
AUX_STATUS32
]
bclr
r0
,
r0
,
AUX_STATUS_BIT_SC
kflag
r0
lr
r0
,
[
AUX_STATUS32
]
bclr
r0
,
r0
,
AUX_STATUS_BIT_SC
kflag
r0
#endif
#endif
irq_handler_1
:
PUSH
blink
PUSH
blink
jl
rt_interrupt_enter
jl
rt_interrupt_enter
lr
r0
,
[
AUX_IRQ_CAUSE
]
sr
r0
,
[
AUX_IRQ_SELECT
]
mov
r1
,
exc_int_handler_table
ld.as
r2
,
[
r1
,
r0
]
/*
r2
=
exc_int_handler_table
+
irqno
*
4
*/
lr
r0
,
[
AUX_IRQ_CAUSE
]
sr
r0
,
[
AUX_IRQ_SELECT
]
mov
r1
,
exc_int_handler_table
ld.as
r2
,
[
r1
,
r0
]
/*
r2
=
exc_int_handler_table
+
irqno
*
4
*/
/*
handle
software
triggered
interrupt
*/
lr
r3
,
[
AUX_IRQ_HINT
]
cmp
r3
,
r0
bne.d
irq_hint_handled
xor
r3
,
r3
,
r3
sr
r3
,
[
AUX_IRQ_HINT
]
lr
r3
,
[
AUX_IRQ_HINT
]
cmp
r3
,
r0
bne.d
irq_hint_handled
xor
r3
,
r3
,
r3
sr
r3
,
[
AUX_IRQ_HINT
]
irq_hint_handled
:
lr
r3
,
[
AUX_IRQ_PRIORITY
]
PUSH
r3
/*
save
irq
priority
*/
lr
r3
,
[
AUX_IRQ_PRIORITY
]
PUSH
r3
/*
save
irq
priority
*/
jl
[
r2
]
/*
jump
to
interrupt
handler
*/
jl
rt_interrupt_leave
jl
[
r2
]
/*
jump
to
interrupt
handler
*/
jl
rt_interrupt_leave
ret_int
:
clri
/*
disable
interrupt
*/
POP
r3
/*
irq
priority
*/
POP
sp
mov
r1
,
exc_nest_count
ld
r0
,
[
r1
]
sub
r0
,
r0
,
1
st
r0
,
[
r1
]
clri
/*
disable
interrupt
*/
POP
r3
/*
irq
priority
*/
POP
sp
mov
r1
,
exc_nest_count
ld
r0
,
[
r1
]
sub
r0
,
r0
,
1
st
r0
,
[
r1
]
/*
if
there
are
multi
-
bits
set
in
IRQ_ACT
,
it
's still in nest interrupt */
lr
r0
,
[
AUX_IRQ_CAUSE
]
sr
r0
,
[
AUX_IRQ_SELECT
]
lr
r3
,
[
AUX_IRQ_PRIORITY
]
lr
r1
,
[
AUX_IRQ_ACT
]
bclr
r2
,
r1
,
r3
brne
r2
,
0
,
ret_int_1
ld
r0
,
[
context_switch_reqflg
]
brne
r0
,
0
,
ret_int_2
ret_int_1
:
/
*
return
from
non
-
task
context
*/
INTERRUPT_EPILOGUE
rtie
lr
r0
,
[
AUX_IRQ_CAUSE
]
sr
r0
,
[
AUX_IRQ_SELECT
]
lr
r3
,
[
AUX_IRQ_PRIORITY
]
lr
r1
,
[
AUX_IRQ_ACT
]
bclr
r2
,
r1
,
r3
brne
r2
,
0
,
ret_int_1
ld
r0
,
[
context_switch_reqflg
]
brne
r0
,
0
,
ret_int_2
ret_int_1
:
/
*
return
from
non
-
task
context
*/
INTERRUPT_EPILOGUE
rtie
/*
there
is
a
dispatch
request
*/
ret_int_2
:
/
*
clear
dispatch
request
*/
mov
r0
,
0
st
r0
,
[
context_switch_reqflg
]
/
*
clear
dispatch
request
*/
mov
r0
,
0
st
r0
,
[
context_switch_reqflg
]
/
*
interrupt
return
by
SW
*/
lr
r10
,
[
AUX_IRQ_ACT
]
PUSH
r10
bclr
r10
,
r10
,
r3
/*
clear
related
bits
in
IRQ_ACT
*/
sr
r10
,
[
AUX_IRQ_ACT
]
/
*
interrupt
return
by
SW
*/
lr
r10
,
[
AUX_IRQ_ACT
]
PUSH
r10
bclr
r10
,
r10
,
r3
/*
clear
related
bits
in
IRQ_ACT
*/
sr
r10
,
[
AUX_IRQ_ACT
]
SAVE_CALLEE_REGS
/*
save
callee
save
registers
*/
mov
r1
,
ret_int_r
/*
save
return
address
*/
PUSH
r1
SAVE_CALLEE_REGS
/*
save
callee
save
registers
*/
mov
r1
,
ret_int_r
/*
save
return
address
*/
PUSH
r1
ld
r0
,
[
rt_interrupt_from_thread
]
ld
r1
,
[
rt_interrupt_to_thread
]
b
dispatcher
ld
r0
,
[
rt_interrupt_from_thread
]
ld
r1
,
[
rt_interrupt_to_thread
]
b
dispatcher
ret_int_r
:
RESTORE_CALLEE_REGS
/
*
recover
AUX_IRQ_ACT
to
restore
the
interrup
status
*/
POPAX
AUX_IRQ_ACT
INTERRUPT_EPILOGUE
rtie
RESTORE_CALLEE_REGS
/
*
recover
AUX_IRQ_ACT
to
restore
the
interrup
status
*/
POPAX
AUX_IRQ_ACT
INTERRUPT_EPILOGUE
rtie
/******
entry
for
fast
irq
exception
handling
******/
.
global
exc_entry_firq
.
weak
exc_entry_firq
.
align
4
.
global
exc_entry_firq
.
weak
exc_entry_firq
.
align
4
exc_entry_firq
:
SAVE_FIQ_EXC_REGS
SAVE_FIQ_EXC_REGS
lr
r0
,
[
AUX_IRQ_CAUSE
]
mov
r1
,
exc_int_handler_table
lr
r0
,
[
AUX_IRQ_CAUSE
]
mov
r1
,
exc_int_handler_table
/*
r2
=
_kernel_exc_tbl
+
irqno
*
4
*/
ld.as
r2
,
[
r1
,
r0
]
ld.as
r2
,
[
r1
,
r0
]
/*
for
the
case
of
software
triggered
interrupt
*/
lr
r3
,
[
AUX_IRQ_HINT
]
cmp
r3
,
r0
bne.d
firq_hint_handled
xor
r3
,
r3
,
r3
sr
r3
,
[
AUX_IRQ_HINT
]
lr
r3
,
[
AUX_IRQ_HINT
]
cmp
r3
,
r0
bne.d
firq_hint_handled
xor
r3
,
r3
,
r3
sr
r3
,
[
AUX_IRQ_HINT
]
firq_hint_handled
:
/*
jump
to
interrupt
handler
*/
mov
r0
,
sp
jl
[
r2
]
mov
r0
,
sp
jl
[
r2
]
firq_return
:
RESTORE_FIQ_EXC_REGS
rtie
RESTORE_FIQ_EXC_REGS
rtie
libcpu/arm/AT91SAM7S/context_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -8,25 +8,25 @@
*
2006
-
03
-
13
Bernard
first
version
*/
#define NOINT
0xc0
#define NOINT
0xc0
/*
*
rt_base_t
rt_hw_interrupt_disable
()/*
*/
.
globl
rt_hw_interrupt_disable
rt_hw_interrupt_disable
:
mrs
r0
,
cpsr
orr
r1
,
r0
,
#
NOINT
msr
cpsr_c
,
r1
mov
pc
,
lr
mrs
r0
,
cpsr
orr
r1
,
r0
,
#
NOINT
msr
cpsr_c
,
r1
mov
pc
,
lr
/*
*
void
rt_hw_interrupt_enable
(
rt_base_t
level
)/*
*/
.
globl
rt_hw_interrupt_enable
rt_hw_interrupt_enable
:
msr
cpsr
,
r0
mov
pc
,
lr
msr
cpsr
,
r0
mov
pc
,
lr
/*
*
void
rt_hw_context_switch
(
rt_uint32
from
,
rt_uint32
to
)/*
...
...
@@ -35,23 +35,23 @@ rt_hw_interrupt_enable:
*/
.
globl
rt_hw_context_switch
rt_hw_context_switch
:
stmfd
sp
!,
{
lr
}
/*
push
pc
(
lr
should
be
pushed
in
place
of
PC
)
*/
stmfd
sp
!,
{
r0
-
r12
,
lr
}
/*
push
lr
&
register
file
*/
stmfd
sp
!,
{
lr
}
/*
push
pc
(
lr
should
be
pushed
in
place
of
PC
)
*/
stmfd
sp
!,
{
r0
-
r12
,
lr
}
/*
push
lr
&
register
file
*/
mrs
r4
,
cpsr
stmfd
sp
!,
{
r4
}
/*
push
cpsr
*/
mrs
r4
,
spsr
stmfd
sp
!,
{
r4
}
/*
push
spsr
*/
mrs
r4
,
cpsr
stmfd
sp
!,
{
r4
}
/*
push
cpsr
*/
mrs
r4
,
spsr
stmfd
sp
!,
{
r4
}
/*
push
spsr
*/
str
sp
,
[
r0
]
/*
store
sp
in
preempted
tasks
TCB
*/
ldr
sp
,
[
r1
]
/*
get
new
task
stack
pointer
*/
str
sp
,
[
r0
]
/*
store
sp
in
preempted
tasks
TCB
*/
ldr
sp
,
[
r1
]
/*
get
new
task
stack
pointer
*/
ldmfd
sp
!,
{
r4
}
/*
pop
new
task
spsr
*/
msr
spsr_cxsf
,
r4
ldmfd
sp
!,
{
r4
}
/*
pop
new
task
cpsr
*/
msr
cpsr_cxsf
,
r4
ldmfd
sp
!,
{
r4
}
/*
pop
new
task
spsr
*/
msr
spsr_cxsf
,
r4
ldmfd
sp
!,
{
r4
}
/*
pop
new
task
cpsr
*/
msr
cpsr_cxsf
,
r4
ldmfd
sp
!,
{
r0
-
r12
,
lr
,
pc
}
/*
pop
new
task
r0
-
r12
,
lr
&
pc
*/
ldmfd
sp
!,
{
r0
-
r12
,
lr
,
pc
}
/*
pop
new
task
r0
-
r12
,
lr
&
pc
*/
/*
*
void
rt_hw_context_switch_to
(
rt_uint32
to
)/*
...
...
@@ -59,14 +59,14 @@ rt_hw_context_switch:
*/
.
globl
rt_hw_context_switch_to
rt_hw_context_switch_to
:
ldr
sp
,
[
r0
]
/*
get
new
task
stack
pointer
*/
ldr
sp
,
[
r0
]
/*
get
new
task
stack
pointer
*/
ldmfd
sp
!,
{
r4
}
/*
pop
new
task
spsr
*/
msr
spsr_cxsf
,
r4
ldmfd
sp
!,
{
r4
}
/*
pop
new
task
cpsr
*/
msr
cpsr_cxsf
,
r4
ldmfd
sp
!,
{
r4
}
/*
pop
new
task
spsr
*/
msr
spsr_cxsf
,
r4
ldmfd
sp
!,
{
r4
}
/*
pop
new
task
cpsr
*/
msr
cpsr_cxsf
,
r4
ldmfd
sp
!,
{
r0
-
r12
,
lr
,
pc
}
/*
pop
new
task
r0
-
r12
,
lr
&
pc
*/
ldmfd
sp
!,
{
r0
-
r12
,
lr
,
pc
}
/*
pop
new
task
r0
-
r12
,
lr
&
pc
*/
/*
*
void
rt_hw_context_switch_interrupt
(
rt_uint32
from
,
rt_uint32
to
)/*
...
...
@@ -76,15 +76,15 @@ rt_hw_context_switch_to:
.
globl
rt_interrupt_to_thread
.
globl
rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt
:
ldr
r2
,
=
rt_thread_switch_interrupt_flag
ldr
r3
,
[
r2
]
cmp
r3
,
#
1
beq
_reswitch
mov
r3
,
#
1
/*
set
rt_thread_switch_interrupt_flag
to
1
*/
str
r3
,
[
r2
]
ldr
r2
,
=
rt_interrupt_from_thread
/*
set
rt_interrupt_from_thread
*/
str
r0
,
[
r2
]
ldr
r2
,
=
rt_thread_switch_interrupt_flag
ldr
r3
,
[
r2
]
cmp
r3
,
#
1
beq
_reswitch
mov
r3
,
#
1
/*
set
rt_thread_switch_interrupt_flag
to
1
*/
str
r3
,
[
r2
]
ldr
r2
,
=
rt_interrupt_from_thread
/*
set
rt_interrupt_from_thread
*/
str
r0
,
[
r2
]
_reswitch
:
ldr
r2
,
=
rt_interrupt_to_thread
/*
set
rt_interrupt_to_thread
*/
str
r1
,
[
r2
]
mov
pc
,
lr
ldr
r2
,
=
rt_interrupt_to_thread
/*
set
rt_interrupt_to_thread
*/
str
r1
,
[
r2
]
mov
pc
,
lr
libcpu/arm/AT91SAM7S/context_rvds.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -8,7 +8,7 @@
*
2009
-
01
-
20
Bernard
first
version
*/
NOINT
EQU
0xc0
; disable interrupt in psr
NOINT
EQU
0xc0
; disable interrupt in psr
AREA
|.text|
,
CODE
,
READONLY
,
ALIGN
=
2
ARM
...
...
@@ -18,21 +18,21 @@ NOINT EQU 0xc0 ; disable interrupt in psr
;/*
; * rt_base_t rt_hw_interrupt_disable();
; */
rt_hw_interrupt_disable
PROC
rt_hw_interrupt_disable
PROC
EXPORT
rt_hw_interrupt_disable
MRS
r0
,
cpsr
ORR
r1
,
r0
,
#
NOINT
MSR
cpsr_c
,
r1
BX
lr
BX
lr
ENDP
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
rt_hw_interrupt_enable
PROC
rt_hw_interrupt_enable
PROC
EXPORT
rt_hw_interrupt_enable
MSR
cpsr_c
,
r0
BX
lr
BX
lr
ENDP
;/*
...
...
@@ -40,41 +40,41 @@ rt_hw_interrupt_enable PROC
; * r0 --> from
; * r1 --> to
; */
rt_hw_context_switch
PROC
rt_hw_context_switch
PROC
EXPORT
rt_hw_context_switch
STMFD
sp
!,
{
lr
}
; push pc (lr should be pushed in place of PC)
STMFD
sp
!,
{
r0
-
r12
,
lr
}
; push lr & register file
STMFD
sp
!,
{
lr
}
; push pc (lr should be pushed in place of PC)
STMFD
sp
!,
{
r0
-
r12
,
lr
}
; push lr & register file
MRS
r4
,
cpsr
STMFD
sp
!,
{
r4
}
; push cpsr
MRS
r4
,
spsr
STMFD
sp
!,
{
r4
}
; push spsr
MRS
r4
,
cpsr
STMFD
sp
!,
{
r4
}
; push cpsr
MRS
r4
,
spsr
STMFD
sp
!,
{
r4
}
; push spsr
STR
sp
,
[
r0
]
; store sp in preempted tasks TCB
LDR
sp
,
[
r1
]
; get new task stack pointer
STR
sp
,
[
r0
]
; store sp in preempted tasks TCB
LDR
sp
,
[
r1
]
; get new task stack pointer
LDMFD
sp
!,
{
r4
}
; pop new task spsr
MSR
spsr_cxsf
,
r4
LDMFD
sp
!,
{
r4
}
; pop new task cpsr
MSR
cpsr_cxsf
,
r4
LDMFD
sp
!,
{
r4
}
; pop new task spsr
MSR
spsr_cxsf
,
r4
LDMFD
sp
!,
{
r4
}
; pop new task cpsr
MSR
cpsr_cxsf
,
r4
LDMFD
sp
!,
{
r0
-
r12
,
lr
,
pc
}
; pop new task r0-r12, lr & pc
LDMFD
sp
!,
{
r0
-
r12
,
lr
,
pc
}
; pop new task r0-r12, lr & pc
ENDP
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
; * r0 --> to
; */
rt_hw_context_switch_to
PROC
rt_hw_context_switch_to
PROC
EXPORT
rt_hw_context_switch_to
LDR
sp
,
[
r0
]
; get new task stack pointer
LDR
sp
,
[
r0
]
; get new task stack pointer
LDMFD
sp
!,
{
r4
}
; pop new task spsr
MSR
spsr_cxsf
,
r4
LDMFD
sp
!,
{
r4
}
; pop new task cpsr
MSR
cpsr_cxsf
,
r4
LDMFD
sp
!,
{
r4
}
; pop new task spsr
MSR
spsr_cxsf
,
r4
LDMFD
sp
!,
{
r4
}
; pop new task cpsr
MSR
cpsr_cxsf
,
r4
LDMFD
sp
!,
{
r0
-
r12
,
lr
,
pc
}
; pop new task r0-r12, lr & pc
LDMFD
sp
!,
{
r0
-
r12
,
lr
,
pc
}
; pop new task r0-r12, lr & pc
ENDP
;/*
...
...
@@ -84,20 +84,20 @@ rt_hw_context_switch_to PROC
IMPORT
rt_interrupt_from_thread
IMPORT
rt_interrupt_to_thread
rt_hw_context_switch_interrupt
PROC
rt_hw_context_switch_interrupt
PROC
EXPORT
rt_hw_context_switch_interrupt
LDR
r2
,
=
rt_thread_switch_interrupt_flag
LDR
r3
,
[
r2
]
CMP
r3
,
#
1
BEQ
_reswitch
MOV
r3
,
#
1
; set rt_thread_switch_interrupt_flag to 1
MOV
r3
,
#
1
; set rt_thread_switch_interrupt_flag to 1
STR
r3
,
[
r2
]
LDR
r2
,
=
rt_interrupt_from_thread
; set rt_interrupt_from_thread
LDR
r2
,
=
rt_interrupt_from_thread
; set rt_interrupt_from_thread
STR
r0
,
[
r2
]
_reswitch
LDR
r2
,
=
rt_interrupt_to_thread
; set rt_interrupt_to_thread
LDR
r2
,
=
rt_interrupt_to_thread
; set rt_interrupt_to_thread
STR
r1
,
[
r2
]
BX
lr
BX
lr
ENDP
END
\ No newline at end of file
END
libcpu/arm/AT91SAM7S/start_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -8,151 +8,151 @@
*
2006
-
08
-
31
Bernard
first
version
*/
/
*
Internal
Memory
Base
Addresses
*/
.
equ
FLASH_BASE
,
0x00100000
.
equ
RAM_BASE
,
0x00200000
/
*
Stack
Configuration
*/
.
equ
TOP_STACK
,
0x00204000
.
equ
UND_STACK_SIZE
,
0x00000100
.
equ
SVC_STACK_SIZE
,
0x00000400
.
equ
ABT_STACK_SIZE
,
0x00000100
.
equ
FIQ_STACK_SIZE
,
0x00000100
.
equ
IRQ_STACK_SIZE
,
0x00000100
.
equ
USR_STACK_SIZE
,
0x00000004
/
*
ARM
architecture
definitions
*/
.
equ
MODE_USR
,
0x10
.
equ
MODE_FIQ
,
0x11
.
equ
MODE_IRQ
,
0x12
.
equ
MODE_SVC
,
0x13
.
equ
MODE_ABT
,
0x17
.
equ
MODE_UND
,
0x1B
.
equ
MODE_SYS
,
0x1F
.
equ
I_BIT
,
0x80
/*
when
this
bit
is
set
,
IRQ
is
disabled
*/
.
equ
F_BIT
,
0x40
/*
when
this
bit
is
set
,
FIQ
is
disabled
*/
/
*
Internal
Memory
Base
Addresses
*/
.
equ
FLASH_BASE
,
0x00100000
.
equ
RAM_BASE
,
0x00200000
/
*
Stack
Configuration
*/
.
equ
TOP_STACK
,
0x00204000
.
equ
UND_STACK_SIZE
,
0x00000100
.
equ
SVC_STACK_SIZE
,
0x00000400
.
equ
ABT_STACK_SIZE
,
0x00000100
.
equ
FIQ_STACK_SIZE
,
0x00000100
.
equ
IRQ_STACK_SIZE
,
0x00000100
.
equ
USR_STACK_SIZE
,
0x00000004
/
*
ARM
architecture
definitions
*/
.
equ
MODE_USR
,
0x10
.
equ
MODE_FIQ
,
0x11
.
equ
MODE_IRQ
,
0x12
.
equ
MODE_SVC
,
0x13
.
equ
MODE_ABT
,
0x17
.
equ
MODE_UND
,
0x1B
.
equ
MODE_SYS
,
0x1F
.
equ
I_BIT
,
0x80
/*
when
this
bit
is
set
,
IRQ
is
disabled
*/
.
equ
F_BIT
,
0x40
/*
when
this
bit
is
set
,
FIQ
is
disabled
*/
.
section
.
init
,
"ax"
.
code
32
.
align
0
.
globl
_start
_start
:
b
reset
ldr
pc
,
_vector_undef
ldr
pc
,
_vector_swi
ldr
pc
,
_vector_pabt
ldr
pc
,
_vector_dabt
nop
/*
reserved
vector
*/
ldr
pc
,
_vector_irq
ldr
pc
,
_vector_fiq
_vector_undef
:
.
word
vector_undef
_vector_swi
:
.
word
vector_swi
_vector_pabt
:
.
word
vector_pabt
_vector_dabt
:
.
word
vector_dabt
_vector_resv
:
.
word
vector_resv
_vector_irq
:
.
word
vector_irq
_vector_fiq
:
.
word
vector_fiq
b
reset
ldr
pc
,
_vector_undef
ldr
pc
,
_vector_swi
ldr
pc
,
_vector_pabt
ldr
pc
,
_vector_dabt
nop
/*
reserved
vector
*/
ldr
pc
,
_vector_irq
ldr
pc
,
_vector_fiq
_vector_undef
:
.
word
vector_undef
_vector_swi
:
.
word
vector_swi
_vector_pabt
:
.
word
vector_pabt
_vector_dabt
:
.
word
vector_dabt
_vector_resv
:
.
word
vector_resv
_vector_irq
:
.
word
vector_irq
_vector_fiq
:
.
word
vector_fiq
/*
*
rtthread
bss
start
and
end
*
which
are
defined
in
linker
script
*/
.
globl
_bss_start
_bss_start
:
.
word
__bss_start
_bss_start
:
.
word
__bss_start
.
globl
_bss_end
_bss_end
:
.
word
__bss_end
_bss_end
:
.
word
__bss_end
/*
the
system
entry
*/
reset
:
/
*
disable
watchdog
*/
ldr
r0
,
=
0xFFFFFD40
ldr
r1
,
=
0x00008000
str
r1
,
[
r0
,
#
0x04
]
/
*
enable
the
main
oscillator
*/
ldr
r0
,
=
0xFFFFFC00
ldr
r1
,
=
0x00000601
str
r1
,
[
r0
,
#
0x20
]
/
*
wait
for
main
oscillator
to
stabilize
*/
/
*
disable
watchdog
*/
ldr
r0
,
=
0xFFFFFD40
ldr
r1
,
=
0x00008000
str
r1
,
[
r0
,
#
0x04
]
/
*
enable
the
main
oscillator
*/
ldr
r0
,
=
0xFFFFFC00
ldr
r1
,
=
0x00000601
str
r1
,
[
r0
,
#
0x20
]
/
*
wait
for
main
oscillator
to
stabilize
*/
moscs_loop
:
ldr
r2
,
[
r0
,
#
0x68
]
ands
r2
,
r2
,
#
1
beq
moscs_loop
/
*
set
up
the
PLL
*/
ldr
r1
,
=
0x00191C05
str
r1
,
[
r0
,
#
0x2C
]
/
*
wait
for
PLL
to
lock
*/
ldr
r2
,
[
r0
,
#
0x68
]
ands
r2
,
r2
,
#
1
beq
moscs_loop
/
*
set
up
the
PLL
*/
ldr
r1
,
=
0x00191C05
str
r1
,
[
r0
,
#
0x2C
]
/
*
wait
for
PLL
to
lock
*/
pll_loop
:
ldr
r2
,
[
r0
,
#
0x68
]
ands
r2
,
r2
,
#
0x04
beq
pll_loop
/
*
select
clock
*/
ldr
r1
,
=
0x00000007
str
r1
,
[
r0
,
#
0x30
]
/
*
setup
stack
for
each
mode
*/
ldr
r0
,
=
TOP_STACK
/
*
set
stack
*/
/
*
undefined
instruction
mode
*/
msr
cpsr_c
,
#
MODE_UND|I_BIT|F_BIT
mov
sp
,
r0
sub
r0
,
r0
,
#
UND_STACK_SIZE
/
*
abort
mode
*/
msr
cpsr_c
,
#
MODE_ABT|I_BIT|F_BIT
mov
sp
,
r0
sub
r0
,
r0
,
#
ABT_STACK_SIZE
/
*
FIQ
mode
*/
msr
cpsr_c
,
#
MODE_FIQ|I_BIT|F_BIT
mov
sp
,
r0
sub
r0
,
r0
,
#
FIQ_STACK_SIZE
/
*
IRQ
mode
*/
msr
cpsr_c
,
#
MODE_IRQ|I_BIT|F_BIT
mov
sp
,
r0
sub
r0
,
r0
,
#
IRQ_STACK_SIZE
/
*
supervisor
mode
*/
msr
cpsr_c
,
#
MODE_SVC
mov
sp
,
r0
ldr
r2
,
[
r0
,
#
0x68
]
ands
r2
,
r2
,
#
0x04
beq
pll_loop
/
*
select
clock
*/
ldr
r1
,
=
0x00000007
str
r1
,
[
r0
,
#
0x30
]
/
*
setup
stack
for
each
mode
*/
ldr
r0
,
=
TOP_STACK
/
*
set
stack
*/
/
*
undefined
instruction
mode
*/
msr
cpsr_c
,
#
MODE_UND|I_BIT|F_BIT
mov
sp
,
r0
sub
r0
,
r0
,
#
UND_STACK_SIZE
/
*
abort
mode
*/
msr
cpsr_c
,
#
MODE_ABT|I_BIT|F_BIT
mov
sp
,
r0
sub
r0
,
r0
,
#
ABT_STACK_SIZE
/
*
FIQ
mode
*/
msr
cpsr_c
,
#
MODE_FIQ|I_BIT|F_BIT
mov
sp
,
r0
sub
r0
,
r0
,
#
FIQ_STACK_SIZE
/
*
IRQ
mode
*/
msr
cpsr_c
,
#
MODE_IRQ|I_BIT|F_BIT
mov
sp
,
r0
sub
r0
,
r0
,
#
IRQ_STACK_SIZE
/
*
supervisor
mode
*/
msr
cpsr_c
,
#
MODE_SVC
mov
sp
,
r0
#ifdef __FLASH_BUILD__
/
*
Relocate
.
data
section
(
Copy
from
ROM
to
RAM
)
*/
ldr
r1
,
=
_etext
ldr
r2
,
=
_data
ldr
r3
,
=
_edata
/
*
Relocate
.
data
section
(
Copy
from
ROM
to
RAM
)
*/
ldr
r1
,
=
_etext
ldr
r2
,
=
_data
ldr
r3
,
=
_edata
data_loop
:
cmp
r2
,
r3
ldrlo
r0
,
[
r1
],
#
4
strlo
r0
,
[
r2
],
#
4
blo
data_loop
cmp
r2
,
r3
ldrlo
r0
,
[
r1
],
#
4
strlo
r0
,
[
r2
],
#
4
blo
data_loop
#else
/
*
remap
SRAM
to
0x0000
*/
ldr
r0
,
=
0xFFFFFF00
mov
r1
,
#
0x01
str
r1
,
[
r0
]
/
*
remap
SRAM
to
0x0000
*/
ldr
r0
,
=
0xFFFFFF00
mov
r1
,
#
0x01
str
r1
,
[
r0
]
#endif
/
*
mask
all
IRQs
*/
ldr
r1
,
=
0xFFFFF124
ldr
r0
,
=
0XFFFFFFFF
str
r0
,
[
r1
]
/
*
start
RT
-
Thread
Kernel
*/
ldr
pc
,
_rtthread_startup
/
*
mask
all
IRQs
*/
ldr
r1
,
=
0xFFFFF124
ldr
r0
,
=
0XFFFFFFFF
str
r0
,
[
r1
]
/
*
start
RT
-
Thread
Kernel
*/
ldr
pc
,
_rtthread_startup
_rtthread_startup
:
.
word
rtthread_startup
/*
exception
handlers
*/
vector_undef
:
b
vector_undef
vector_undef
:
b
vector_undef
vector_swi
:
b
vector_swi
vector_pabt
:
b
vector_pabt
vector_dabt
:
b
vector_dabt
...
...
@@ -164,70 +164,70 @@ vector_resv : b vector_resv
.
globl
rt_interrupt_from_thread
.
globl
rt_interrupt_to_thread
vector_irq
:
stmfd
sp
!,
{
r0
-
r12
,
lr
}
bl
rt_interrupt_enter
bl
rt_hw_trap_irq
bl
rt_interrupt_leave
/
*
*
if
rt_thread_switch_interrupt_flag
set
,
jump
to
*
rt_hw_context_switch_interrupt_do
and
don
't return
*/
ldr
r0
,
=
rt_thread_switch_interrupt_flag
ldr
r1
,
[
r0
]
cmp
r1
,
#
1
beq
rt_hw_context_switch_interrupt_do
ldmfd
sp
!,
{
r0
-
r12
,
lr
}
subs
pc
,
lr
,
#
4
stmfd
sp
!,
{
r0
-
r12
,
lr
}
bl
rt_interrupt_enter
bl
rt_hw_trap_irq
bl
rt_interrupt_leave
/
*
*
if
rt_thread_switch_interrupt_flag
set
,
jump
to
*
rt_hw_context_switch_interrupt_do
and
don
't return
*/
ldr
r0
,
=
rt_thread_switch_interrupt_flag
ldr
r1
,
[
r0
]
cmp
r1
,
#
1
beq
rt_hw_context_switch_interrupt_do
ldmfd
sp
!,
{
r0
-
r12
,
lr
}
subs
pc
,
lr
,
#
4
vector_fiq
:
stmfd
sp
!,{
r0
-
r7
,
lr
}
bl
rt_hw_trap_fiq
ldmfd
sp
!,{
r0
-
r7
,
lr
}
subs
pc
,
lr
,#
4
stmfd
sp
!,{
r0
-
r7
,
lr
}
bl
rt_hw_trap_fiq
ldmfd
sp
!,{
r0
-
r7
,
lr
}
subs
pc
,
lr
,#
4
/*
*
void
rt_hw_context_switch_interrupt_do
(
rt_base_t
flag
)
*/
rt_hw_context_switch_interrupt_do
:
mov
r1
,
#
0
/*
clear
flag
*/
str
r1
,
[
r0
]
ldmfd
sp
!,
{
r0
-
r12
,
lr
}
/*
reload
saved
registers
*/
stmfd
sp
!,
{
r0
-
r3
}
/*
save
r0
-
r3
*/
mov
r1
,
sp
add
sp
,
sp
,
#
16
/*
restore
sp
*/
sub
r2
,
lr
,
#
4
/*
save
old
task
's pc to r2 */
mrs
r3
,
spsr
/*
disable
interrupt
*/
orr
r0
,
r3
,
#
I_BIT
|
F_BIT
msr
spsr_c
,
r0
ldr
r0
,
=
.
+
8
/*
switch
to
interrupted
task
's stack */
movs
pc
,
r0
stmfd
sp
!,
{
r2
}
/*
push
old
task
's pc */
stmfd
sp
!,
{
r4
-
r12
,
lr
}
/*
push
old
task
's lr,r12-r4 */
mov
r4
,
r1
/*
Special
optimised
code
below
*/
mov
r5
,
r3
ldmfd
r4
!,
{
r0
-
r3
}
stmfd
sp
!,
{
r0
-
r3
}
/*
push
old
task
's r3-r0 */
stmfd
sp
!,
{
r5
}
/*
push
old
task
's psr */
mrs
r4
,
spsr
stmfd
sp
!,
{
r4
}
/*
push
old
task
's spsr */
ldr
r4
,
=
rt_interrupt_from_thread
ldr
r5
,
[
r4
]
str
sp
,
[
r5
]
/*
store
sp
in
preempted
tasks
's TCB */
ldr
r6
,
=
rt_interrupt_to_thread
ldr
r6
,
[
r6
]
ldr
sp
,
[
r6
]
/*
get
new
task
's stack pointer */
ldmfd
sp
!,
{
r4
}
/*
pop
new
task
's spsr */
msr
SPSR_cxsf
,
r4
ldmfd
sp
!,
{
r4
}
/*
pop
new
task
's psr */
msr
CPSR_cxsf
,
r4
ldmfd
sp
!,
{
r0
-
r12
,
lr
,
pc
}
/*
pop
new
task
's r0-r12,lr & pc */
mov
r1
,
#
0
/*
clear
flag
*/
str
r1
,
[
r0
]
ldmfd
sp
!,
{
r0
-
r12
,
lr
}
/*
reload
saved
registers
*/
stmfd
sp
!,
{
r0
-
r3
}
/*
save
r0
-
r3
*/
mov
r1
,
sp
add
sp
,
sp
,
#
16
/*
restore
sp
*/
sub
r2
,
lr
,
#
4
/*
save
old
task
's pc to r2 */
mrs
r3
,
spsr
/*
disable
interrupt
*/
orr
r0
,
r3
,
#
I_BIT
|
F_BIT
msr
spsr_c
,
r0
ldr
r0
,
=
.
+
8
/*
switch
to
interrupted
task
's stack */
movs
pc
,
r0
stmfd
sp
!,
{
r2
}
/*
push
old
task
's pc */
stmfd
sp
!,
{
r4
-
r12
,
lr
}
/*
push
old
task
's lr,r12-r4 */
mov
r4
,
r1
/*
Special
optimised
code
below
*/
mov
r5
,
r3
ldmfd
r4
!,
{
r0
-
r3
}
stmfd
sp
!,
{
r0
-
r3
}
/*
push
old
task
's r3-r0 */
stmfd
sp
!,
{
r5
}
/*
push
old
task
's psr */
mrs
r4
,
spsr
stmfd
sp
!,
{
r4
}
/*
push
old
task
's spsr */
ldr
r4
,
=
rt_interrupt_from_thread
ldr
r5
,
[
r4
]
str
sp
,
[
r5
]
/*
store
sp
in
preempted
tasks
's TCB */
ldr
r6
,
=
rt_interrupt_to_thread
ldr
r6
,
[
r6
]
ldr
sp
,
[
r6
]
/*
get
new
task
's stack pointer */
ldmfd
sp
!,
{
r4
}
/*
pop
new
task
's spsr */
msr
SPSR_cxsf
,
r4
ldmfd
sp
!,
{
r4
}
/*
pop
new
task
's psr */
msr
CPSR_cxsf
,
r4
ldmfd
sp
!,
{
r0
-
r12
,
lr
,
pc
}
/*
pop
new
task
's r0-r12,lr & pc */
libcpu/arm/AT91SAM7X/context_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -13,25 +13,25 @@
*/
/*@{*/
#define NOINT
0xc0
#define NOINT
0xc0
/*
*
rt_base_t
rt_hw_interrupt_disable
()
;
*/
.
globl
rt_hw_interrupt_disable
rt_hw_interrupt_disable
:
mrs
r0
,
cpsr
orr
r1
,
r0
,
#
NOINT
msr
cpsr_c
,
r1
mov
pc
,
lr
mrs
r0
,
cpsr
orr
r1
,
r0
,
#
NOINT
msr
cpsr_c
,
r1
mov
pc
,
lr
/*
*
void
rt_hw_interrupt_enable
(
rt_base_t
level
)
;
*/
.
globl
rt_hw_interrupt_enable
rt_hw_interrupt_enable
:
msr
cpsr
,
r0
mov
pc
,
lr
msr
cpsr
,
r0
mov
pc
,
lr
/*
*
void
rt_hw_context_switch
(
rt_uint32
from
,
rt_uint32
to
)
;
...
...
@@ -40,23 +40,23 @@ rt_hw_interrupt_enable:
*/
.
globl
rt_hw_context_switch
rt_hw_context_switch
:
stmfd
sp
!,
{
lr
}
@
push
pc
(
lr
should
be
pushed
in
place
of
PC
)
stmfd
sp
!,
{
r0
-
r12
,
lr
}
@
push
lr
&
register
file
stmfd
sp
!,
{
lr
}
@
push
pc
(
lr
should
be
pushed
in
place
of
PC
)
stmfd
sp
!,
{
r0
-
r12
,
lr
}
@
push
lr
&
register
file
mrs
r4
,
cpsr
stmfd
sp
!,
{
r4
}
@
push
cpsr
mrs
r4
,
spsr
stmfd
sp
!,
{
r4
}
@
push
spsr
mrs
r4
,
cpsr
stmfd
sp
!,
{
r4
}
@
push
cpsr
mrs
r4
,
spsr
stmfd
sp
!,
{
r4
}
@
push
spsr
str
sp
,
[
r0
]
@
store
sp
in
preempted
tasks
TCB
ldr
sp
,
[
r1
]
@
get
new
task
stack
pointer
str
sp
,
[
r0
]
@
store
sp
in
preempted
tasks
TCB
ldr
sp
,
[
r1
]
@
get
new
task
stack
pointer
ldmfd
sp
!,
{
r4
}
@
pop
new
task
spsr
msr
spsr_cxsf
,
r4
ldmfd
sp
!,
{
r4
}
@
pop
new
task
cpsr
msr
cpsr_cxsf
,
r4
ldmfd
sp
!,
{
r4
}
@
pop
new
task
spsr
msr
spsr_cxsf
,
r4
ldmfd
sp
!,
{
r4
}
@
pop
new
task
cpsr
msr
cpsr_cxsf
,
r4
ldmfd
sp
!,
{
r0
-
r12
,
lr
,
pc
}
@
pop
new
task
r0
-
r12
,
lr
&
pc
ldmfd
sp
!,
{
r0
-
r12
,
lr
,
pc
}
@
pop
new
task
r0
-
r12
,
lr
&
pc
/*
*
void
rt_hw_context_switch_to
(
rt_uint32
to
)
;
...
...
@@ -64,14 +64,14 @@ rt_hw_context_switch:
*/
.
globl
rt_hw_context_switch_to
rt_hw_context_switch_to
:
ldr
sp
,
[
r0
]
@
get
new
task
stack
pointer
ldr
sp
,
[
r0
]
@
get
new
task
stack
pointer
ldmfd
sp
!,
{
r4
}
@
pop
new
task
spsr
msr
spsr_cxsf
,
r4
ldmfd
sp
!,
{
r4
}
@
pop
new
task
cpsr
msr
cpsr_cxsf
,
r4
ldmfd
sp
!,
{
r4
}
@
pop
new
task
spsr
msr
spsr_cxsf
,
r4
ldmfd
sp
!,
{
r4
}
@
pop
new
task
cpsr
msr
cpsr_cxsf
,
r4
ldmfd
sp
!,
{
r0
-
r12
,
lr
,
pc
}
@
pop
new
task
r0
-
r12
,
lr
&
pc
ldmfd
sp
!,
{
r0
-
r12
,
lr
,
pc
}
@
pop
new
task
r0
-
r12
,
lr
&
pc
/*
*
void
rt_hw_context_switch_interrupt
(
rt_uint32
from
,
rt_uint32
to
)
;
...
...
@@ -81,15 +81,15 @@ rt_hw_context_switch_to:
.
globl
rt_interrupt_to_thread
.
globl
rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt
:
ldr
r2
,
=
rt_thread_switch_interrupt_flag
ldr
r3
,
[
r2
]
cmp
r3
,
#
1
beq
_reswitch
mov
r3
,
#
1
@
set
rt_thread_switch_interrupt_flag
to
1
str
r3
,
[
r2
]
ldr
r2
,
=
rt_interrupt_from_thread
@
set
rt_interrupt_from_thread
str
r0
,
[
r2
]
ldr
r2
,
=
rt_thread_switch_interrupt_flag
ldr
r3
,
[
r2
]
cmp
r3
,
#
1
beq
_reswitch
mov
r3
,
#
1
@
set
rt_thread_switch_interrupt_flag
to
1
str
r3
,
[
r2
]
ldr
r2
,
=
rt_interrupt_from_thread
@
set
rt_interrupt_from_thread
str
r0
,
[
r2
]
_reswitch
:
ldr
r2
,
=
rt_interrupt_to_thread
@
set
rt_interrupt_to_thread
str
r1
,
[
r2
]
mov
pc
,
lr
ldr
r2
,
=
rt_interrupt_to_thread
@
set
rt_interrupt_to_thread
str
r1
,
[
r2
]
mov
pc
,
lr
libcpu/arm/AT91SAM7X/context_rvds.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -8,96 +8,96 @@
*
2009
-
01
-
20
Bernard
first
version
*/
NOINT
EQU
0xc0
; disable interrupt in psr
NOINT
EQU
0xc0
; disable interrupt in psr
AREA
|.text|
,
CODE
,
READONLY
,
ALIGN
=
2
ARM
REQUIRE8
PRESERVE8
AREA
|.text|
,
CODE
,
READONLY
,
ALIGN
=
2
ARM
REQUIRE8
PRESERVE8
;/*
; * rt_base_t rt_hw_interrupt_disable();
; */
rt_hw_interrupt_disable
PROC
EXPORT
rt_hw_interrupt_disable
MRS
r0
,
cpsr
ORR
r1
,
r0
,
#
NOINT
MSR
cpsr_c
,
r1
BX
lr
ENDP
rt_hw_interrupt_disable
PROC
EXPORT
rt_hw_interrupt_disable
MRS
r0
,
cpsr
ORR
r1
,
r0
,
#
NOINT
MSR
cpsr_c
,
r1
BX
lr
ENDP
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
rt_hw_interrupt_enable
PROC
EXPORT
rt_hw_interrupt_enable
MSR
cpsr_c
,
r0
BX
lr
ENDP
rt_hw_interrupt_enable
PROC
EXPORT
rt_hw_interrupt_enable
MSR
cpsr_c
,
r0
BX
lr
ENDP
;/*
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
; * r0 --> from
; * r1 --> to
; */
rt_hw_context_switch
PROC
EXPORT
rt_hw_context_switch
STMFD
sp
!,
{
lr
}
; push pc (lr should be pushed in place of PC)
STMFD
sp
!,
{
r0
-
r12
,
lr
}
; push lr & register file
rt_hw_context_switch
PROC
EXPORT
rt_hw_context_switch
STMFD
sp
!,
{
lr
}
; push pc (lr should be pushed in place of PC)
STMFD
sp
!,
{
r0
-
r12
,
lr
}
; push lr & register file
MRS
r4
,
cpsr
STMFD
sp
!,
{
r4
}
; push cpsr
MRS
r4
,
spsr
STMFD
sp
!,
{
r4
}
; push spsr
MRS
r4
,
cpsr
STMFD
sp
!,
{
r4
}
; push cpsr
MRS
r4
,
spsr
STMFD
sp
!,
{
r4
}
; push spsr
STR
sp
,
[
r0
]
; store sp in preempted tasks TCB
LDR
sp
,
[
r1
]
; get new task stack pointer
STR
sp
,
[
r0
]
; store sp in preempted tasks TCB
LDR
sp
,
[
r1
]
; get new task stack pointer
LDMFD
sp
!,
{
r4
}
; pop new task spsr
MSR
spsr_cxsf
,
r4
LDMFD
sp
!,
{
r4
}
; pop new task cpsr
MSR
cpsr_cxsf
,
r4
LDMFD
sp
!,
{
r4
}
; pop new task spsr
MSR
spsr_cxsf
,
r4
LDMFD
sp
!,
{
r4
}
; pop new task cpsr
MSR
cpsr_cxsf
,
r4
LDMFD
sp
!,
{
r0
-
r12
,
lr
,
pc
}
; pop new task r0-r12, lr & pc
ENDP
LDMFD
sp
!,
{
r0
-
r12
,
lr
,
pc
}
; pop new task r0-r12, lr & pc
ENDP
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
; * r0 --> to
; */
rt_hw_context_switch_to
PROC
EXPORT
rt_hw_context_switch_to
LDR
sp
,
[
r0
]
; get new task stack pointer
rt_hw_context_switch_to
PROC
EXPORT
rt_hw_context_switch_to
LDR
sp
,
[
r0
]
; get new task stack pointer
LDMFD
sp
!,
{
r4
}
; pop new task spsr
MSR
spsr_cxsf
,
r4
LDMFD
sp
!,
{
r4
}
; pop new task cpsr
MSR
cpsr_cxsf
,
r4
LDMFD
sp
!,
{
r4
}
; pop new task spsr
MSR
spsr_cxsf
,
r4
LDMFD
sp
!,
{
r4
}
; pop new task cpsr
MSR
cpsr_cxsf
,
r4
LDMFD
sp
!,
{
r0
-
r12
,
lr
,
pc
}
; pop new task r0-r12, lr & pc
ENDP
LDMFD
sp
!,
{
r0
-
r12
,
lr
,
pc
}
; pop new task r0-r12, lr & pc
ENDP
;/*
; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
; */
IMPORT
rt_thread_switch_interrupt_flag
IMPORT
rt_interrupt_from_thread
IMPORT
rt_interrupt_to_thread
IMPORT
rt_thread_switch_interrupt_flag
IMPORT
rt_interrupt_from_thread
IMPORT
rt_interrupt_to_thread
rt_hw_context_switch_interrupt
PROC
EXPORT
rt_hw_context_switch_interrupt
LDR
r2
,
=
rt_thread_switch_interrupt_flag
LDR
r3
,
[
r2
]
CMP
r3
,
#
1
BEQ
_reswitch
MOV
r3
,
#
1
; set rt_thread_switch_interrupt_flag to 1
STR
r3
,
[
r2
]
LDR
r2
,
=
rt_interrupt_from_thread
; set rt_interrupt_from_thread
STR
r0
,
[
r2
]
rt_hw_context_switch_interrupt
PROC
EXPORT
rt_hw_context_switch_interrupt
LDR
r2
,
=
rt_thread_switch_interrupt_flag
LDR
r3
,
[
r2
]
CMP
r3
,
#
1
BEQ
_reswitch
MOV
r3
,
#
1
; set rt_thread_switch_interrupt_flag to 1
STR
r3
,
[
r2
]
LDR
r2
,
=
rt_interrupt_from_thread
; set rt_interrupt_from_thread
STR
r0
,
[
r2
]
_reswitch
LDR
r2
,
=
rt_interrupt_to_thread
; set rt_interrupt_to_thread
STR
r1
,
[
r2
]
BX
lr
ENDP
LDR
r2
,
=
rt_interrupt_to_thread
; set rt_interrupt_to_thread
STR
r1
,
[
r2
]
BX
lr
ENDP
END
\ No newline at end of file
END
libcpu/arm/AT91SAM7X/start_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -8,145 +8,145 @@
*
2006
-
08
-
31
Bernard
first
version
*/
/
*
Internal
Memory
Base
Addresses
*/
.
equ
FLASH_BASE
,
0x00100000
.
equ
RAM_BASE
,
0x00200000
/
*
Stack
Configuration
*/
.
equ
TOP_STACK
,
0x00204000
.
equ
UND_STACK_SIZE
,
0x00000100
.
equ
SVC_STACK_SIZE
,
0x00000400
.
equ
ABT_STACK_SIZE
,
0x00000100
.
equ
FIQ_STACK_SIZE
,
0x00000100
.
equ
IRQ_STACK_SIZE
,
0x00000100
.
equ
USR_STACK_SIZE
,
0x00000004
/
*
ARM
architecture
definitions
*/
.
equ
MODE_USR
,
0x10
.
equ
MODE_FIQ
,
0x11
.
equ
MODE_IRQ
,
0x12
.
equ
MODE_SVC
,
0x13
.
equ
MODE_ABT
,
0x17
.
equ
MODE_UND
,
0x1B
.
equ
MODE_SYS
,
0x1F
.
equ
I_BIT
,
0x80
/*
when
this
bit
is
set
,
IRQ
is
disabled
*/
.
equ
F_BIT
,
0x40
/*
when
this
bit
is
set
,
FIQ
is
disabled
*/
/
*
Internal
Memory
Base
Addresses
*/
.
equ
FLASH_BASE
,
0x00100000
.
equ
RAM_BASE
,
0x00200000
/
*
Stack
Configuration
*/
.
equ
TOP_STACK
,
0x00204000
.
equ
UND_STACK_SIZE
,
0x00000100
.
equ
SVC_STACK_SIZE
,
0x00000400
.
equ
ABT_STACK_SIZE
,
0x00000100
.
equ
FIQ_STACK_SIZE
,
0x00000100
.
equ
IRQ_STACK_SIZE
,
0x00000100
.
equ
USR_STACK_SIZE
,
0x00000004
/
*
ARM
architecture
definitions
*/
.
equ
MODE_USR
,
0x10
.
equ
MODE_FIQ
,
0x11
.
equ
MODE_IRQ
,
0x12
.
equ
MODE_SVC
,
0x13
.
equ
MODE_ABT
,
0x17
.
equ
MODE_UND
,
0x1B
.
equ
MODE_SYS
,
0x1F
.
equ
I_BIT
,
0x80
/*
when
this
bit
is
set
,
IRQ
is
disabled
*/
.
equ
F_BIT
,
0x40
/*
when
this
bit
is
set
,
FIQ
is
disabled
*/
.
section
.
init
,
"ax"
.
code
32
.
align
0
.
globl
_start
_start
:
b
reset
ldr
pc
,
_vector_undef
ldr
pc
,
_vector_swi
ldr
pc
,
_vector_pabt
ldr
pc
,
_vector_dabt
nop
/*
reserved
vector
*/
ldr
pc
,
_vector_irq
ldr
pc
,
_vector_fiq
_vector_undef
:
.
word
vector_undef
_vector_swi
:
.
word
vector_swi
_vector_pabt
:
.
word
vector_pabt
_vector_dabt
:
.
word
vector_dabt
_vector_resv
:
.
word
vector_resv
_vector_irq
:
.
word
vector_irq
_vector_fiq
:
.
word
vector_fiq
b
reset
ldr
pc
,
_vector_undef
ldr
pc
,
_vector_swi
ldr
pc
,
_vector_pabt
ldr
pc
,
_vector_dabt
nop
/*
reserved
vector
*/
ldr
pc
,
_vector_irq
ldr
pc
,
_vector_fiq
_vector_undef
:
.
word
vector_undef
_vector_swi
:
.
word
vector_swi
_vector_pabt
:
.
word
vector_pabt
_vector_dabt
:
.
word
vector_dabt
_vector_resv
:
.
word
vector_resv
_vector_irq
:
.
word
vector_irq
_vector_fiq
:
.
word
vector_fiq
/*
*
rtthread
bss
start
and
end
*
which
are
defined
in
linker
script
*/
.
globl
_bss_start
_bss_start
:
.
word
__bss_start
_bss_start
:
.
word
__bss_start
.
globl
_bss_end
_bss_end
:
.
word
__bss_end
_bss_end
:
.
word
__bss_end
/*
the
system
entry
*/
reset
:
/
*
disable
watchdog
*/
ldr
r0
,
=
0xFFFFFD40
ldr
r1
,
=
0x00008000
str
r1
,
[
r0
,
#
0x04
]
/
*
enable
the
main
oscillator
*/
ldr
r0
,
=
0xFFFFFC00
ldr
r1
,
=
0x00000601
str
r1
,
[
r0
,
#
0x20
]
/
*
wait
for
main
oscillator
to
stabilize
*/
/
*
disable
watchdog
*/
ldr
r0
,
=
0xFFFFFD40
ldr
r1
,
=
0x00008000
str
r1
,
[
r0
,
#
0x04
]
/
*
enable
the
main
oscillator
*/
ldr
r0
,
=
0xFFFFFC00
ldr
r1
,
=
0x00000601
str
r1
,
[
r0
,
#
0x20
]
/
*
wait
for
main
oscillator
to
stabilize
*/
moscs_loop
:
ldr
r2
,
[
r0
,
#
0x68
]
ands
r2
,
r2
,
#
1
beq
moscs_loop
/
*
set
up
the
PLL
*/
ldr
r1
,
=
0x00191C05
str
r1
,
[
r0
,
#
0x2C
]
/
*
wait
for
PLL
to
lock
*/
ldr
r2
,
[
r0
,
#
0x68
]
ands
r2
,
r2
,
#
1
beq
moscs_loop
/
*
set
up
the
PLL
*/
ldr
r1
,
=
0x00191C05
str
r1
,
[
r0
,
#
0x2C
]
/
*
wait
for
PLL
to
lock
*/
pll_loop
:
ldr
r2
,
[
r0
,
#
0x68
]
ands
r2
,
r2
,
#
0x04
beq
pll_loop
/
*
select
clock
*/
ldr
r1
,
=
0x00000007
str
r1
,
[
r0
,
#
0x30
]
ldr
r2
,
[
r0
,
#
0x68
]
ands
r2
,
r2
,
#
0x04
beq
pll_loop
/
*
select
clock
*/
ldr
r1
,
=
0x00000007
str
r1
,
[
r0
,
#
0x30
]
#ifdef __FLASH_BUILD__
/
*
copy
exception
vectors
into
internal
sram
*/
/
*
copy
exception
vectors
into
internal
sram
*/
/
*
mov
r8
,
#
RAM_BASE
ldr
r9
,
=
_start
ldmia
r9
!,
{
r0
-
r7
}
stmia
r8
!,
{
r0
-
r7
}
ldmia
r9
!,
{
r0
-
r6
}
stmia
r8
!,
{
r0
-
r6
}
mov
r8
,
#
RAM_BASE
ldr
r9
,
=
_start
ldmia
r9
!,
{
r0
-
r7
}
stmia
r8
!,
{
r0
-
r7
}
ldmia
r9
!,
{
r0
-
r6
}
stmia
r8
!,
{
r0
-
r6
}
*/
#endif
/
*
setup
stack
for
each
mode
*/
ldr
r0
,
=
TOP_STACK
/
*
set
stack
*/
/
*
undefined
instruction
mode
*/
msr
cpsr_c
,
#
MODE_UND|I_BIT|F_BIT
mov
sp
,
r0
sub
r0
,
r0
,
#
UND_STACK_SIZE
/
*
abort
mode
*/
msr
cpsr_c
,
#
MODE_ABT|I_BIT|F_BIT
mov
sp
,
r0
sub
r0
,
r0
,
#
ABT_STACK_SIZE
/
*
FIQ
mode
*/
msr
cpsr_c
,
#
MODE_FIQ|I_BIT|F_BIT
mov
sp
,
r0
sub
r0
,
r0
,
#
FIQ_STACK_SIZE
/
*
IRQ
mode
*/
msr
cpsr_c
,
#
MODE_IRQ|I_BIT|F_BIT
mov
sp
,
r0
sub
r0
,
r0
,
#
IRQ_STACK_SIZE
/
*
supervisor
mode
*/
msr
cpsr_c
,
#
MODE_SVC|I_BIT|F_BIT
mov
sp
,
r0
/
*
remap
SRAM
to
0x0000
*/
/
*
ldr
r0
,
=
0xFFFFFF00
mov
r1
,
#
0x01
str
r1
,
[
r0
]
*/
/
*
mask
all
IRQs
*/
ldr
r1
,
=
0xFFFFF124
ldr
r0
,
=
0XFFFFFFFF
str
r0
,
[
r1
]
/
*
setup
stack
for
each
mode
*/
ldr
r0
,
=
TOP_STACK
/
*
set
stack
*/
/
*
undefined
instruction
mode
*/
msr
cpsr_c
,
#
MODE_UND|I_BIT|F_BIT
mov
sp
,
r0
sub
r0
,
r0
,
#
UND_STACK_SIZE
/
*
abort
mode
*/
msr
cpsr_c
,
#
MODE_ABT|I_BIT|F_BIT
mov
sp
,
r0
sub
r0
,
r0
,
#
ABT_STACK_SIZE
/
*
FIQ
mode
*/
msr
cpsr_c
,
#
MODE_FIQ|I_BIT|F_BIT
mov
sp
,
r0
sub
r0
,
r0
,
#
FIQ_STACK_SIZE
/
*
IRQ
mode
*/
msr
cpsr_c
,
#
MODE_IRQ|I_BIT|F_BIT
mov
sp
,
r0
sub
r0
,
r0
,
#
IRQ_STACK_SIZE
/
*
supervisor
mode
*/
msr
cpsr_c
,
#
MODE_SVC|I_BIT|F_BIT
mov
sp
,
r0
/
*
remap
SRAM
to
0x0000
*/
/
*
ldr
r0
,
=
0xFFFFFF00
mov
r1
,
#
0x01
str
r1
,
[
r0
]
*/
/
*
mask
all
IRQs
*/
ldr
r1
,
=
0xFFFFF124
ldr
r0
,
=
0XFFFFFFFF
str
r0
,
[
r1
]
/
*
copy
.
data
to
SRAM
*/
ldr
r1
,
=
_sidata
/*
.
data
start
in
image
*/
...
...
@@ -187,14 +187,14 @@ ctor_loop:
b
ctor_loop
ctor_end
:
/
*
start
RT
-
Thread
Kernel
*/
ldr
pc
,
_rtthread_startup
/
*
start
RT
-
Thread
Kernel
*/
ldr
pc
,
_rtthread_startup
_rtthread_startup
:
.
word
rtthread_startup
/*
exception
handlers
*/
vector_undef
:
b
vector_undef
vector_undef
:
b
vector_undef
vector_swi
:
b
vector_swi
vector_pabt
:
b
vector_pabt
vector_dabt
:
b
vector_dabt
...
...
@@ -206,70 +206,70 @@ vector_resv : b vector_resv
.
globl
rt_interrupt_from_thread
.
globl
rt_interrupt_to_thread
vector_irq
:
stmfd
sp
!,
{
r0
-
r12
,
lr
}
bl
rt_interrupt_enter
bl
rt_hw_trap_irq
bl
rt_interrupt_leave
/
*
*
if
rt_thread_switch_interrupt_flag
set
,
jump
to
*
rt_hw_context_switch_interrupt_do
and
don
't return
*/
ldr
r0
,
=
rt_thread_switch_interrupt_flag
ldr
r1
,
[
r0
]
cmp
r1
,
#
1
beq
rt_hw_context_switch_interrupt_do
ldmfd
sp
!,
{
r0
-
r12
,
lr
}
subs
pc
,
lr
,
#
4
stmfd
sp
!,
{
r0
-
r12
,
lr
}
bl
rt_interrupt_enter
bl
rt_hw_trap_irq
bl
rt_interrupt_leave
/
*
*
if
rt_thread_switch_interrupt_flag
set
,
jump
to
*
rt_hw_context_switch_interrupt_do
and
don
't return
*/
ldr
r0
,
=
rt_thread_switch_interrupt_flag
ldr
r1
,
[
r0
]
cmp
r1
,
#
1
beq
rt_hw_context_switch_interrupt_do
ldmfd
sp
!,
{
r0
-
r12
,
lr
}
subs
pc
,
lr
,
#
4
vector_fiq
:
stmfd
sp
!,{
r0
-
r7
,
lr
}
bl
rt_hw_trap_fiq
ldmfd
sp
!,{
r0
-
r7
,
lr
}
subs
pc
,
lr
,#
4
stmfd
sp
!,{
r0
-
r7
,
lr
}
bl
rt_hw_trap_fiq
ldmfd
sp
!,{
r0
-
r7
,
lr
}
subs
pc
,
lr
,#
4
/*
*
void
rt_hw_context_switch_interrupt_do
(
rt_base_t
flag
)
*/
rt_hw_context_switch_interrupt_do
:
mov
r1
,
#
0
@
clear
flag
str
r1
,
[
r0
]
ldmfd
sp
!,
{
r0
-
r12
,
lr
}
@
reload
saved
registers
stmfd
sp
!,
{
r0
-
r3
}
@
save
r0
-
r3
mov
r1
,
sp
add
sp
,
sp
,
#
16
@
restore
sp
sub
r2
,
lr
,
#
4
@
save
old
task
's pc to r2
mrs
r3
,
spsr
@
disable
interrupt
orr
r0
,
r3
,
#
I_BIT
|
F_BIT
msr
spsr_c
,
r0
ldr
r0
,
=
.
+
8
@
switch
to
interrupted
task
's stack
movs
pc
,
r0
stmfd
sp
!,
{
r2
}
@
push
old
task
's pc
stmfd
sp
!,
{
r4
-
r12
,
lr
}
@
push
old
task
's lr,r12-r4
mov
r4
,
r1
@
Special
optimised
code
below
mov
r5
,
r3
ldmfd
r4
!,
{
r0
-
r3
}
stmfd
sp
!,
{
r0
-
r3
}
@
push
old
task
's r3-r0
stmfd
sp
!,
{
r5
}
@
push
old
task
's psr
mrs
r4
,
spsr
stmfd
sp
!,
{
r4
}
@
push
old
task
's spsr
ldr
r4
,
=
rt_interrupt_from_thread
ldr
r5
,
[
r4
]
str
sp
,
[
r5
]
@
store
sp
in
preempted
tasks
's TCB
ldr
r6
,
=
rt_interrupt_to_thread
ldr
r6
,
[
r6
]
ldr
sp
,
[
r6
]
@
get
new
task
's stack pointer
ldmfd
sp
!,
{
r4
}
@
pop
new
task
's spsr
msr
SPSR_cxsf
,
r4
ldmfd
sp
!,
{
r4
}
@
pop
new
task
's psr
msr
CPSR_cxsf
,
r4
ldmfd
sp
!,
{
r0
-
r12
,
lr
,
pc
}
@
pop
new
task
's r0-r12,lr & pc
mov
r1
,
#
0
@
clear
flag
str
r1
,
[
r0
]
ldmfd
sp
!,
{
r0
-
r12
,
lr
}
@
reload
saved
registers
stmfd
sp
!,
{
r0
-
r3
}
@
save
r0
-
r3
mov
r1
,
sp
add
sp
,
sp
,
#
16
@
restore
sp
sub
r2
,
lr
,
#
4
@
save
old
task
's pc to r2
mrs
r3
,
spsr
@
disable
interrupt
orr
r0
,
r3
,
#
I_BIT
|
F_BIT
msr
spsr_c
,
r0
ldr
r0
,
=
.
+
8
@
switch
to
interrupted
task
's stack
movs
pc
,
r0
stmfd
sp
!,
{
r2
}
@
push
old
task
's pc
stmfd
sp
!,
{
r4
-
r12
,
lr
}
@
push
old
task
's lr,r12-r4
mov
r4
,
r1
@
Special
optimised
code
below
mov
r5
,
r3
ldmfd
r4
!,
{
r0
-
r3
}
stmfd
sp
!,
{
r0
-
r3
}
@
push
old
task
's r3-r0
stmfd
sp
!,
{
r5
}
@
push
old
task
's psr
mrs
r4
,
spsr
stmfd
sp
!,
{
r4
}
@
push
old
task
's spsr
ldr
r4
,
=
rt_interrupt_from_thread
ldr
r5
,
[
r4
]
str
sp
,
[
r5
]
@
store
sp
in
preempted
tasks
's TCB
ldr
r6
,
=
rt_interrupt_to_thread
ldr
r6
,
[
r6
]
ldr
sp
,
[
r6
]
@
get
new
task
's stack pointer
ldmfd
sp
!,
{
r4
}
@
pop
new
task
's spsr
msr
SPSR_cxsf
,
r4
ldmfd
sp
!,
{
r4
}
@
pop
new
task
's psr
msr
CPSR_cxsf
,
r4
ldmfd
sp
!,
{
r0
-
r12
,
lr
,
pc
}
@
pop
new
task
's r0-r12,lr & pc
libcpu/arm/am335x/cp15_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -26,7 +26,7 @@ rt_cpu_get_sctlr:
.
globl
rt_cpu_dcache_enable
rt_cpu_dcache_enable
:
mrc
p15
,
#
0
,
r0
,
c1
,
c0
,
#
0
mrc
p15
,
#
0
,
r0
,
c1
,
c0
,
#
0
orr
r0
,
r0
,
#
0x00000004
mcr
p15
,
#
0
,
r0
,
c1
,
c0
,
#
0
bx
lr
...
...
@@ -35,7 +35,7 @@ rt_cpu_dcache_enable:
rt_cpu_icache_enable
:
mrc
p15
,
#
0
,
r0
,
c1
,
c0
,
#
0
orr
r0
,
r0
,
#
0x00001000
mcr
p15
,
#
0
,
r0
,
c1
,
c0
,
#
0
mcr
p15
,
#
0
,
r0
,
c1
,
c0
,
#
0
bx
lr
_FLD_MAX_WAY
:
...
...
@@ -45,48 +45,48 @@ _FLD_MAX_IDX:
.
globl
rt_cpu_dcache_clean_flush
rt_cpu_dcache_clean_flush
:
push
{
r4
-
r11
}
dmb
push
{
r4
-
r11
}
dmb
mrc
p15
,
#
1
,
r0
,
c0
,
c0
,
#
1
@
read
clid
register
ands
r3
,
r0
,
#
0x7000000
@
get
level
of
coherency
mov
r3
,
r3
,
lsr
#
23
beq
finished
mov
r10
,
#
0
mov
r3
,
r3
,
lsr
#
23
beq
finished
mov
r10
,
#
0
loop1
:
add
r2
,
r10
,
r10
,
lsr
#
1
add
r2
,
r10
,
r10
,
lsr
#
1
mov
r1
,
r0
,
lsr
r2
and
r1
,
r1
,
#
7
cmp
r1
,
#
2
blt
skip
mcr
p15
,
#
2
,
r10
,
c0
,
c0
,
#
0
isb
mrc
p15
,
#
1
,
r1
,
c0
,
c0
,
#
0
and
r2
,
r1
,
#
7
add
r2
,
r2
,
#
4
ldr
r4
,
_FLD_MAX_WAY
and
r1
,
r1
,
#
7
cmp
r1
,
#
2
blt
skip
mcr
p15
,
#
2
,
r10
,
c0
,
c0
,
#
0
isb
mrc
p15
,
#
1
,
r1
,
c0
,
c0
,
#
0
and
r2
,
r1
,
#
7
add
r2
,
r2
,
#
4
ldr
r4
,
_FLD_MAX_WAY
ands
r4
,
r4
,
r1
,
lsr
#
3
clz
r5
,
r4
ldr
r7
,
_FLD_MAX_IDX
ands
r7
,
r7
,
r1
,
lsr
#
13
ands
r7
,
r7
,
r1
,
lsr
#
13
loop2
:
mov
r9
,
r4
mov
r9
,
r4
loop3
:
orr
r11
,
r10
,
r9
,
lsl
r5
orr
r11
,
r11
,
r7
,
lsl
r2
mcr
p15
,
#
0
,
r11
,
c7
,
c14
,
#
2
subs
r9
,
r9
,
#
1
bge
loop3
subs
r7
,
r7
,
#
1
bge
loop2
skip
:
add
r10
,
r10
,
#
2
cmp
r3
,
r10
bgt
loop1
orr
r11
,
r10
,
r9
,
lsl
r5
orr
r11
,
r11
,
r7
,
lsl
r2
mcr
p15
,
#
0
,
r11
,
c7
,
c14
,
#
2
subs
r9
,
r9
,
#
1
bge
loop3
subs
r7
,
r7
,
#
1
bge
loop2
skip
:
add
r10
,
r10
,
#
2
cmp
r3
,
r10
bgt
loop1
finished
:
dsb
isb
pop
{
r4
-
r11
}
isb
pop
{
r4
-
r11
}
bx
lr
.
globl
rt_cpu_dcache_disable
...
...
@@ -108,11 +108,11 @@ rt_cpu_icache_disable:
.
globl
rt_cpu_mmu_disable
rt_cpu_mmu_disable
:
mcr
p15
,
#
0
,
r0
,
c8
,
c7
,
#
0
@
invalidate
tlb
mrc
p15
,
#
0
,
r0
,
c1
,
c0
,
#
0
bic
r0
,
r0
,
#
1
mcr
p15
,
#
0
,
r0
,
c8
,
c7
,
#
0
@
invalidate
tlb
mrc
p15
,
#
0
,
r0
,
c1
,
c0
,
#
0
bic
r0
,
r0
,
#
1
mcr
p15
,
#
0
,
r0
,
c1
,
c0
,
#
0
@
clear
mmu
bit
dsb
dsb
bx
lr
.
globl
rt_cpu_mmu_enable
...
...
libcpu/arm/am335x/cp15_iar.s
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -7,9 +7,9 @@
*
Date
Author
Notes
*
2015
-
04
-
06
zchong
change
to
iar
compiler
from
convert
from
cp15_gcc
.
S
*/
SECTION
.
text
:
CODE
:
NOROOT
(
2
)
ARM
EXPORT
rt_cpu_vector_set_base
...
...
@@ -17,7 +17,7 @@ rt_cpu_vector_set_base:
MCR
p15
,
#
0
,
r0
,
c12
,
c0
,
#
0
DSB
BX
lr
EXPORT
rt_cpu_vector_get_base
rt_cpu_vector_get_base
:
MRC
p15
,
#
0
,
r0
,
c12
,
c0
,
#
0
...
...
@@ -30,7 +30,7 @@ rt_cpu_get_sctlr:
EXPORT
rt_cpu_dcache_enable
rt_cpu_dcache_enable
:
MRC
p15
,
#
0
,
r0
,
c1
,
c0
,
#
0
MRC
p15
,
#
0
,
r0
,
c1
,
c0
,
#
0
ORR
r0
,
r0
,
#
0x00000004
MCR
p15
,
#
0
,
r0
,
c1
,
c0
,
#
0
BX
lr
...
...
@@ -39,7 +39,7 @@ rt_cpu_dcache_enable:
rt_cpu_icache_enable
:
MRC
p15
,
#
0
,
r0
,
c1
,
c0
,
#
0
ORR
r0
,
r0
,
#
0x00001000
MCR
p15
,
#
0
,
r0
,
c1
,
c0
,
#
0
MCR
p15
,
#
0
,
r0
,
c1
,
c0
,
#
0
BX
lr
;_FLD_MAX_WAY DEFINE 0x3ff
...
...
@@ -48,50 +48,50 @@ rt_cpu_icache_enable:
EXPORT
rt_cpu_dcache_clean_flush
rt_cpu_dcache_clean_flush
:
PUSH
{
r4
-
r11
}
DMB
PUSH
{
r4
-
r11
}
DMB
MRC
p15
,
#
1
,
r0
,
c0
,
c0
,
#
1
; read clid register
ANDS
r3
,
r0
,
#
0x7000000
; get level of coherency
MOV
r3
,
r3
,
lsr
#
23
BEQ
finished
MOV
r10
,
#
0
MOV
r3
,
r3
,
lsr
#
23
BEQ
finished
MOV
r10
,
#
0
loop1
:
ADD
r2
,
r10
,
r10
,
lsr
#
1
ADD
r2
,
r10
,
r10
,
lsr
#
1
MOV
r1
,
r0
,
lsr
r2
AND
r1
,
r1
,
#
7
CMP
r1
,
#
2
BLT
skip
MCR
p15
,
#
2
,
r10
,
c0
,
c0
,
#
0
ISB
MRC
p15
,
#
1
,
r1
,
c0
,
c0
,
#
0
AND
r2
,
r1
,
#
7
ADD
r2
,
r2
,
#
4
;LDR r4, _FLD_MAX_WAY
AND
r1
,
r1
,
#
7
CMP
r1
,
#
2
BLT
skip
MCR
p15
,
#
2
,
r10
,
c0
,
c0
,
#
0
ISB
MRC
p15
,
#
1
,
r1
,
c0
,
c0
,
#
0
AND
r2
,
r1
,
#
7
ADD
r2
,
r2
,
#
4
;LDR r4, _FLD_MAX_WAY
LDR
r4
,
=
0x3FF
ANDS
r4
,
r4
,
r1
,
lsr
#
3
CLZ
r5
,
r4
;LDR r7, _FLD_MAX_IDX
LDR
r7
,
=
0x7FF
ANDS
r7
,
r7
,
r1
,
lsr
#
13
ANDS
r7
,
r7
,
r1
,
lsr
#
13
loop2
:
MOV
r9
,
r4
MOV
r9
,
r4
loop3
:
ORR
r11
,
r10
,
r9
,
lsl
r5
ORR
r11
,
r11
,
r7
,
lsl
r2
MCR
p15
,
#
0
,
r11
,
c7
,
c14
,
#
2
SUBS
r9
,
r9
,
#
1
BGE
loop3
SUBS
r7
,
r7
,
#
1
BGE
loop2
skip
:
ADD
r10
,
r10
,
#
2
CMP
r3
,
r10
BGT
loop1
ORR
r11
,
r10
,
r9
,
lsl
r5
ORR
r11
,
r11
,
r7
,
lsl
r2
MCR
p15
,
#
0
,
r11
,
c7
,
c14
,
#
2
SUBS
r9
,
r9
,
#
1
BGE
loop3
SUBS
r7
,
r7
,
#
1
BGE
loop2
skip
:
ADD
r10
,
r10
,
#
2
CMP
r3
,
r10
BGT
loop1
finished
:
DSB
ISB
POP
{
r4
-
r11
}
ISB
POP
{
r4
-
r11
}
BX
lr
...
...
@@ -115,11 +115,11 @@ rt_cpu_icache_disable:
EXPORT
rt_cpu_mmu_disable
rt_cpu_mmu_disable
:
MCR
p15
,
#
0
,
r0
,
c8
,
c7
,
#
0
; invalidate tlb
MRC
p15
,
#
0
,
r0
,
c1
,
c0
,
#
0
BIC
r0
,
r0
,
#
1
MCR
p15
,
#
0
,
r0
,
c8
,
c7
,
#
0
; invalidate tlb
MRC
p15
,
#
0
,
r0
,
c1
,
c0
,
#
0
BIC
r0
,
r0
,
#
1
MCR
p15
,
#
0
,
r0
,
c1
,
c0
,
#
0
; clear mmu bit
DSB
DSB
BX
lr
EXPORT
rt_cpu_mmu_enable
...
...
@@ -135,5 +135,5 @@ rt_cpu_tlb_set:
MCR
p15
,
#
0
,
r0
,
c2
,
c0
,
#
0
DMB
BX
lr
END
libcpu/arm/am335x/start_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -65,7 +65,7 @@ bss_loop:
/
*
call
C
++
constructors
of
global
objects
*/
ldr
r0
,
=
__ctors_start__
ldr
r1
,
=
__ctors_end__
ctor_loop
:
cmp
r0
,
r1
beq
ctor_end
...
...
@@ -150,7 +150,7 @@ vector_undef:
vector_swi
:
bl
rt_hw_trap_swi
.
align
5
.
align
5
.
globl
vector_pabt
vector_pabt
:
bl
rt_hw_trap_pabt
...
...
libcpu/arm/am335x/start_iar.s
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
*
Change
Logs
:
*
Date
Author
Notes
*
2015
-
04
-
06
zchong
the
first
version
*
2015
-
04
-
06
zchong
the
first
version
*/
MODULE
?
cstartup
; --------------------
; Mode, correspords to bits 0-5 in CPSR
...
...
@@ -25,7 +25,7 @@ ABT_MODE DEFINE 0x17 ; Abort mode
UND_MODE
DEFINE
0x1B
; Undefined Instruction mode
SYS_MODE
DEFINE
0x1F
; System mode
;; Forward declaration of sections.
SECTION
IRQ_STACK
:
DATA
:
NOROOT
(
3
)
SECTION
FIQ_STACK
:
DATA
:
NOROOT
(
3
)
...
...
@@ -34,8 +34,8 @@ SYS_MODE DEFINE 0x1F ; System mode
SECTION
UND_STACK
:
DATA
:
NOROOT
(
3
)
SECTION
CSTACK
:
DATA
:
NOROOT
(
3
)
SECTION
.
text
:
CODE
SECTION
.
intvec
:
CODE
:
NOROOT
(
5
)
PUBLIC
__vector
...
...
@@ -95,7 +95,7 @@ FIQ_Addr: DCD FIQ_Handler
EXTERN
rt_current_thread
EXTERN
vmm_thread
EXTERN
vmm_virq_check
EXTERN
__cmain
REQUIRE
__vector
EXTWEAK
__iar_init_core
...
...
@@ -135,7 +135,7 @@ __iar_program_start:
MSR
cpsr_c
,
r0
; Change the mode
LDR
sp
,
=
SFE
(
FIQ_STACK
)
; End of FIQ_STACK
BIC
sp
,
sp
,#
0x7
; Make sure SP is 8 aligned
BIC
r0
,
r0
,#
MODE_MSK
; Clear the mode bits
ORR
r0
,
r0
,#
ABT_MODE
; Set Abort mode bits
MSR
cpsr_c
,
r0
; Change the mode
...
...
@@ -165,7 +165,7 @@ __iar_program_start:
;; Continue to __cmain for C-level initialization.
B
__cmain
Undefined_Handler
:
SUB
sp
,
sp
,
#
72
STMIA
sp
,
{
r0
-
r12
}
;/* Calling r0-r12 */
...
...
@@ -217,7 +217,7 @@ Abort_Handler:
LDR
lr
,
[
sp
,
#
60
]
;/* Get PC */
ADD
sp
,
sp
,
#
72
MOVS
pc
,
lr
;/* return & move spsr_svc into cpsr */
FIQ_Handler
:
STMFD
sp
!,{
r0
-
r7
,
lr
}
BL
rt_hw_trap_fiq
...
...
@@ -274,5 +274,5 @@ rt_hw_context_switch_interrupt_do:
MSR
spsr_cxsf
,
r4
LDMFD
sp
!,
{
r0
-
r12
,
lr
,
pc
}^
; pop new task's r0-r12,lr & pc, copy spsr to cpsr
END
libcpu/arm/am335x/vector_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -48,4 +48,4 @@ _vector_irq:
_vector_fiq
:
.
word
vector_fiq
.
balignl
16,0
xdeadbeef
.
balignl
16,0
xdeadbeef
libcpu/arm/arm926/context_iar.S
浏览文件 @
563e4989
...
...
@@ -79,4 +79,4 @@ _reswitch:
STR
R1
,
[
R2
]
MOV
PC
,
LR
END
libcpu/arm/arm926/start_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -71,7 +71,7 @@ _vector_fiq:
/
*
**************************************
*
*
Stack
and
Heap
Definitions
*
Stack
and
Heap
Definitions
**************************************
*
*/
.
section
.
data
...
...
@@ -107,7 +107,7 @@ svc_stack_start:
/*
**************************************
*
*
Startup
Code
*
Startup
Code
**************************************
*
*/
.
section
.
text
...
...
@@ -126,10 +126,10 @@ reset:
ldr
sp
,
=
svc_stack_start
ldr
r0
,
=
rt_low_level_init
blx
r0
/
*
init
stack
*/
bl
stack_setup
/
*
clear
bss
*/
mov
r0
,
#
0
ldr
r1
,
=
__bss_start
...
...
@@ -139,7 +139,7 @@ bss_clear_loop:
cmp
r1
,
r2
strlo
r0
,
[
r1
],
#
4
blo
bss_clear_loop
/
*
call
c
++
constructors
of
global
objects
*/
/
*
ldr
r0
,
=
__ctors_start__
...
...
@@ -178,7 +178,7 @@ cpu_init_crit:
mcr
p15
,
0
,
r0
,
c1
,
c0
,
0
bx
lr
stack_setup
:
/
*
Setup
Stack
for
each
mode
*/
mrs
r0
,
cpsr
...
...
@@ -209,10 +209,10 @@ stack_setup:
ldr
sp
,
=
svc_stack_start
bx
lr
/*
**************************************
*
*
exception
handlers
*
exception
handlers
**************************************
*
*/
/
*
Interrupt
*/
...
...
@@ -238,42 +238,42 @@ vector_irq:
subs
pc
,
lr
,
#
4
rt_hw_context_switch_interrupt_do
:
mov
r1
,
#
0
mov
r1
,
#
0
str
r1
,
[
r0
]
mov
r1
,
sp
mov
r1
,
sp
add
sp
,
sp
,
#
4
*
4
ldmfd
sp
!,
{
r4
-
r12
,
lr
}
mrs
r0
,
spsr
sub
r2
,
lr
,
#
4
mrs
r0
,
spsr
sub
r2
,
lr
,
#
4
msr
cpsr_c
,
#
I_BIT|F_BIT|MODE_SVC
stmfd
sp
!,
{
r2
}
stmfd
sp
!,
{
r2
}
stmfd
sp
!,
{
r4
-
r12
,
lr
}
ldmfd
r1
,
{
r1
-
r4
}
stmfd
sp
!,
{
r1
-
r4
}
stmfd
sp
!,
{
r0
}
ldmfd
r1
,
{
r1
-
r4
}
stmfd
sp
!,
{
r1
-
r4
}
stmfd
sp
!,
{
r0
}
ldr
r4
,
=
rt_interrupt_from_thread
ldr
r5
,
[
r4
]
str
sp
,
[
r5
]
str
sp
,
[
r5
]
ldr
r6
,
=
rt_interrupt_to_thread
ldr
r6
,
[
r6
]
ldr
sp
,
[
r6
]
ldr
sp
,
[
r6
]
ldmfd
sp
!,
{
r4
}
ldmfd
sp
!,
{
r4
}
msr
spsr_cxsf
,
r4
ldmfd
sp
!,
{
r0
-
r12
,
lr
,
pc
}^
ldmfd
sp
!,
{
r0
-
r12
,
lr
,
pc
}^
/
*
Exception
*/
.
macro
push_svc_reg
sub
sp
,
sp
,
#
17
*
4
stmia
sp
,
{
r0
-
r12
}
stmia
sp
,
{
r0
-
r12
}
mov
r0
,
sp
mrs
r6
,
spsr
mrs
r6
,
spsr
str
lr
,
[
r0
,
#
15
*
4
]
str
r6
,
[
r0
,
#
16
*
4
]
str
sp
,
[
r0
,
#
13
*
4
]
...
...
libcpu/arm/armv6/arm_entry_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -14,113 +14,113 @@
//#
define
DEBUG
.
macro
PRINT
,
str
.
macro
PRINT
,
str
#ifdef DEBUG
stmfd
sp
!,
{
r0
-
r3
,
ip
,
lr
}
add
r0
,
pc
,
#
4
bl
rt_kprintf
b
1
f
.
asciz
"UNDEF: \str\n"
.
balign
4
1
:
ldmfd
sp
!,
{
r0
-
r3
,
ip
,
lr
}
stmfd
sp
!,
{
r0
-
r3
,
ip
,
lr
}
add
r0
,
pc
,
#
4
bl
rt_kprintf
b
1
f
.
asciz
"UNDEF: \str\n"
.
balign
4
1
:
ldmfd
sp
!,
{
r0
-
r3
,
ip
,
lr
}
#endif
.
endm
.
endm
.
macro
PRINT1
,
str
,
arg
#ifdef DEBUG
stmfd
sp
!,
{
r0
-
r3
,
ip
,
lr
}
mov
r1
,
\
arg
add
r0
,
pc
,
#
4
bl
rt_kprintf
b
1
f
.
asciz
"UNDEF: \str\n"
.
balign
4
1
:
ldmfd
sp
!,
{
r0
-
r3
,
ip
,
lr
}
stmfd
sp
!,
{
r0
-
r3
,
ip
,
lr
}
mov
r1
,
\
arg
add
r0
,
pc
,
#
4
bl
rt_kprintf
b
1
f
.
asciz
"UNDEF: \str\n"
.
balign
4
1
:
ldmfd
sp
!,
{
r0
-
r3
,
ip
,
lr
}
#endif
.
endm
.
endm
.
macro
PRINT3
,
str
,
arg1
,
arg2
,
arg3
#ifdef DEBUG
stmfd
sp
!,
{
r0
-
r3
,
ip
,
lr
}
mov
r3
,
\
arg3
mov
r2
,
\
arg2
mov
r1
,
\
arg1
add
r0
,
pc
,
#
4
bl
rt_kprintf
b
1
f
.
asciz
"UNDEF: \str\n"
.
balign
4
1
:
ldmfd
sp
!,
{
r0
-
r3
,
ip
,
lr
}
stmfd
sp
!,
{
r0
-
r3
,
ip
,
lr
}
mov
r3
,
\
arg3
mov
r2
,
\
arg2
mov
r1
,
\
arg1
add
r0
,
pc
,
#
4
bl
rt_kprintf
b
1
f
.
asciz
"UNDEF: \str\n"
.
balign
4
1
:
ldmfd
sp
!,
{
r0
-
r3
,
ip
,
lr
}
#endif
.
endm
.
endm
.
macro
get_current_thread
,
rd
ldr
\
rd
,
.
current_thread
ldr
\
rd
,
[
\
rd
]
.
endm
.
macro
get_current_thread
,
rd
ldr
\
rd
,
.
current_thread
ldr
\
rd
,
[
\
rd
]
.
endm
.
current_thread
:
.
word
rt_current_thread
.
word
rt_current_thread
#ifdef RT_USING_NEON
.
align
6
.
align
6
/*
is
the
neon
instuction
on
arm
mode
?
*/
.
neon_opcode
:
.
word
0xfe000000
@
mask
.
word
0xf2000000
@
opcode
.
word
0xfe000000
@
mask
.
word
0xf2000000
@
opcode
.
word
0xff100000
@
mask
.
word
0xf4000000
@
opcode
.
word
0xff100000
@
mask
.
word
0xf4000000
@
opcode
.
word
0x00000000
@
end
mask
.
word
0x00000000
@
end
opcode
.
word
0x00000000
@
end
mask
.
word
0x00000000
@
end
opcode
#endif
/*
undefined
instruction
exception
processing
*/
.
globl
undef_entry
undef_entry
:
PRINT1
"r0=0x%08x"
,
r0
PRINT1
"r2=0x%08x"
,
r2
PRINT1
"r9=0x%08x"
,
r9
PRINT1
"sp=0x%08x"
,
sp
PRINT1
"r0=0x%08x"
,
r0
PRINT1
"r2=0x%08x"
,
r2
PRINT1
"r9=0x%08x"
,
r9
PRINT1
"sp=0x%08x"
,
sp
#ifdef RT_USING_NEON
ldr
r6
,
.
neon_opcode
ldr
r6
,
.
neon_opcode
__check_neon_instruction
:
ldr
r7
,
[
r6
],
#
4
@
load
mask
value
cmp
r7
,
#
0
@
end
mask
?
beq
__check_vfp_instruction
and
r8
,
r0
,
r7
ldr
r7
,
[
r6
],
#
4
@
load
opcode
value
cmp
r8
,
r7
@
is
NEON
instruction
?
bne
__check_neon_instruction
b
vfp_entry
ldr
r7
,
[
r6
],
#
4
@
load
mask
value
cmp
r7
,
#
0
@
end
mask
?
beq
__check_vfp_instruction
and
r8
,
r0
,
r7
ldr
r7
,
[
r6
],
#
4
@
load
opcode
value
cmp
r8
,
r7
@
is
NEON
instruction
?
bne
__check_neon_instruction
b
vfp_entry
__check_vfp_instruction
:
#endif
tst
r0
,
#
0x08000000
@
only
CDP
/
CPRT
/
LDC
/
STC
instruction
has
bit
27
tstne
r0
,
#
0x04000000
@
bit
26
set
on
both
ARM
and
Thumb
-
2
instruction
moveq
pc
,
lr
@
no
vfp
coprocessor
instruction
,
return
get_current_thread
r10
and
r8
,
r0
,
#
0x00000f00
@
get
coprocessor
number
PRINT1
"CP=0x%08x"
,
r8
add
pc
,
pc
,
r8
,
lsr
#
6
nop
mov
pc
,
lr
@
CP0
mov
pc
,
lr
@
CP1
mov
pc
,
lr
@
CP2
mov
pc
,
lr
@
CP3
mov
pc
,
lr
@
CP4
mov
pc
,
lr
@
CP5
mov
pc
,
lr
@
CP6
mov
pc
,
lr
@
CP7
mov
pc
,
lr
@
CP8
mov
pc
,
lr
@
CP9
mov
pc
,
lr
@
CP10
VFP
mov
pc
,
lr
@
CP11
VFP
mov
pc
,
lr
@
CP12
mov
pc
,
lr
@
CP13
mov
pc
,
lr
@
CP14
DEBUG
mov
pc
,
lr
@
CP15
SYS
CONTROL
tst
r0
,
#
0x08000000
@
only
CDP
/
CPRT
/
LDC
/
STC
instruction
has
bit
27
tstne
r0
,
#
0x04000000
@
bit
26
set
on
both
ARM
and
Thumb
-
2
instruction
moveq
pc
,
lr
@
no
vfp
coprocessor
instruction
,
return
get_current_thread
r10
and
r8
,
r0
,
#
0x00000f00
@
get
coprocessor
number
PRINT1
"CP=0x%08x"
,
r8
add
pc
,
pc
,
r8
,
lsr
#
6
nop
mov
pc
,
lr
@
CP0
mov
pc
,
lr
@
CP1
mov
pc
,
lr
@
CP2
mov
pc
,
lr
@
CP3
mov
pc
,
lr
@
CP4
mov
pc
,
lr
@
CP5
mov
pc
,
lr
@
CP6
mov
pc
,
lr
@
CP7
mov
pc
,
lr
@
CP8
mov
pc
,
lr
@
CP9
mov
pc
,
lr
@
CP10
VFP
mov
pc
,
lr
@
CP11
VFP
mov
pc
,
lr
@
CP12
mov
pc
,
lr
@
CP13
mov
pc
,
lr
@
CP14
DEBUG
mov
pc
,
lr
@
CP15
SYS
CONTROL
libcpu/arm/common/divsi3.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
*
Change
Logs
:
*
Date
Author
Notes
*/
/*
$NetBSD
:
divsi3
.
S
,
v
1
.5
2005
/
02
/
26
22
:
58
:
56
perry
Exp
$
*/
/*
$NetBSD
:
divsi3
.
S
,
v
1
.5
2005
/
02
/
26
22
:
58
:
56
perry
Exp
$
*/
/*
*
THIS
SOFTWARE
IS
PROVIDED
BY
THE
AUTHOR
AND
CONTRIBUTORS
``
AS
IS
''
AND
...
...
@@ -26,376 +26,376 @@
*
stack
is
aligned
as
there
's a possibility of branching to L_overflow
*
which
makes
a
C
call
*/
.
text
.
align
0
.
globl
__umodsi3
.
type
__umodsi3
,
function
.
text
.
align
0
.
globl
__umodsi3
.
type
__umodsi3
,
function
__umodsi3
:
stmfd
sp
!,
{
lr
}
sub
sp
,
sp
,
#
4
/*
align
stack
*/
bl
.
L_udivide
add
sp
,
sp
,
#
4
/*
unalign
stack
*/
mov
r0
,
r1
ldmfd
sp
!,
{
pc
}
stmfd
sp
!,
{
lr
}
sub
sp
,
sp
,
#
4
/*
align
stack
*/
bl
.
L_udivide
add
sp
,
sp
,
#
4
/*
unalign
stack
*/
mov
r0
,
r1
ldmfd
sp
!,
{
pc
}
.
text
.
align
0
.
globl
__modsi3
.
type
__modsi3
,
function
.
text
.
align
0
.
globl
__modsi3
.
type
__modsi3
,
function
__modsi3
:
stmfd
sp
!,
{
lr
}
sub
sp
,
sp
,
#
4
/*
align
stack
*/
bl
.
L_divide
add
sp
,
sp
,
#
4
/*
unalign
stack
*/
mov
r0
,
r1
ldmfd
sp
!,
{
pc
}
stmfd
sp
!,
{
lr
}
sub
sp
,
sp
,
#
4
/*
align
stack
*/
bl
.
L_divide
add
sp
,
sp
,
#
4
/*
unalign
stack
*/
mov
r0
,
r1
ldmfd
sp
!,
{
pc
}
.
L_overflow
:
/
*
XXX
should
cause
a
fatal
error
*/
mvn
r0
,
#
0
mov
pc
,
lr
/
*
XXX
should
cause
a
fatal
error
*/
mvn
r0
,
#
0
mov
pc
,
lr
.
text
.
align
0
.
globl
__udivsi3
.
type
__udivsi3
,
function
.
text
.
align
0
.
globl
__udivsi3
.
type
__udivsi3
,
function
__udivsi3
:
.
L_udivide
:
/
*
r0
=
r0
/
r1
; r1 = r0 % r1 */
eor
r0
,
r1
,
r0
eor
r1
,
r0
,
r1
eor
r0
,
r1
,
r0
/
*
r0
=
r1
/
r0
; r1 = r1 % r0 */
cmp
r0
,
#
1
bcc
.
L_overflow
beq
.
L_divide_l0
mov
ip
,
#
0
movs
r1
,
r1
bpl
.
L_divide_l1
orr
ip
,
ip
,
#
0x20000000
/*
ip
bit
0x20000000
=
-
ve
r1
*/
movs
r1
,
r1
,
lsr
#
1
orrcs
ip
,
ip
,
#
0x10000000
/*
ip
bit
0x10000000
=
bit
0
of
r1
*/
b
.
L_divide_l1
.
L_udivide
:
/
*
r0
=
r0
/
r1
; r1 = r0 % r1 */
eor
r0
,
r1
,
r0
eor
r1
,
r0
,
r1
eor
r0
,
r1
,
r0
/
*
r0
=
r1
/
r0
; r1 = r1 % r0 */
cmp
r0
,
#
1
bcc
.
L_overflow
beq
.
L_divide_l0
mov
ip
,
#
0
movs
r1
,
r1
bpl
.
L_divide_l1
orr
ip
,
ip
,
#
0x20000000
/*
ip
bit
0x20000000
=
-
ve
r1
*/
movs
r1
,
r1
,
lsr
#
1
orrcs
ip
,
ip
,
#
0x10000000
/*
ip
bit
0x10000000
=
bit
0
of
r1
*/
b
.
L_divide_l1
.
L_divide_l0
:
/
*
r0
==
1
*/
mov
r0
,
r1
mov
r1
,
#
0
mov
pc
,
lr
.
L_divide_l0
:
/
*
r0
==
1
*/
mov
r0
,
r1
mov
r1
,
#
0
mov
pc
,
lr
.
text
.
align
0
.
globl
__divsi3
.
type
__divsi3
,
function
.
text
.
align
0
.
globl
__divsi3
.
type
__divsi3
,
function
__divsi3
:
.
L_divide
:
/
*
r0
=
r0
/
r1
; r1 = r0 % r1 */
eor
r0
,
r1
,
r0
eor
r1
,
r0
,
r1
eor
r0
,
r1
,
r0
/
*
r0
=
r1
/
r0
; r1 = r1 % r0 */
cmp
r0
,
#
1
bcc
.
L_overflow
beq
.
L_divide_l0
ands
ip
,
r0
,
#
0x80000000
rsbmi
r0
,
r0
,
#
0
ands
r2
,
r1
,
#
0x80000000
eor
ip
,
ip
,
r2
rsbmi
r1
,
r1
,
#
0
orr
ip
,
r2
,
ip
,
lsr
#
1
/*
ip
bit
0x40000000
=
-
ve
division
*/
/
*
ip
bit
0x80000000
=
-
ve
remainder
*/
.
L_divide
:
/
*
r0
=
r0
/
r1
; r1 = r0 % r1 */
eor
r0
,
r1
,
r0
eor
r1
,
r0
,
r1
eor
r0
,
r1
,
r0
/
*
r0
=
r1
/
r0
; r1 = r1 % r0 */
cmp
r0
,
#
1
bcc
.
L_overflow
beq
.
L_divide_l0
ands
ip
,
r0
,
#
0x80000000
rsbmi
r0
,
r0
,
#
0
ands
r2
,
r1
,
#
0x80000000
eor
ip
,
ip
,
r2
rsbmi
r1
,
r1
,
#
0
orr
ip
,
r2
,
ip
,
lsr
#
1
/*
ip
bit
0x40000000
=
-
ve
division
*/
/
*
ip
bit
0x80000000
=
-
ve
remainder
*/
.
L_divide_l1
:
mov
r2
,
#
1
mov
r3
,
#
0
mov
r2
,
#
1
mov
r3
,
#
0
/
*
*
If
the
highest
bit
of
the
dividend
is
set
,
we
have
to
be
*
careful
when
shifting
the
divisor
.
Test
this
.
*/
movs
r1
,
r1
bpl
.
L_old_code
/
*
*
If
the
highest
bit
of
the
dividend
is
set
,
we
have
to
be
*
careful
when
shifting
the
divisor
.
Test
this
.
*/
movs
r1
,
r1
bpl
.
L_old_code
/
*
*
At
this
point
,
the
highest
bit
of
r1
is
known
to
be
set
.
*
We
abuse
this
below
in
the
tst
instructions
.
*/
tst
r1
,
r0
/*,
lsl
#
0
*/
bmi
.
L_divide_b1
tst
r1
,
r0
,
lsl
#
1
bmi
.
L_divide_b2
tst
r1
,
r0
,
lsl
#
2
bmi
.
L_divide_b3
tst
r1
,
r0
,
lsl
#
3
bmi
.
L_divide_b4
tst
r1
,
r0
,
lsl
#
4
bmi
.
L_divide_b5
tst
r1
,
r0
,
lsl
#
5
bmi
.
L_divide_b6
tst
r1
,
r0
,
lsl
#
6
bmi
.
L_divide_b7
tst
r1
,
r0
,
lsl
#
7
bmi
.
L_divide_b8
tst
r1
,
r0
,
lsl
#
8
bmi
.
L_divide_b9
tst
r1
,
r0
,
lsl
#
9
bmi
.
L_divide_b10
tst
r1
,
r0
,
lsl
#
10
bmi
.
L_divide_b11
tst
r1
,
r0
,
lsl
#
11
bmi
.
L_divide_b12
tst
r1
,
r0
,
lsl
#
12
bmi
.
L_divide_b13
tst
r1
,
r0
,
lsl
#
13
bmi
.
L_divide_b14
tst
r1
,
r0
,
lsl
#
14
bmi
.
L_divide_b15
tst
r1
,
r0
,
lsl
#
15
bmi
.
L_divide_b16
tst
r1
,
r0
,
lsl
#
16
bmi
.
L_divide_b17
tst
r1
,
r0
,
lsl
#
17
bmi
.
L_divide_b18
tst
r1
,
r0
,
lsl
#
18
bmi
.
L_divide_b19
tst
r1
,
r0
,
lsl
#
19
bmi
.
L_divide_b20
tst
r1
,
r0
,
lsl
#
20
bmi
.
L_divide_b21
tst
r1
,
r0
,
lsl
#
21
bmi
.
L_divide_b22
tst
r1
,
r0
,
lsl
#
22
bmi
.
L_divide_b23
tst
r1
,
r0
,
lsl
#
23
bmi
.
L_divide_b24
tst
r1
,
r0
,
lsl
#
24
bmi
.
L_divide_b25
tst
r1
,
r0
,
lsl
#
25
bmi
.
L_divide_b26
tst
r1
,
r0
,
lsl
#
26
bmi
.
L_divide_b27
tst
r1
,
r0
,
lsl
#
27
bmi
.
L_divide_b28
tst
r1
,
r0
,
lsl
#
28
bmi
.
L_divide_b29
tst
r1
,
r0
,
lsl
#
29
bmi
.
L_divide_b30
tst
r1
,
r0
,
lsl
#
30
bmi
.
L_divide_b31
/
*
*
At
this
point
,
the
highest
bit
of
r1
is
known
to
be
set
.
*
We
abuse
this
below
in
the
tst
instructions
.
*/
tst
r1
,
r0
/*,
lsl
#
0
*/
bmi
.
L_divide_b1
tst
r1
,
r0
,
lsl
#
1
bmi
.
L_divide_b2
tst
r1
,
r0
,
lsl
#
2
bmi
.
L_divide_b3
tst
r1
,
r0
,
lsl
#
3
bmi
.
L_divide_b4
tst
r1
,
r0
,
lsl
#
4
bmi
.
L_divide_b5
tst
r1
,
r0
,
lsl
#
5
bmi
.
L_divide_b6
tst
r1
,
r0
,
lsl
#
6
bmi
.
L_divide_b7
tst
r1
,
r0
,
lsl
#
7
bmi
.
L_divide_b8
tst
r1
,
r0
,
lsl
#
8
bmi
.
L_divide_b9
tst
r1
,
r0
,
lsl
#
9
bmi
.
L_divide_b10
tst
r1
,
r0
,
lsl
#
10
bmi
.
L_divide_b11
tst
r1
,
r0
,
lsl
#
11
bmi
.
L_divide_b12
tst
r1
,
r0
,
lsl
#
12
bmi
.
L_divide_b13
tst
r1
,
r0
,
lsl
#
13
bmi
.
L_divide_b14
tst
r1
,
r0
,
lsl
#
14
bmi
.
L_divide_b15
tst
r1
,
r0
,
lsl
#
15
bmi
.
L_divide_b16
tst
r1
,
r0
,
lsl
#
16
bmi
.
L_divide_b17
tst
r1
,
r0
,
lsl
#
17
bmi
.
L_divide_b18
tst
r1
,
r0
,
lsl
#
18
bmi
.
L_divide_b19
tst
r1
,
r0
,
lsl
#
19
bmi
.
L_divide_b20
tst
r1
,
r0
,
lsl
#
20
bmi
.
L_divide_b21
tst
r1
,
r0
,
lsl
#
21
bmi
.
L_divide_b22
tst
r1
,
r0
,
lsl
#
22
bmi
.
L_divide_b23
tst
r1
,
r0
,
lsl
#
23
bmi
.
L_divide_b24
tst
r1
,
r0
,
lsl
#
24
bmi
.
L_divide_b25
tst
r1
,
r0
,
lsl
#
25
bmi
.
L_divide_b26
tst
r1
,
r0
,
lsl
#
26
bmi
.
L_divide_b27
tst
r1
,
r0
,
lsl
#
27
bmi
.
L_divide_b28
tst
r1
,
r0
,
lsl
#
28
bmi
.
L_divide_b29
tst
r1
,
r0
,
lsl
#
29
bmi
.
L_divide_b30
tst
r1
,
r0
,
lsl
#
30
bmi
.
L_divide_b31
/*
*
instead
of
:
*
tst
r1
,
r0
,
lsl
#
31
*
bmi
.
L_divide_b32
*
tst
r1
,
r0
,
lsl
#
31
*
bmi
.
L_divide_b32
*/
b
.
L_divide_b32
b
.
L_divide_b32
.
L_old_code
:
cmp
r1
,
r0
bcc
.
L_divide_b0
cmp
r1
,
r0
,
lsl
#
1
bcc
.
L_divide_b1
cmp
r1
,
r0
,
lsl
#
2
bcc
.
L_divide_b2
cmp
r1
,
r0
,
lsl
#
3
bcc
.
L_divide_b3
cmp
r1
,
r0
,
lsl
#
4
bcc
.
L_divide_b4
cmp
r1
,
r0
,
lsl
#
5
bcc
.
L_divide_b5
cmp
r1
,
r0
,
lsl
#
6
bcc
.
L_divide_b6
cmp
r1
,
r0
,
lsl
#
7
bcc
.
L_divide_b7
cmp
r1
,
r0
,
lsl
#
8
bcc
.
L_divide_b8
cmp
r1
,
r0
,
lsl
#
9
bcc
.
L_divide_b9
cmp
r1
,
r0
,
lsl
#
10
bcc
.
L_divide_b10
cmp
r1
,
r0
,
lsl
#
11
bcc
.
L_divide_b11
cmp
r1
,
r0
,
lsl
#
12
bcc
.
L_divide_b12
cmp
r1
,
r0
,
lsl
#
13
bcc
.
L_divide_b13
cmp
r1
,
r0
,
lsl
#
14
bcc
.
L_divide_b14
cmp
r1
,
r0
,
lsl
#
15
bcc
.
L_divide_b15
cmp
r1
,
r0
,
lsl
#
16
bcc
.
L_divide_b16
cmp
r1
,
r0
,
lsl
#
17
bcc
.
L_divide_b17
cmp
r1
,
r0
,
lsl
#
18
bcc
.
L_divide_b18
cmp
r1
,
r0
,
lsl
#
19
bcc
.
L_divide_b19
cmp
r1
,
r0
,
lsl
#
20
bcc
.
L_divide_b20
cmp
r1
,
r0
,
lsl
#
21
bcc
.
L_divide_b21
cmp
r1
,
r0
,
lsl
#
22
bcc
.
L_divide_b22
cmp
r1
,
r0
,
lsl
#
23
bcc
.
L_divide_b23
cmp
r1
,
r0
,
lsl
#
24
bcc
.
L_divide_b24
cmp
r1
,
r0
,
lsl
#
25
bcc
.
L_divide_b25
cmp
r1
,
r0
,
lsl
#
26
bcc
.
L_divide_b26
cmp
r1
,
r0
,
lsl
#
27
bcc
.
L_divide_b27
cmp
r1
,
r0
,
lsl
#
28
bcc
.
L_divide_b28
cmp
r1
,
r0
,
lsl
#
29
bcc
.
L_divide_b29
cmp
r1
,
r0
,
lsl
#
30
bcc
.
L_divide_b30
cmp
r1
,
r0
bcc
.
L_divide_b0
cmp
r1
,
r0
,
lsl
#
1
bcc
.
L_divide_b1
cmp
r1
,
r0
,
lsl
#
2
bcc
.
L_divide_b2
cmp
r1
,
r0
,
lsl
#
3
bcc
.
L_divide_b3
cmp
r1
,
r0
,
lsl
#
4
bcc
.
L_divide_b4
cmp
r1
,
r0
,
lsl
#
5
bcc
.
L_divide_b5
cmp
r1
,
r0
,
lsl
#
6
bcc
.
L_divide_b6
cmp
r1
,
r0
,
lsl
#
7
bcc
.
L_divide_b7
cmp
r1
,
r0
,
lsl
#
8
bcc
.
L_divide_b8
cmp
r1
,
r0
,
lsl
#
9
bcc
.
L_divide_b9
cmp
r1
,
r0
,
lsl
#
10
bcc
.
L_divide_b10
cmp
r1
,
r0
,
lsl
#
11
bcc
.
L_divide_b11
cmp
r1
,
r0
,
lsl
#
12
bcc
.
L_divide_b12
cmp
r1
,
r0
,
lsl
#
13
bcc
.
L_divide_b13
cmp
r1
,
r0
,
lsl
#
14
bcc
.
L_divide_b14
cmp
r1
,
r0
,
lsl
#
15
bcc
.
L_divide_b15
cmp
r1
,
r0
,
lsl
#
16
bcc
.
L_divide_b16
cmp
r1
,
r0
,
lsl
#
17
bcc
.
L_divide_b17
cmp
r1
,
r0
,
lsl
#
18
bcc
.
L_divide_b18
cmp
r1
,
r0
,
lsl
#
19
bcc
.
L_divide_b19
cmp
r1
,
r0
,
lsl
#
20
bcc
.
L_divide_b20
cmp
r1
,
r0
,
lsl
#
21
bcc
.
L_divide_b21
cmp
r1
,
r0
,
lsl
#
22
bcc
.
L_divide_b22
cmp
r1
,
r0
,
lsl
#
23
bcc
.
L_divide_b23
cmp
r1
,
r0
,
lsl
#
24
bcc
.
L_divide_b24
cmp
r1
,
r0
,
lsl
#
25
bcc
.
L_divide_b25
cmp
r1
,
r0
,
lsl
#
26
bcc
.
L_divide_b26
cmp
r1
,
r0
,
lsl
#
27
bcc
.
L_divide_b27
cmp
r1
,
r0
,
lsl
#
28
bcc
.
L_divide_b28
cmp
r1
,
r0
,
lsl
#
29
bcc
.
L_divide_b29
cmp
r1
,
r0
,
lsl
#
30
bcc
.
L_divide_b30
.
L_divide_b32
:
cmp
r1
,
r0
,
lsl
#
31
subhs
r1
,
r1
,
r0
,
lsl
#
31
addhs
r3
,
r3
,
r2
,
lsl
#
31
cmp
r1
,
r0
,
lsl
#
31
subhs
r1
,
r1
,
r0
,
lsl
#
31
addhs
r3
,
r3
,
r2
,
lsl
#
31
.
L_divide_b31
:
cmp
r1
,
r0
,
lsl
#
30
subhs
r1
,
r1
,
r0
,
lsl
#
30
addhs
r3
,
r3
,
r2
,
lsl
#
30
cmp
r1
,
r0
,
lsl
#
30
subhs
r1
,
r1
,
r0
,
lsl
#
30
addhs
r3
,
r3
,
r2
,
lsl
#
30
.
L_divide_b30
:
cmp
r1
,
r0
,
lsl
#
29
subhs
r1
,
r1
,
r0
,
lsl
#
29
addhs
r3
,
r3
,
r2
,
lsl
#
29
cmp
r1
,
r0
,
lsl
#
29
subhs
r1
,
r1
,
r0
,
lsl
#
29
addhs
r3
,
r3
,
r2
,
lsl
#
29
.
L_divide_b29
:
cmp
r1
,
r0
,
lsl
#
28
subhs
r1
,
r1
,
r0
,
lsl
#
28
addhs
r3
,
r3
,
r2
,
lsl
#
28
cmp
r1
,
r0
,
lsl
#
28
subhs
r1
,
r1
,
r0
,
lsl
#
28
addhs
r3
,
r3
,
r2
,
lsl
#
28
.
L_divide_b28
:
cmp
r1
,
r0
,
lsl
#
27
subhs
r1
,
r1
,
r0
,
lsl
#
27
addhs
r3
,
r3
,
r2
,
lsl
#
27
cmp
r1
,
r0
,
lsl
#
27
subhs
r1
,
r1
,
r0
,
lsl
#
27
addhs
r3
,
r3
,
r2
,
lsl
#
27
.
L_divide_b27
:
cmp
r1
,
r0
,
lsl
#
26
subhs
r1
,
r1
,
r0
,
lsl
#
26
addhs
r3
,
r3
,
r2
,
lsl
#
26
cmp
r1
,
r0
,
lsl
#
26
subhs
r1
,
r1
,
r0
,
lsl
#
26
addhs
r3
,
r3
,
r2
,
lsl
#
26
.
L_divide_b26
:
cmp
r1
,
r0
,
lsl
#
25
subhs
r1
,
r1
,
r0
,
lsl
#
25
addhs
r3
,
r3
,
r2
,
lsl
#
25
cmp
r1
,
r0
,
lsl
#
25
subhs
r1
,
r1
,
r0
,
lsl
#
25
addhs
r3
,
r3
,
r2
,
lsl
#
25
.
L_divide_b25
:
cmp
r1
,
r0
,
lsl
#
24
subhs
r1
,
r1
,
r0
,
lsl
#
24
addhs
r3
,
r3
,
r2
,
lsl
#
24
cmp
r1
,
r0
,
lsl
#
24
subhs
r1
,
r1
,
r0
,
lsl
#
24
addhs
r3
,
r3
,
r2
,
lsl
#
24
.
L_divide_b24
:
cmp
r1
,
r0
,
lsl
#
23
subhs
r1
,
r1
,
r0
,
lsl
#
23
addhs
r3
,
r3
,
r2
,
lsl
#
23
cmp
r1
,
r0
,
lsl
#
23
subhs
r1
,
r1
,
r0
,
lsl
#
23
addhs
r3
,
r3
,
r2
,
lsl
#
23
.
L_divide_b23
:
cmp
r1
,
r0
,
lsl
#
22
subhs
r1
,
r1
,
r0
,
lsl
#
22
addhs
r3
,
r3
,
r2
,
lsl
#
22
cmp
r1
,
r0
,
lsl
#
22
subhs
r1
,
r1
,
r0
,
lsl
#
22
addhs
r3
,
r3
,
r2
,
lsl
#
22
.
L_divide_b22
:
cmp
r1
,
r0
,
lsl
#
21
subhs
r1
,
r1
,
r0
,
lsl
#
21
addhs
r3
,
r3
,
r2
,
lsl
#
21
cmp
r1
,
r0
,
lsl
#
21
subhs
r1
,
r1
,
r0
,
lsl
#
21
addhs
r3
,
r3
,
r2
,
lsl
#
21
.
L_divide_b21
:
cmp
r1
,
r0
,
lsl
#
20
subhs
r1
,
r1
,
r0
,
lsl
#
20
addhs
r3
,
r3
,
r2
,
lsl
#
20
cmp
r1
,
r0
,
lsl
#
20
subhs
r1
,
r1
,
r0
,
lsl
#
20
addhs
r3
,
r3
,
r2
,
lsl
#
20
.
L_divide_b20
:
cmp
r1
,
r0
,
lsl
#
19
subhs
r1
,
r1
,
r0
,
lsl
#
19
addhs
r3
,
r3
,
r2
,
lsl
#
19
cmp
r1
,
r0
,
lsl
#
19
subhs
r1
,
r1
,
r0
,
lsl
#
19
addhs
r3
,
r3
,
r2
,
lsl
#
19
.
L_divide_b19
:
cmp
r1
,
r0
,
lsl
#
18
subhs
r1
,
r1
,
r0
,
lsl
#
18
addhs
r3
,
r3
,
r2
,
lsl
#
18
cmp
r1
,
r0
,
lsl
#
18
subhs
r1
,
r1
,
r0
,
lsl
#
18
addhs
r3
,
r3
,
r2
,
lsl
#
18
.
L_divide_b18
:
cmp
r1
,
r0
,
lsl
#
17
subhs
r1
,
r1
,
r0
,
lsl
#
17
addhs
r3
,
r3
,
r2
,
lsl
#
17
cmp
r1
,
r0
,
lsl
#
17
subhs
r1
,
r1
,
r0
,
lsl
#
17
addhs
r3
,
r3
,
r2
,
lsl
#
17
.
L_divide_b17
:
cmp
r1
,
r0
,
lsl
#
16
subhs
r1
,
r1
,
r0
,
lsl
#
16
addhs
r3
,
r3
,
r2
,
lsl
#
16
cmp
r1
,
r0
,
lsl
#
16
subhs
r1
,
r1
,
r0
,
lsl
#
16
addhs
r3
,
r3
,
r2
,
lsl
#
16
.
L_divide_b16
:
cmp
r1
,
r0
,
lsl
#
15
subhs
r1
,
r1
,
r0
,
lsl
#
15
addhs
r3
,
r3
,
r2
,
lsl
#
15
cmp
r1
,
r0
,
lsl
#
15
subhs
r1
,
r1
,
r0
,
lsl
#
15
addhs
r3
,
r3
,
r2
,
lsl
#
15
.
L_divide_b15
:
cmp
r1
,
r0
,
lsl
#
14
subhs
r1
,
r1
,
r0
,
lsl
#
14
addhs
r3
,
r3
,
r2
,
lsl
#
14
cmp
r1
,
r0
,
lsl
#
14
subhs
r1
,
r1
,
r0
,
lsl
#
14
addhs
r3
,
r3
,
r2
,
lsl
#
14
.
L_divide_b14
:
cmp
r1
,
r0
,
lsl
#
13
subhs
r1
,
r1
,
r0
,
lsl
#
13
addhs
r3
,
r3
,
r2
,
lsl
#
13
cmp
r1
,
r0
,
lsl
#
13
subhs
r1
,
r1
,
r0
,
lsl
#
13
addhs
r3
,
r3
,
r2
,
lsl
#
13
.
L_divide_b13
:
cmp
r1
,
r0
,
lsl
#
12
subhs
r1
,
r1
,
r0
,
lsl
#
12
addhs
r3
,
r3
,
r2
,
lsl
#
12
cmp
r1
,
r0
,
lsl
#
12
subhs
r1
,
r1
,
r0
,
lsl
#
12
addhs
r3
,
r3
,
r2
,
lsl
#
12
.
L_divide_b12
:
cmp
r1
,
r0
,
lsl
#
11
subhs
r1
,
r1
,
r0
,
lsl
#
11
addhs
r3
,
r3
,
r2
,
lsl
#
11
cmp
r1
,
r0
,
lsl
#
11
subhs
r1
,
r1
,
r0
,
lsl
#
11
addhs
r3
,
r3
,
r2
,
lsl
#
11
.
L_divide_b11
:
cmp
r1
,
r0
,
lsl
#
10
subhs
r1
,
r1
,
r0
,
lsl
#
10
addhs
r3
,
r3
,
r2
,
lsl
#
10
cmp
r1
,
r0
,
lsl
#
10
subhs
r1
,
r1
,
r0
,
lsl
#
10
addhs
r3
,
r3
,
r2
,
lsl
#
10
.
L_divide_b10
:
cmp
r1
,
r0
,
lsl
#
9
subhs
r1
,
r1
,
r0
,
lsl
#
9
addhs
r3
,
r3
,
r2
,
lsl
#
9
cmp
r1
,
r0
,
lsl
#
9
subhs
r1
,
r1
,
r0
,
lsl
#
9
addhs
r3
,
r3
,
r2
,
lsl
#
9
.
L_divide_b9
:
cmp
r1
,
r0
,
lsl
#
8
subhs
r1
,
r1
,
r0
,
lsl
#
8
addhs
r3
,
r3
,
r2
,
lsl
#
8
cmp
r1
,
r0
,
lsl
#
8
subhs
r1
,
r1
,
r0
,
lsl
#
8
addhs
r3
,
r3
,
r2
,
lsl
#
8
.
L_divide_b8
:
cmp
r1
,
r0
,
lsl
#
7
subhs
r1
,
r1
,
r0
,
lsl
#
7
addhs
r3
,
r3
,
r2
,
lsl
#
7
cmp
r1
,
r0
,
lsl
#
7
subhs
r1
,
r1
,
r0
,
lsl
#
7
addhs
r3
,
r3
,
r2
,
lsl
#
7
.
L_divide_b7
:
cmp
r1
,
r0
,
lsl
#
6
subhs
r1
,
r1
,
r0
,
lsl
#
6
addhs
r3
,
r3
,
r2
,
lsl
#
6
cmp
r1
,
r0
,
lsl
#
6
subhs
r1
,
r1
,
r0
,
lsl
#
6
addhs
r3
,
r3
,
r2
,
lsl
#
6
.
L_divide_b6
:
cmp
r1
,
r0
,
lsl
#
5
subhs
r1
,
r1
,
r0
,
lsl
#
5
addhs
r3
,
r3
,
r2
,
lsl
#
5
cmp
r1
,
r0
,
lsl
#
5
subhs
r1
,
r1
,
r0
,
lsl
#
5
addhs
r3
,
r3
,
r2
,
lsl
#
5
.
L_divide_b5
:
cmp
r1
,
r0
,
lsl
#
4
subhs
r1
,
r1
,
r0
,
lsl
#
4
addhs
r3
,
r3
,
r2
,
lsl
#
4
cmp
r1
,
r0
,
lsl
#
4
subhs
r1
,
r1
,
r0
,
lsl
#
4
addhs
r3
,
r3
,
r2
,
lsl
#
4
.
L_divide_b4
:
cmp
r1
,
r0
,
lsl
#
3
subhs
r1
,
r1
,
r0
,
lsl
#
3
addhs
r3
,
r3
,
r2
,
lsl
#
3
cmp
r1
,
r0
,
lsl
#
3
subhs
r1
,
r1
,
r0
,
lsl
#
3
addhs
r3
,
r3
,
r2
,
lsl
#
3
.
L_divide_b3
:
cmp
r1
,
r0
,
lsl
#
2
subhs
r1
,
r1
,
r0
,
lsl
#
2
addhs
r3
,
r3
,
r2
,
lsl
#
2
cmp
r1
,
r0
,
lsl
#
2
subhs
r1
,
r1
,
r0
,
lsl
#
2
addhs
r3
,
r3
,
r2
,
lsl
#
2
.
L_divide_b2
:
cmp
r1
,
r0
,
lsl
#
1
subhs
r1
,
r1
,
r0
,
lsl
#
1
addhs
r3
,
r3
,
r2
,
lsl
#
1
cmp
r1
,
r0
,
lsl
#
1
subhs
r1
,
r1
,
r0
,
lsl
#
1
addhs
r3
,
r3
,
r2
,
lsl
#
1
.
L_divide_b1
:
cmp
r1
,
r0
subhs
r1
,
r1
,
r0
addhs
r3
,
r3
,
r2
cmp
r1
,
r0
subhs
r1
,
r1
,
r0
addhs
r3
,
r3
,
r2
.
L_divide_b0
:
tst
ip
,
#
0x20000000
bne
.
L_udivide_l1
mov
r0
,
r3
cmp
ip
,
#
0
rsbmi
r1
,
r1
,
#
0
movs
ip
,
ip
,
lsl
#
1
bicmi
r0
,
r0
,
#
0x80000000
/*
Fix
incase
we
divided
0x80000000
*/
rsbmi
r0
,
r0
,
#
0
mov
pc
,
lr
tst
ip
,
#
0x20000000
bne
.
L_udivide_l1
mov
r0
,
r3
cmp
ip
,
#
0
rsbmi
r1
,
r1
,
#
0
movs
ip
,
ip
,
lsl
#
1
bicmi
r0
,
r0
,
#
0x80000000
/*
Fix
incase
we
divided
0x80000000
*/
rsbmi
r0
,
r0
,
#
0
mov
pc
,
lr
.
L_udivide_l1
:
tst
ip
,
#
0x10000000
mov
r1
,
r1
,
lsl
#
1
orrne
r1
,
r1
,
#
1
mov
r3
,
r3
,
lsl
#
1
cmp
r1
,
r0
subhs
r1
,
r1
,
r0
addhs
r3
,
r3
,
r2
mov
r0
,
r3
mov
pc
,
lr
tst
ip
,
#
0x10000000
mov
r1
,
r1
,
lsl
#
1
orrne
r1
,
r1
,
#
1
mov
r3
,
r3
,
lsl
#
1
cmp
r1
,
r0
subhs
r1
,
r1
,
r0
addhs
r3
,
r3
,
r2
mov
r0
,
r3
mov
pc
,
lr
libcpu/arm/cortex-a/start_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
libcpu/arm/cortex-m0/context_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -12,18 +12,18 @@
*
2013
-
06
-
18
aozima
add
restore
MSP
feature
.
*
2013
-
11
-
04
bright
fixed
hardfault
bug
for
gcc
.
*/
.
cpu
cortex
-
m0
.
fpu
softvfp
.
syntax
unified
.
thumb
.
text
.
equ
SCB_VTOR
,
0xE000ED08
/*
Vector
Table
Offset
Register
*/
.
equ
NVIC_INT_CTRL
,
0xE000ED04
/*
interrupt
control
state
register
*/
.
equ
NVIC_SHPR3
,
0xE000ED20
/*
system
priority
register
(
3
)
*/
.
equ
NVIC_PENDSV_PRI
,
0xFFFF0000
/*
PendSV
and
SysTick
priority
value
(
lowest
)
*/
.
equ
NVIC_PENDSVSET
,
0x10000000
/*
value
to
trigger
PendSV
exception
*/
.
equ
SCB_VTOR
,
0xE000ED08
/*
Vector
Table
Offset
Register
*/
.
equ
NVIC_INT_CTRL
,
0xE000ED04
/*
interrupt
control
state
register
*/
.
equ
NVIC_SHPR3
,
0xE000ED20
/*
system
priority
register
(
3
)
*/
.
equ
NVIC_PENDSV_PRI
,
0xFFFF0000
/*
PendSV
and
SysTick
priority
value
(
lowest
)
*/
.
equ
NVIC_PENDSVSET
,
0x10000000
/*
value
to
trigger
PendSV
exception
*/
/*
*
rt_base_t
rt_hw_interrupt_disable
()
;
...
...
@@ -90,7 +90,7 @@ PendSV_Handler:
LDR
R0
,
=
rt_thread_switch_interrupt_flag
LDR
R1
,
[
R0
]
CMP
R1
,
#
0x00
BEQ
pendsv_exit
/*
pendsv
aLReady
handled
*/
BEQ
pendsv_exit
/*
pendsv
aLReady
handled
*/
/
*
clear
rt_thread_switch_interrupt_flag
to
0
*/
MOVS
R1
,
#
0
...
...
@@ -101,7 +101,7 @@ PendSV_Handler:
CMP
R1
,
#
0x00
BEQ
switch_to_thread
/*
skip
register
save
at
the
first
time
*/
MRS
R1
,
PSP
/*
get
from
thread
stack
pointer
*/
MRS
R1
,
PSP
/*
get
from
thread
stack
pointer
*/
SUBS
R1
,
R1
,
#
0x20
/*
space
for
{
R4
-
R7
}
and
{
R8
-
R11
}
*/
LDR
R0
,
[
R0
]
...
...
@@ -119,7 +119,7 @@ switch_to_thread:
LDR
R1
,
[
R1
]
LDR
R1
,
[
R1
]
/*
load
thread
stack
pointer
*/
LDMIA
R1
!,
{
R4
-
R7
}
/*
pop
thread
{
R4
-
R7
}
register
from
thread
stack
*/
LDMIA
R1
!,
{
R4
-
R7
}
/*
pop
thread
{
R4
-
R7
}
register
from
thread
stack
*/
PUSH
{
R4
-
R7
}
/*
push
{
R4
-
R7
}
to
MSP
for
copy
{
R8
-
R11
}
*/
LDMIA
R1
!,
{
R4
-
R7
}
/*
pop
thread
{
R8
-
R11
}
high
register
from
thread
stack
to
{
R4
-
R7
}
*/
...
...
libcpu/arm/cortex-m0/context_rvds.S
浏览文件 @
563e4989
;/*
; * Copyright (c) 2006-20
18
, RT-Thread Development Team
; * Copyright (c) 2006-20
22
, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
...
...
@@ -46,8 +46,8 @@ rt_hw_interrupt_disable PROC
; */
rt_hw_interrupt_enable
PROC
EXPORT
rt_hw_interrupt_enable
MSR
PRIMASK
,
r0
BX
LR
MSR
PRIMASK
,
r0
BX
LR
ENDP
;/*
...
...
libcpu/arm/cortex-m23/context_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
19
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -13,18 +13,18 @@
*
2013
-
11
-
04
bright
fixed
hardfault
bug
for
gcc
.
*
2019
-
03
-
31
xuzhuoyi
port
to
Cortex
-
M23
.
*/
.
cpu
cortex
-
m23
.
fpu
softvfp
.
syntax
unified
.
thumb
.
text
.
equ
SCB_VTOR
,
0xE000ED08
/*
Vector
Table
Offset
Register
*/
.
equ
NVIC_INT_CTRL
,
0xE000ED04
/*
interrupt
control
state
register
*/
.
equ
NVIC_SHPR3
,
0xE000ED20
/*
system
priority
register
(
3
)
*/
.
equ
NVIC_PENDSV_PRI
,
0xFFFF0000
/*
PendSV
and
SysTick
priority
value
(
lowest
)
*/
.
equ
NVIC_PENDSVSET
,
0x10000000
/*
value
to
trigger
PendSV
exception
*/
.
equ
SCB_VTOR
,
0xE000ED08
/*
Vector
Table
Offset
Register
*/
.
equ
NVIC_INT_CTRL
,
0xE000ED04
/*
interrupt
control
state
register
*/
.
equ
NVIC_SHPR3
,
0xE000ED20
/*
system
priority
register
(
3
)
*/
.
equ
NVIC_PENDSV_PRI
,
0xFFFF0000
/*
PendSV
and
SysTick
priority
value
(
lowest
)
*/
.
equ
NVIC_PENDSVSET
,
0x10000000
/*
value
to
trigger
PendSV
exception
*/
/*
*
rt_base_t
rt_hw_interrupt_disable
()
;
...
...
@@ -91,7 +91,7 @@ PendSV_Handler:
LDR
R0
,
=
rt_thread_switch_interrupt_flag
LDR
R1
,
[
R0
]
CMP
R1
,
#
0x00
BEQ
pendsv_exit
/*
pendsv
aLReady
handled
*/
BEQ
pendsv_exit
/*
pendsv
aLReady
handled
*/
/
*
clear
rt_thread_switch_interrupt_flag
to
0
*/
MOVS
R1
,
#
0
...
...
@@ -102,7 +102,7 @@ PendSV_Handler:
CMP
R1
,
#
0x00
BEQ
switch_to_thread
/*
skip
register
save
at
the
first
time
*/
MRS
R1
,
PSP
/*
get
from
thread
stack
pointer
*/
MRS
R1
,
PSP
/*
get
from
thread
stack
pointer
*/
SUBS
R1
,
R1
,
#
0x20
/*
space
for
{
R4
-
R7
}
and
{
R8
-
R11
}
*/
LDR
R0
,
[
R0
]
...
...
@@ -120,7 +120,7 @@ switch_to_thread:
LDR
R1
,
[
R1
]
LDR
R1
,
[
R1
]
/*
load
thread
stack
pointer
*/
LDMIA
R1
!,
{
R4
-
R7
}
/*
pop
thread
{
R4
-
R7
}
register
from
thread
stack
*/
LDMIA
R1
!,
{
R4
-
R7
}
/*
pop
thread
{
R4
-
R7
}
register
from
thread
stack
*/
PUSH
{
R4
-
R7
}
/*
push
{
R4
-
R7
}
to
MSP
for
copy
{
R8
-
R11
}
*/
LDMIA
R1
!,
{
R4
-
R7
}
/*
pop
thread
{
R8
-
R11
}
high
register
from
thread
stack
to
{
R4
-
R7
}
*/
...
...
libcpu/arm/cortex-m23/context_rvds.S
浏览文件 @
563e4989
;/*
; * Copyright (c) 2006-20
19
, RT-Thread Development Team
; * Copyright (c) 2006-20
22
, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
...
...
@@ -47,8 +47,8 @@ rt_hw_interrupt_disable PROC
; */
rt_hw_interrupt_enable
PROC
EXPORT
rt_hw_interrupt_enable
MSR
PRIMASK
,
r0
BX
LR
MSR
PRIMASK
,
r0
BX
LR
ENDP
;/*
...
...
libcpu/arm/cortex-m3/context_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -12,7 +12,7 @@
*
2013
-
06
-
18
aozima
add
restore
MSP
feature
.
*
2013
-
07
-
09
aozima
enhancement
hard
fault
exception
handler
.
*/
.
cpu
cortex
-
m3
.
fpu
softvfp
.
syntax
unified
...
...
@@ -22,7 +22,7 @@
.
equ
SCB_VTOR
,
0xE000ED08
/*
Vector
Table
Offset
Register
*/
.
equ
ICSR
,
0xE000ED04
/*
interrupt
control
state
register
*/
.
equ
PENDSVSET_BIT
,
0x10000000
/*
value
to
trigger
PendSV
exception
*/
.
equ
SHPR3
,
0xE000ED20
/*
system
priority
register
(
3
)
*/
.
equ
PENDSV_PRI_LOWEST
,
0xFFFF0000
/*
PendSV
and
SysTick
priority
value
(
lowest
)
*/
...
...
libcpu/arm/cortex-m3/context_rvds.S
浏览文件 @
563e4989
;/*
; * Copyright (c) 2006-20
18
, RT-Thread Development Team
; * Copyright (c) 2006-20
22
, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
...
...
libcpu/arm/cortex-m33/context_iar.S
浏览文件 @
563e4989
...
...
@@ -272,7 +272,7 @@ HardFault_Handler:
get_sp_done
STMFD
r0
!,
{
r4
-
r11
}
; push r4 - r11 register
LDR
r2
,
=
rt_trustzone_current_context
; r2 = &rt_secure_current_context
LDR
r2
,
[
r2
]
; r2 = *r2
MOV
r3
,
lr
; r3 = lr
...
...
libcpu/arm/cortex-m33/syscall_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -19,7 +19,7 @@
.
global
tzcall
.
type
tzcall
,
%
function
tzcall
:
SVC
1
/*
call
SVC
1
*/
SVC
1
/*
call
SVC
1
*/
BX
LR
tzcall_entry
:
...
...
libcpu/arm/cortex-m33/syscall_iar.S
浏览文件 @
563e4989
;/*
; * Copyright (c) 2006-20
18
, RT-Thread Development Team
; * Copyright (c) 2006-20
22
, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
...
...
@@ -23,7 +23,7 @@
.
global
tzcall
.
type
tzcall
,
%
function
tzcall
:
SVC
1
;/* call SVC 1 */
SVC
1
;/* call SVC 1 */
BX
LR
tzcall_entry
:
...
...
libcpu/arm/cortex-m33/syscall_rvds.S
浏览文件 @
563e4989
;/*
; * Copyright (c) 2006-20
18
, RT-Thread Development Team
; * Copyright (c) 2006-20
22
, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
...
...
@@ -20,7 +20,7 @@
; */
tzcall
PROC
EXPORT
tzcall
SVC
1
;call SVC 1
SVC
1
;call SVC 1
BX
LR
ENDP
...
...
@@ -28,7 +28,7 @@ tzcall PROC
tzcall_entry
PROC
PUSH
{
R1
,
R4
,
LR
}
MOV
R4
,
R1
; copy thread SP to R4
LDMFD
R4
!,
{
r0
-
r3
}
; pop user stack, get input arg0, arg1, arg2
LDMFD
R4
!,
{
r0
-
r3
}
; pop user stack, get input arg0, arg1, arg2
STMFD
R4
!,
{
r0
-
r3
}
; push stack, user stack recovery
BL
rt_secure_svc_handle
; call fun
POP
{
R1
,
R4
,
LR
}
...
...
@@ -71,4 +71,4 @@ get_sp_done
ALIGN
END
\ No newline at end of file
END
libcpu/arm/cortex-m4/context_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -104,13 +104,13 @@ PendSV_Handler:
CBZ
r1
,
switch_to_thread
/*
skip
register
save
at
the
first
time
*/
MRS
r1
,
psp
/*
get
from
thread
stack
pointer
*/
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
TST
lr
,
#
0x10
/*
if
(!
EXC_RETURN
[
4
])
*/
IT
EQ
VSTMDBEQ
r1
!,
{
d8
-
d15
}
/*
push
FPU
register
s16
~
s31
*/
#endif
STMFD
r1
!,
{
r4
-
r11
}
/*
push
r4
-
r11
register
*/
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
...
...
libcpu/arm/cortex-m7/context_gcc.S
浏览文件 @
563e4989
...
...
@@ -104,13 +104,13 @@ PendSV_Handler:
CBZ
r1
,
switch_to_thread
/*
skip
register
save
at
the
first
time
*/
MRS
r1
,
psp
/*
get
from
thread
stack
pointer
*/
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
TST
lr
,
#
0x10
/*
if
(!
EXC_RETURN
[
4
])
*/
IT
EQ
VSTMDBEQ
r1
!,
{
d8
-
d15
}
/*
push
FPU
register
s16
~
s31
*/
#endif
STMFD
r1
!,
{
r4
-
r11
}
/*
push
r4
-
r11
register
*/
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
...
...
libcpu/arm/cortex-r4/context_ccs.asm
浏览文件 @
563e4989
;/*
; * Copyright (c) 2006-20
18
, RT-Thread Development Team
; * Copyright (c) 2006-20
22
, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
...
...
@@ -59,17 +59,17 @@ rt_hw_context_switch
STMDB
sp
!
,
{
r4
}
; push cpsr
.if
(
__TI_VFP_SUPPORT__
)
VMRS
r4
,
fpexc
VMRS
r4
,
fpexc
TST
r4
,
#
0x40000000
BEQ
__no_vfp_frame1
VSTMDB
sp
!
,
{
d0
-
d15
}
VSTMDB
sp
!
,
{
d0
-
d15
}
VMRS
r5
,
fpscr
; TODO: add support for Common VFPv3.
; Save registers like FPINST, FPINST2
STMDB
sp
!
,
{
r5
}
__no_vfp_frame1
STMDB
sp
!
,
{
r4
}
.endif
.endif
STR
sp
,
[
r0
]
; store sp in preempted tasks TCB
LDR
sp
,
[
r1
]
; get new task stack pointer
...
...
@@ -81,7 +81,7 @@ __no_vfp_frame1
BEQ
__no_vfp_frame2
LDMIA
sp
!
,
{
r1
}
; get fpscr
VMSR
fpscr
,
r1
VLDMIA
sp
!
,
{
d0
-
d15
}
VLDMIA
sp
!
,
{
d0
-
d15
}
__no_vfp_frame2
.endif
...
...
@@ -107,7 +107,7 @@ rt_hw_context_switch_to
BEQ
__no_vfp_frame_to
LDMIA
sp
!
,
{
r1
}
; get fpscr
VMSR
fpscr
,
r1
VLDMIA
sp
!
,
{
d0
-
d15
}
VLDMIA
sp
!
,
{
d0
-
d15
}
__no_vfp_frame_to
.endif
...
...
@@ -143,17 +143,17 @@ IRQ_Handler
STMDB
sp
!
,
{
r0
-
r12
,
lr
}
.if
(
__TI_VFP_SUPPORT__
)
VMRS
r0
,
fpexc
VMRS
r0
,
fpexc
TST
r0
,
#
0x40000000
BEQ
__no_vfp_frame_str_irq
VSTMDB
sp
!
,
{
d0
-
d15
}
VSTMDB
sp
!
,
{
d0
-
d15
}
VMRS
r1
,
fpscr
; TODO: add support for Common VFPv3.
; Save registers like FPINST, FPINST2
STMDB
sp
!
,
{
r1
}
__no_vfp_frame_str_irq
STMDB
sp
!
,
{
r0
}
.endif
.endif
BL
rt_interrupt_enter
BL
rt_hw_trap_irq
...
...
@@ -173,7 +173,7 @@ __no_vfp_frame_str_irq
BEQ
__no_vfp_frame_ldr_irq
LDMIA
sp
!
,
{
r1
}
; get fpscr
VMSR
fpscr
,
r1
VLDMIA
sp
!
,
{
d0
-
d15
}
VLDMIA
sp
!
,
{
d0
-
d15
}
__no_vfp_frame_ldr_irq
.endif
...
...
@@ -195,7 +195,7 @@ rt_hw_context_switch_interrupt_do
BEQ
__no_vfp_frame_do1
LDMIA
sp
!
,
{
r1
}
; get fpscr
VMSR
fpscr
,
r1
VLDMIA
sp
!
,
{
d0
-
d15
}
VLDMIA
sp
!
,
{
d0
-
d15
}
__no_vfp_frame_do1
.endif
...
...
@@ -219,7 +219,7 @@ __no_vfp_frame_do1
STMDB
sp
!
,
{
r3
}
; push old task's cpsr
.if
(
__TI_VFP_SUPPORT__
)
VMRS
r0
,
fpexc
VMRS
r0
,
fpexc
TST
r0
,
#
0x40000000
BEQ
__no_vfp_frame_do2
VSTMDB
sp
!
,
{
d0
-
d15
}
...
...
@@ -229,7 +229,7 @@ __no_vfp_frame_do1
STMDB
sp
!
,
{
r1
}
__no_vfp_frame_do2
STMDB
sp
!
,
{
r0
}
.endif
.endif
LDR
r4
,
pfromthread
LDR
r5
,
[
r4
]
...
...
@@ -246,7 +246,7 @@ __no_vfp_frame_do2
BEQ
__no_vfp_frame_do3
LDMIA
sp
!
,
{
r1
}
; get fpscr
VMSR
fpscr
,
r1
VLDMIA
sp
!
,
{
d0
-
d15
}
VLDMIA
sp
!
,
{
d0
-
d15
}
__no_vfp_frame_do3
.endif
...
...
libcpu/arm/cortex-r4/context_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -57,10 +57,10 @@ rt_hw_context_switch:
STMDB
sp
!,
{
r4
}
@
push
cpsr
#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
VMRS
r4
,
fpexc
VMRS
r4
,
fpexc
TST
r4
,
#
0x40000000
BEQ
__no_vfp_frame1
VSTMDB
sp
!,
{
d0
-
d15
}
VSTMDB
sp
!,
{
d0
-
d15
}
VMRS
r5
,
fpscr
@
TODO
:
add
support
for
Common
VFPv3
.
@
Save
registers
like
FPINST
,
FPINST2
...
...
@@ -79,7 +79,7 @@ __no_vfp_frame1:
BEQ
__no_vfp_frame2
LDMIA
sp
!,
{
r1
}
@
get
fpscr
VMSR
fpscr
,
r1
VLDMIA
sp
!,
{
d0
-
d15
}
VLDMIA
sp
!,
{
d0
-
d15
}
__no_vfp_frame2
:
#endif
...
...
@@ -103,7 +103,7 @@ rt_hw_context_switch_to:
BEQ
__no_vfp_frame_to
LDMIA
sp
!,
{
r1
}
@
get
fpscr
VMSR
fpscr
,
r1
VLDMIA
sp
!,
{
d0
-
d15
}
VLDMIA
sp
!,
{
d0
-
d15
}
__no_vfp_frame_to
:
#endif
...
...
@@ -137,10 +137,10 @@ IRQ_Handler:
STMDB
sp
!,
{
r0
-
r12
,
lr
}
#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
VMRS
r0
,
fpexc
VMRS
r0
,
fpexc
TST
r0
,
#
0x40000000
BEQ
__no_vfp_frame_str_irq
VSTMDB
sp
!,
{
d0
-
d15
}
VSTMDB
sp
!,
{
d0
-
d15
}
VMRS
r1
,
fpscr
@
TODO
:
add
support
for
Common
VFPv3
.
@
Save
registers
like
FPINST
,
FPINST2
...
...
@@ -167,7 +167,7 @@ __no_vfp_frame_str_irq:
BEQ
__no_vfp_frame_ldr_irq
LDMIA
sp
!,
{
r1
}
@
get
fpscr
VMSR
fpscr
,
r1
VLDMIA
sp
!,
{
d0
-
d15
}
VLDMIA
sp
!,
{
d0
-
d15
}
__no_vfp_frame_ldr_irq
:
#endif
...
...
@@ -189,7 +189,7 @@ rt_hw_context_switch_interrupt_do:
BEQ
__no_vfp_frame_do1
LDMIA
sp
!,
{
r1
}
@
get
fpscr
VMSR
fpscr
,
r1
VLDMIA
sp
!,
{
d0
-
d15
}
VLDMIA
sp
!,
{
d0
-
d15
}
__no_vfp_frame_do1
:
#endif
...
...
@@ -213,7 +213,7 @@ __no_vfp_frame_do1:
STMDB
sp
!,
{
r3
}
@
push
old
task
's cpsr
#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
VMRS
r0
,
fpexc
VMRS
r0
,
fpexc
TST
r0
,
#
0x40000000
BEQ
__no_vfp_frame_do2
VSTMDB
sp
!,
{
d0
-
d15
}
...
...
@@ -240,7 +240,7 @@ __no_vfp_frame_do2:
BEQ
__no_vfp_frame_do3
LDMIA
sp
!,
{
r1
}
@
get
fpscr
VMSR
fpscr
,
r1
VLDMIA
sp
!,
{
d0
-
d15
}
VLDMIA
sp
!,
{
d0
-
d15
}
__no_vfp_frame_do3
:
#endif
...
...
libcpu/arm/cortex-r4/start_ccs.asm
浏览文件 @
563e4989
...
...
@@ -502,42 +502,42 @@ _push_svc_reg .macro
cps
#
0x13
str
sp
,
[
r0
,
#
13
*
4
]
;/* Save calling SP */
str
lr
,
[
r0
,
#
14
*
4
]
;/* Save calling PC */
.endm
.endm
.ref
rt_hw_trap_svc
.def
vector_svc
.ref
rt_hw_trap_svc
.def
vector_svc
.asmfunc
vector_svc:
_push_svc_reg
bl
rt_hw_trap_svc
sub
pc
,
pc
,
#
-
4
sub
pc
,
pc
,
#
-
4
.endasmfunc
.ref
rt_hw_trap_pabt
.def
vector_pabort
.ref
rt_hw_trap_pabt
.def
vector_pabort
.asmfunc
vector_pabort:
_push_svc_reg
bl
rt_hw_trap_pabt
sub
pc
,
pc
,
#
-
4
sub
pc
,
pc
,
#
-
4
.endasmfunc
.ref
rt_hw_trap_dabt
.def
vector_dabort
.ref
rt_hw_trap_dabt
.def
vector_dabort
.asmfunc
vector_dabort:
_push_svc_reg
bl
rt_hw_trap_dabt
sub
pc
,
pc
,
#
-
4
sub
pc
,
pc
,
#
-
4
.endasmfunc
.ref
rt_hw_trap_resv
.def
vector_resv
.ref
rt_hw_trap_resv
.def
vector_resv
.asmfunc
vector_resv:
_push_svc_reg
bl
rt_hw_trap_resv
sub
pc
,
pc
,
#
-
4
sub
pc
,
pc
,
#
-
4
.endasmfunc
;-------------------------------------------------------------------------------
...
...
libcpu/arm/cortex-r4/start_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -462,26 +462,26 @@ turnon_VFP:
str
lr
,
[
r0
,
#
14
*
4
]
@
/*
Save
calling
PC
*/
.
endm
.
globl
vector_svc
.
globl
vector_svc
vector_svc
:
push_svc_reg
bl
rt_hw_trap_svc
b
.
b
.
.
globl
vector_pabort
.
globl
vector_pabort
vector_pabort
:
push_svc_reg
bl
rt_hw_trap_pabt
b
.
b
.
.
globl
vector_dabort
.
globl
vector_dabort
vector_dabort
:
push_svc_reg
bl
rt_hw_trap_dabt
b
.
b
.
.
globl
vector_resv
.
globl
vector_resv
vector_resv
:
push_svc_reg
bl
rt_hw_trap_resv
b
.
b
.
libcpu/arm/dm36x/context_rvds.S
浏览文件 @
563e4989
;/*
; * Copyright (c) 2006-20
18
, RT-Thread Development Team
; * Copyright (c) 2006-20
22
, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
...
...
@@ -8,96 +8,96 @@
; * 2011-08-14 weety copy from mini2440
; */
NOINT
EQU
0xc0
; disable interrupt in psr
NOINT
EQU
0xc0
; disable interrupt in psr
AREA
|.text|
,
CODE
,
READONLY
,
ALIGN
=
2
ARM
REQUIRE8
PRESERVE8
AREA
|.text|
,
CODE
,
READONLY
,
ALIGN
=
2
ARM
REQUIRE8
PRESERVE8
;/*
; * rt_base_t rt_hw_interrupt_disable();
; */
rt_hw_interrupt_disable
PROC
EXPORT
rt_hw_interrupt_disable
MRS
r0
,
cpsr
ORR
r1
,
r0
,
#
NOINT
MSR
cpsr_c
,
r1
BX
lr
ENDP
rt_hw_interrupt_disable
PROC
EXPORT
rt_hw_interrupt_disable
MRS
r0
,
cpsr
ORR
r1
,
r0
,
#
NOINT
MSR
cpsr_c
,
r1
BX
lr
ENDP
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
rt_hw_interrupt_enable
PROC
EXPORT
rt_hw_interrupt_enable
MSR
cpsr_c
,
r0
BX
lr
ENDP
rt_hw_interrupt_enable
PROC
EXPORT
rt_hw_interrupt_enable
MSR
cpsr_c
,
r0
BX
lr
ENDP
;/*
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
; * r0 --> from
; * r1 --> to
; */
rt_hw_context_switch
PROC
EXPORT
rt_hw_context_switch
STMFD
sp
!,
{
lr
}
; push pc (lr should be pushed in place of PC)
STMFD
sp
!,
{
r0
-
r12
,
lr
}
; push lr & register file
rt_hw_context_switch
PROC
EXPORT
rt_hw_context_switch
STMFD
sp
!,
{
lr
}
; push pc (lr should be pushed in place of PC)
STMFD
sp
!,
{
r0
-
r12
,
lr
}
; push lr & register file
MRS
r4
,
cpsr
STMFD
sp
!,
{
r4
}
; push cpsr
MRS
r4
,
spsr
STMFD
sp
!,
{
r4
}
; push spsr
MRS
r4
,
cpsr
STMFD
sp
!,
{
r4
}
; push cpsr
MRS
r4
,
spsr
STMFD
sp
!,
{
r4
}
; push spsr
STR
sp
,
[
r0
]
; store sp in preempted tasks TCB
LDR
sp
,
[
r1
]
; get new task stack pointer
STR
sp
,
[
r0
]
; store sp in preempted tasks TCB
LDR
sp
,
[
r1
]
; get new task stack pointer
LDMFD
sp
!,
{
r4
}
; pop new task spsr
MSR
spsr_cxsf
,
r4
LDMFD
sp
!,
{
r4
}
; pop new task cpsr
MSR
spsr_cxsf
,
r4
LDMFD
sp
!,
{
r4
}
; pop new task spsr
MSR
spsr_cxsf
,
r4
LDMFD
sp
!,
{
r4
}
; pop new task cpsr
MSR
spsr_cxsf
,
r4
LDMFD
sp
!,
{
r0
-
r12
,
lr
,
pc
}^
; pop new task r0-r12, lr & pc
ENDP
LDMFD
sp
!,
{
r0
-
r12
,
lr
,
pc
}^
; pop new task r0-r12, lr & pc
ENDP
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
; * r0 --> to
; */
rt_hw_context_switch_to
PROC
EXPORT
rt_hw_context_switch_to
LDR
sp
,
[
r0
]
; get new task stack pointer
rt_hw_context_switch_to
PROC
EXPORT
rt_hw_context_switch_to
LDR
sp
,
[
r0
]
; get new task stack pointer
LDMFD
sp
!,
{
r4
}
; pop new task spsr
MSR
spsr_cxsf
,
r4
LDMFD
sp
!,
{
r4
}
; pop new task cpsr
MSR
cpsr_cxsf
,
r4
LDMFD
sp
!,
{
r4
}
; pop new task spsr
MSR
spsr_cxsf
,
r4
LDMFD
sp
!,
{
r4
}
; pop new task cpsr
MSR
cpsr_cxsf
,
r4
LDMFD
sp
!,
{
r0
-
r12
,
lr
,
pc
}
; pop new task r0-r12, lr & pc
ENDP
LDMFD
sp
!,
{
r0
-
r12
,
lr
,
pc
}
; pop new task r0-r12, lr & pc
ENDP
;/*
; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
; */
IMPORT
rt_thread_switch_interrupt_flag
IMPORT
rt_interrupt_from_thread
IMPORT
rt_interrupt_to_thread
IMPORT
rt_thread_switch_interrupt_flag
IMPORT
rt_interrupt_from_thread
IMPORT
rt_interrupt_to_thread
rt_hw_context_switch_interrupt
PROC
EXPORT
rt_hw_context_switch_interrupt
LDR
r2
,
=
rt_thread_switch_interrupt_flag
LDR
r3
,
[
r2
]
CMP
r3
,
#
1
BEQ
_reswitch
MOV
r3
,
#
1
; set rt_thread_switch_interrupt_flag to 1
STR
r3
,
[
r2
]
LDR
r2
,
=
rt_interrupt_from_thread
; set rt_interrupt_from_thread
STR
r0
,
[
r2
]
rt_hw_context_switch_interrupt
PROC
EXPORT
rt_hw_context_switch_interrupt
LDR
r2
,
=
rt_thread_switch_interrupt_flag
LDR
r3
,
[
r2
]
CMP
r3
,
#
1
BEQ
_reswitch
MOV
r3
,
#
1
; set rt_thread_switch_interrupt_flag to 1
STR
r3
,
[
r2
]
LDR
r2
,
=
rt_interrupt_from_thread
; set rt_interrupt_from_thread
STR
r0
,
[
r2
]
_reswitch
LDR
r2
,
=
rt_interrupt_to_thread
; set rt_interrupt_to_thread
STR
r1
,
[
r2
]
BX
lr
ENDP
LDR
r2
,
=
rt_interrupt_to_thread
; set rt_interrupt_to_thread
STR
r1
,
[
r2
]
BX
lr
ENDP
END
END
libcpu/arm/lpc214x/context_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -19,22 +19,22 @@
关闭中断,关闭前返回
CPSR
寄存器值
*/
rt_hw_interrupt_disable
:
//
EXPORT
rt_hw_interrupt_disable
MRS
r0
,
cpsr
ORR
r1
,
r0
,
#
NOINT
MSR
cpsr_c
,
r1
BX
lr
//
ENDP
//
EXPORT
rt_hw_interrupt_disable
MRS
r0
,
cpsr
ORR
r1
,
r0
,
#
NOINT
MSR
cpsr_c
,
r1
BX
lr
//
ENDP
/*
*
void
rt_hw_interrupt_enable
(
rt_base_t
level
)
;
恢复中断状态
*/
rt_hw_interrupt_enable
:
//
EXPORT
rt_hw_interrupt_enable
MSR
cpsr_c
,
r0
BX
lr
//
ENDP
//
EXPORT
rt_hw_interrupt_enable
MSR
cpsr_c
,
r0
BX
lr
//
ENDP
/*
*
void
rt_hw_context_switch
(
rt_uint32
from
,
rt_uint32
to
)
;
...
...
@@ -43,68 +43,68 @@ rt_hw_interrupt_enable:
进行线程的上下文切换
*/
rt_hw_context_switch
:
//
EXPORT
rt_hw_context_switch
STMFD
sp
!,
{
lr
}
/*
push
pc
(
lr
should
be
pushed
in
place
of
PC
)
*/
/
*
把
LR
寄存器压入栈(这个函数返回后的下一个执行处)
*/
STMFD
sp
!,
{
r0
-
r12
,
lr
}
/*
push
lr
&
register
file
*/
/
*
把
R0
–
R12
以及
LR
压入栈
*/
//
EXPORT
rt_hw_context_switch
STMFD
sp
!,
{
lr
}
/*
push
pc
(
lr
should
be
pushed
in
place
of
PC
)
*/
/
*
把
LR
寄存器压入栈(这个函数返回后的下一个执行处)
*/
STMFD
sp
!,
{
r0
-
r12
,
lr
}
/*
push
lr
&
register
file
*/
/
*
把
R0
–
R12
以及
LR
压入栈
*/
MRS
r4
,
cpsr
/*
读取
CPSR
寄存器到
R4
寄存器
*/
STMFD
sp
!,
{
r4
}
/*
push
cpsr
*/
/
*
把
R4
寄存器压栈(即上一指令取出的
CPSR
寄存器)
*/
MRS
r4
,
spsr
/*
读取
SPSR
寄存器到
R4
寄存器
*/
STMFD
sp
!,
{
r4
}
/*
push
spsr
*/
/
*
把
R4
寄存器压栈(即
SPSR
寄存器)
*/
MRS
r4
,
cpsr
/*
读取
CPSR
寄存器到
R4
寄存器
*/
STMFD
sp
!,
{
r4
}
/*
push
cpsr
*/
/
*
把
R4
寄存器压栈(即上一指令取出的
CPSR
寄存器)
*/
MRS
r4
,
spsr
/*
读取
SPSR
寄存器到
R4
寄存器
*/
STMFD
sp
!,
{
r4
}
/*
push
spsr
*/
/
*
把
R4
寄存器压栈(即
SPSR
寄存器)
*/
STR
sp
,
[
r0
]
/*
store
sp
in
preempted
tasks
TCB
*/
/
*
把栈指针更新到
TCB
的
sp
,是由
R0
传入此函数
*/
/
*
到这里换出线程的上下文都保存在栈中
*/
LDR
sp
,
[
r1
]
/*
get
new
task
stack
pointer
*/
/
*
载入切换到线程的
TCB
的
sp
*/
/
*
从切换到线程的栈中恢复上下文,次序和保存的时候刚好相反
*/
STR
sp
,
[
r0
]
/*
store
sp
in
preempted
tasks
TCB
*/
/
*
把栈指针更新到
TCB
的
sp
,是由
R0
传入此函数
*/
/
*
到这里换出线程的上下文都保存在栈中
*/
LDR
sp
,
[
r1
]
/*
get
new
task
stack
pointer
*/
/
*
载入切换到线程的
TCB
的
sp
*/
/
*
从切换到线程的栈中恢复上下文,次序和保存的时候刚好相反
*/
LDMFD
sp
!,
{
r4
}
/*
pop
new
task
spsr
*/
/
*
出栈到
R4
寄存器(保存了
SPSR
寄存器)
*/
MSR
spsr_cxsf
,
r4
/*
恢复
SPSR
寄存器
*/
LDMFD
sp
!,
{
r4
}
/*
pop
new
task
cpsr
*/
/
*
出栈到
R4
寄存器(保存了
CPSR
寄存器)
*/
MSR
cpsr_cxsf
,
r4
/*
恢复
CPSR
寄存器
*/
LDMFD
sp
!,
{
r4
}
/*
pop
new
task
spsr
*/
/
*
出栈到
R4
寄存器(保存了
SPSR
寄存器)
*/
MSR
spsr_cxsf
,
r4
/*
恢复
SPSR
寄存器
*/
LDMFD
sp
!,
{
r4
}
/*
pop
new
task
cpsr
*/
/
*
出栈到
R4
寄存器(保存了
CPSR
寄存器)
*/
MSR
cpsr_cxsf
,
r4
/*
恢复
CPSR
寄存器
*/
LDMFD
sp
!,
{
r0
-
r12
,
lr
,
pc
}
/*
pop
new
task
r0
-
r12
,
lr
&
pc
*/
/
*
对
R0
–
R12
及
LR
、
PC
进行恢复
*/
//
ENDP
LDMFD
sp
!,
{
r0
-
r12
,
lr
,
pc
}
/*
pop
new
task
r0
-
r12
,
lr
&
pc
*/
/
*
对
R0
–
R12
及
LR
、
PC
进行恢复
*/
//
ENDP
rt_hw_context_switch_to
:
//
EXPORT
rt_hw_context_switch_to
LDR
sp
,
[
r0
]
/*
get
new
task
stack
pointer
*/
/
*
获得切换到线程的
SP
指针
*/
//
EXPORT
rt_hw_context_switch_to
LDR
sp
,
[
r0
]
/*
get
new
task
stack
pointer
*/
/
*
获得切换到线程的
SP
指针
*/
LDMFD
sp
!,
{
r4
}
/*
pop
new
task
spsr
*/
/
*
出栈
R4
寄存器(保存了
SPSR
寄存器值)
*/
MSR
spsr_cxsf
,
r4
/*
恢复
SPSR
寄存器
*/
LDMFD
sp
!,
{
r4
}
/*
pop
new
task
cpsr
*/
/
*
出栈
R4
寄存器(保存了
CPSR
寄存器值)
*/
MSR
cpsr_cxsf
,
r4
/*
恢复
CPSR
寄存器
*/
LDMFD
sp
!,
{
r4
}
/*
pop
new
task
spsr
*/
/
*
出栈
R4
寄存器(保存了
SPSR
寄存器值)
*/
MSR
spsr_cxsf
,
r4
/*
恢复
SPSR
寄存器
*/
LDMFD
sp
!,
{
r4
}
/*
pop
new
task
cpsr
*/
/
*
出栈
R4
寄存器(保存了
CPSR
寄存器值)
*/
MSR
cpsr_cxsf
,
r4
/*
恢复
CPSR
寄存器
*/
LDMFD
sp
!,
{
r0
-
r12
,
lr
,
pc
}
/*
pop
new
task
r0
-
r12
,
lr
&
pc
*/
/
*
恢复
R0
–
R12
,
LR
及
PC
寄存器
*/
//
ENDP
LDMFD
sp
!,
{
r0
-
r12
,
lr
,
pc
}
/*
pop
new
task
r0
-
r12
,
lr
&
pc
*/
/
*
恢复
R0
–
R12
,
LR
及
PC
寄存器
*/
//
ENDP
rt_hw_context_switch_interrupt
:
//
EXPORT
rt_hw_context_switch_interrupt
LDR
r2
,
=
rt_thread_switch_interrupt_flag
LDR
r3
,
[
r2
]
/*
载入中断中切换标致地址
*/
CMP
r3
,
#
1
/*
等于
1
?
*/
BEQ
_reswitch
/*
如果等于
1
,跳转到
_reswitch
*/
MOV
r3
,
#
1
/*
set
rt_thread_switch_interrupt_flag
to
1
*/
/
*
设置中断中切换标志位
1
*/
STR
r3
,
[
r2
]
/*
*/
LDR
r2
,
=
rt_interrupt_from_thread
/*
set
rt_interrupt_from_thread
*/
STR
r0
,
[
r2
]
/*
保存切换出线程栈指针
*/
//
EXPORT
rt_hw_context_switch_interrupt
LDR
r2
,
=
rt_thread_switch_interrupt_flag
LDR
r3
,
[
r2
]
/*
载入中断中切换标致地址
*/
CMP
r3
,
#
1
/*
等于
1
?
*/
BEQ
_reswitch
/*
如果等于
1
,跳转到
_reswitch
*/
MOV
r3
,
#
1
/*
set
rt_thread_switch_interrupt_flag
to
1
*/
/
*
设置中断中切换标志位
1
*/
STR
r3
,
[
r2
]
/*
*/
LDR
r2
,
=
rt_interrupt_from_thread
/*
set
rt_interrupt_from_thread
*/
STR
r0
,
[
r2
]
/*
保存切换出线程栈指针
*/
_reswitch
:
LDR
r2
,
=
rt_interrupt_to_thread
/*
set
rt_interrupt_to_thread
*/
STR
r1
,
[
r2
]
/*
保存切换到线程栈指针
*/
BX
lr
//
ENDP
LDR
r2
,
=
rt_interrupt_to_thread
/*
set
rt_interrupt_to_thread
*/
STR
r1
,
[
r2
]
/*
保存切换到线程栈指针
*/
BX
lr
//
ENDP
//
END
\ No newline at end of file
//
END
libcpu/arm/lpc214x/context_rvds.S
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libcpu/arm/lpc24xx/context_gcc.S
浏览文件 @
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/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -13,25 +13,25 @@
*/
/*@{*/
#define NOINT
0xc0
#define NOINT
0xc0
/*
*
rt_base_t
rt_hw_interrupt_disable
()
;
*/
.
globl
rt_hw_interrupt_disable
rt_hw_interrupt_disable
:
mrs
r0
,
cpsr
orr
r1
,
r0
,
#
NOINT
msr
cpsr_c
,
r1
mov
pc
,
lr
mrs
r0
,
cpsr
orr
r1
,
r0
,
#
NOINT
msr
cpsr_c
,
r1
mov
pc
,
lr
/*
*
void
rt_hw_interrupt_enable
(
rt_base_t
level
)
;
*/
.
globl
rt_hw_interrupt_enable
rt_hw_interrupt_enable
:
msr
cpsr
,
r0
mov
pc
,
lr
msr
cpsr
,
r0
mov
pc
,
lr
/*
*
void
rt_hw_context_switch
(
rt_uint32
from
,
rt_uint32
to
)
;
...
...
@@ -40,23 +40,23 @@ rt_hw_interrupt_enable:
*/
.
globl
rt_hw_context_switch
rt_hw_context_switch
:
stmfd
sp
!,
{
lr
}
@
push
pc
(
lr
should
be
pushed
in
place
of
PC
)
stmfd
sp
!,
{
r0
-
r12
,
lr
}
@
push
lr
&
register
file
stmfd
sp
!,
{
lr
}
@
push
pc
(
lr
should
be
pushed
in
place
of
PC
)
stmfd
sp
!,
{
r0
-
r12
,
lr
}
@
push
lr
&
register
file
mrs
r4
,
cpsr
stmfd
sp
!,
{
r4
}
@
push
cpsr
mrs
r4
,
spsr
stmfd
sp
!,
{
r4
}
@
push
spsr
mrs
r4
,
cpsr
stmfd
sp
!,
{
r4
}
@
push
cpsr
mrs
r4
,
spsr
stmfd
sp
!,
{
r4
}
@
push
spsr
str
sp
,
[
r0
]
@
store
sp
in
preempted
tasks
TCB
ldr
sp
,
[
r1
]
@
get
new
task
stack
pointer
str
sp
,
[
r0
]
@
store
sp
in
preempted
tasks
TCB
ldr
sp
,
[
r1
]
@
get
new
task
stack
pointer
ldmfd
sp
!,
{
r4
}
@
pop
new
task
spsr
msr
spsr_cxsf
,
r4
ldmfd
sp
!,
{
r4
}
@
pop
new
task
cpsr
msr
cpsr_cxsf
,
r4
ldmfd
sp
!,
{
r4
}
@
pop
new
task
spsr
msr
spsr_cxsf
,
r4
ldmfd
sp
!,
{
r4
}
@
pop
new
task
cpsr
msr
cpsr_cxsf
,
r4
ldmfd
sp
!,
{
r0
-
r12
,
lr
,
pc
}
@
pop
new
task
r0
-
r12
,
lr
&
pc
ldmfd
sp
!,
{
r0
-
r12
,
lr
,
pc
}
@
pop
new
task
r0
-
r12
,
lr
&
pc
/*
*
void
rt_hw_context_switch_to
(
rt_uint32
to
)
;
...
...
@@ -64,14 +64,14 @@ rt_hw_context_switch:
*/
.
globl
rt_hw_context_switch_to
rt_hw_context_switch_to
:
ldr
sp
,
[
r0
]
@
get
new
task
stack
pointer
ldr
sp
,
[
r0
]
@
get
new
task
stack
pointer
ldmfd
sp
!,
{
r4
}
@
pop
new
task
spsr
msr
spsr_cxsf
,
r4
ldmfd
sp
!,
{
r4
}
@
pop
new
task
cpsr
msr
cpsr_cxsf
,
r4
ldmfd
sp
!,
{
r4
}
@
pop
new
task
spsr
msr
spsr_cxsf
,
r4
ldmfd
sp
!,
{
r4
}
@
pop
new
task
cpsr
msr
cpsr_cxsf
,
r4
ldmfd
sp
!,
{
r0
-
r12
,
lr
,
pc
}
@
pop
new
task
r0
-
r12
,
lr
&
pc
ldmfd
sp
!,
{
r0
-
r12
,
lr
,
pc
}
@
pop
new
task
r0
-
r12
,
lr
&
pc
/*
*
void
rt_hw_context_switch_interrupt
(
rt_uint32
from
,
rt_uint32
to
)
;
...
...
@@ -81,15 +81,15 @@ rt_hw_context_switch_to:
.
globl
rt_interrupt_to_thread
.
globl
rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt
:
ldr
r2
,
=
rt_thread_switch_interrupt_flag
ldr
r3
,
[
r2
]
cmp
r3
,
#
1
beq
_reswitch
mov
r3
,
#
1
@
set
rt_thread_switch_interrupt_flag
to
1
str
r3
,
[
r2
]
ldr
r2
,
=
rt_interrupt_from_thread
@
set
rt_interrupt_from_thread
str
r0
,
[
r2
]
ldr
r2
,
=
rt_thread_switch_interrupt_flag
ldr
r3
,
[
r2
]
cmp
r3
,
#
1
beq
_reswitch
mov
r3
,
#
1
@
set
rt_thread_switch_interrupt_flag
to
1
str
r3
,
[
r2
]
ldr
r2
,
=
rt_interrupt_from_thread
@
set
rt_interrupt_from_thread
str
r0
,
[
r2
]
_reswitch
:
ldr
r2
,
=
rt_interrupt_to_thread
@
set
rt_interrupt_to_thread
str
r1
,
[
r2
]
mov
pc
,
lr
ldr
r2
,
=
rt_interrupt_to_thread
@
set
rt_interrupt_to_thread
str
r1
,
[
r2
]
mov
pc
,
lr
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libcpu/arm/realview-a8-vmm/start_gcc.S
浏览文件 @
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/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -245,16 +245,16 @@ switch_to_guest:
ldr
r0
,
[
r1
]
mcr
p15
,
0
,
r0
,
c3
,
c0
#endif
/
*
check
whether
there
is
a
pending
interrupt
for
Guest
OS
*/
bl
vmm_virq_check
/
*
check
whether
there
is
a
pending
interrupt
for
Guest
OS
*/
bl
vmm_virq_check
#ifdef RT_VMM_USING_DOMAIN
@
All
done
,
restore
the
guest
domain
.
mcr
p15
,
0
,
r5
,
c3
,
c0
#endif
cmp
r0
,
#
0x0
beq
route_irq_to_guest
cmp
r0
,
#
0x0
beq
route_irq_to_guest
ldmfd
sp
!,
{
r0
-
r12
,
lr
}
subs
pc
,
lr
,
#
4
...
...
@@ -318,35 +318,35 @@ rt_hw_context_switch_interrupt_do:
.
endm
.
align
5
.
globl
vector_swi
.
globl
vector_swi
vector_swi
:
push_svc_reg
bl
rt_hw_trap_swi
b
.
.
align
5
.
globl
vector_undef
.
globl
vector_undef
vector_undef
:
push_svc_reg
bl
rt_hw_trap_undef
b
.
.
align
5
.
globl
vector_pabt
.
globl
vector_pabt
vector_pabt
:
push_svc_reg
bl
rt_hw_trap_pabt
b
.
.
align
5
.
globl
vector_dabt
.
globl
vector_dabt
vector_dabt
:
push_svc_reg
bl
rt_hw_trap_dabt
b
.
.
align
5
.
globl
vector_resv
.
globl
vector_resv
vector_resv
:
push_svc_reg
bl
rt_hw_trap_resv
...
...
libcpu/arm/realview-a8-vmm/vector_gcc.S
浏览文件 @
563e4989
/*
*
Copyright
(
c
)
2006
-
20
18
,
RT
-
Thread
Development
Team
*
Copyright
(
c
)
2006
-
20
22
,
RT
-
Thread
Development
Team
*
*
SPDX
-
License
-
Identifier
:
Apache
-
2
.0
*
...
...
@@ -49,4 +49,4 @@ _vector_irq:
_vector_fiq
:
.
word
vector_fiq
.
balignl
16,0
xdeadbeef
.
balignl
16,0
xdeadbeef
libcpu/arm/s3c24x0/context_gcc.S
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