* Allow configuration of Ethernet PHY clock source
Refer to https://github.com/espressif/esp-idf/pull/1127
The internal APLL can be used to generate the 50MHz clock for the internal EMAC and the external Ethernet PHY.
The clock can either be input on GPIO0 (as before) or output on GPIO0, GPIO16 or GPIO17 (only GPIO17 extensively tested).
New example available.

* Allow configuration of Ethernet PHY clock source
Refer to https://github.com/espressif/esp-idf/pull/1127
The internal APLL can be used to generate the 50MHz clock for the internal EMAC and the external Ethernet PHY.
The clock can either be input on GPIO0 (as before) or output on GPIO0, GPIO16 or GPIO17 (only GPIO17 extensively tested).
New example available.