Merge branch 'VeriSilicon' into 'master'

add VeriSilicon projects

See merge request codechina/mirrors-settings!533

projects/VeriSilicon/imports.yml

+---
+group:
+  name: 'VeriSilicon'
+  description: ''
+  projects:
+  - name: 'TIM-VX'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+- name: 'tensorflow'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+- name: 'tflite-vx-delegate'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+- name: 'acuitylite'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+- name: 'tvm'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+- name: 'mlcommons-inference'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+- name: 'ffmpeg'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+- name: 'acuity-models'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+- name: 'solios-x-device-plugin'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+- name: 'vpe'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+- name: 'acuity-dataset'
+    description: ''
+    mirrorRelease: false
+    topic: ''
+- name: 'caffe'
+    description: ''
+    mirrorRelease: false
+    topic: ''
\ No newline at end of file